board/freescale/mpc8349itx/mpc8349itx.c

   1 // SPDX-License-Identifier: GPL-2.0+
   2 /*
   3  * Copyright (C) Freescale Semiconductor, Inc. 2006.
   4  */
   5
   6 #include <common.h>
   7 #include <fdt_support.h>
   8 #include <init.h>
   9 #include <ioports.h>
  10 #include <log.h>
  11 #include <mpc83xx.h>
  12 #include <i2c.h>
  13 #include <miiphy.h>
  14 #include <vsc7385.h>
  15 #ifdef CONFIG_PCI
  16 #include <asm/mpc8349_pci.h>
  17 #include <pci.h>
  18 #endif
  19 #include <spd_sdram.h>
  20 #include <asm/bitops.h>
  21 #include <asm/mmu.h>
  22 #if defined(CONFIG_OF_LIBFDT)
  23 #include <linux/libfdt.h>
  24 #endif
  25 #include <linux/delay.h>
  26
  27 #include "../../../arch/powerpc/cpu/mpc83xx/hrcw/hrcw.h"
  28 #include "../../../arch/powerpc/cpu/mpc83xx/elbc/elbc.h"
  29
  30 DECLARE_GLOBAL_DATA_PTR;
  31
  32 #ifndef CONFIG_SPD_EEPROM
  33 /*************************************************************************
  34  *  fixed sdram init -- doesn't use serial presence detect.
  35  ************************************************************************/
  36 int fixed_sdram(void)
  37 {
  38         volatile immap_t *im = (immap_t *) CONFIG_SYS_IMMR;
  39         /* The size of RAM, in bytes */
  40         u32 ddr_size = CONFIG_SYS_DDR_SIZE << 20;
  41         u32 ddr_size_log2 = __ilog2(ddr_size);
  42
  43         im->sysconf.ddrlaw[0].ar =
  44             LAWAR_EN | ((ddr_size_log2 - 1) & LAWAR_SIZE);
  45         im->sysconf.ddrlaw[0].bar = CONFIG_SYS_SDRAM_BASE & 0xfffff000;
  46
  47 #if ((CONFIG_SYS_SDRAM_BASE & 0x00FFFFFF) != 0)
  48 #warning Chip select bounds is only configurable in 16MB increments
  49 #endif
  50         im->ddr.csbnds[0].csbnds =
  51                 ((CONFIG_SYS_SDRAM_BASE >> CSBNDS_SA_SHIFT) & CSBNDS_SA) |
  52                 (((CONFIG_SYS_SDRAM_BASE + ddr_size - 1) >>
  53                                 CSBNDS_EA_SHIFT) & CSBNDS_EA);
  54         im->ddr.cs_config[0] = CONFIG_SYS_DDR_CS0_CONFIG;
  55
  56         /* Only one CS for DDR */
  57         im->ddr.cs_config[1] = 0;
  58         im->ddr.cs_config[2] = 0;
  59         im->ddr.cs_config[3] = 0;
  60
  61         debug("cs0_bnds = 0x%08x\n", im->ddr.csbnds[0].csbnds);
  62         debug("cs0_config = 0x%08x\n", im->ddr.cs_config[0]);
  63
  64         debug("DDR:bar=0x%08x\n", im->sysconf.ddrlaw[0].bar);
  65         debug("DDR:ar=0x%08x\n", im->sysconf.ddrlaw[0].ar);
  66
  67         im->ddr.timing_cfg_1 = CONFIG_SYS_DDR_TIMING_1;
  68         im->ddr.timing_cfg_2 = CONFIG_SYS_DDR_TIMING_2;/* Was "2 << TIMING_CFG2_WR_DATA_DELAY_SHIFT" */
  69         im->ddr.sdram_cfg = SDRAM_CFG_SREN | SDRAM_CFG_SDRAM_TYPE_DDR1;
  70         im->ddr.sdram_mode =
  71             (0x0000 << SDRAM_MODE_ESD_SHIFT) | (0x0032 << SDRAM_MODE_SD_SHIFT);
  72         im->ddr.sdram_interval =
  73             (0x0410 << SDRAM_INTERVAL_REFINT_SHIFT) | (0x0100 <<
  74                                                        SDRAM_INTERVAL_BSTOPRE_SHIFT);
  75         im->ddr.sdram_clk_cntl = CONFIG_SYS_DDR_SDRAM_CLK_CNTL;
  76
  77         udelay(200);
  78
  79         im->ddr.sdram_cfg |= SDRAM_CFG_MEM_EN;
  80
  81         debug("DDR:timing_cfg_1=0x%08x\n", im->ddr.timing_cfg_1);
  82         debug("DDR:timing_cfg_2=0x%08x\n", im->ddr.timing_cfg_2);
  83         debug("DDR:sdram_mode=0x%08x\n", im->ddr.sdram_mode);
  84         debug("DDR:sdram_interval=0x%08x\n", im->ddr.sdram_interval);
  85         debug("DDR:sdram_cfg=0x%08x\n", im->ddr.sdram_cfg);
  86
  87         return CONFIG_SYS_DDR_SIZE;
  88 }
  89 #endif
  90
  91 #ifdef CONFIG_PCI
  92 /*
  93  * Initialize PCI Devices, report devices found
  94  */
  95 #ifndef CONFIG_PCI_PNP
  96 static struct pci_config_table pci_mpc83xxmitx_config_table[] = {
  97         {
  98          PCI_ANY_ID,
  99          PCI_ANY_ID,
 100          PCI_ANY_ID,
 101          PCI_ANY_ID,
 102          0x0f,
 103          PCI_ANY_ID,
 104          pci_cfgfunc_config_device,
 105          {
 106           PCI_ENET0_IOADDR,
 107           PCI_ENET0_MEMADDR,
 108           PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER}
 109          },
 110         {}
 111 }
 112 #endif
 113
 114 volatile static struct pci_controller hose[] = {
 115         {
 116 #ifndef CONFIG_PCI_PNP
 117               config_table:pci_mpc83xxmitx_config_table,
 118 #endif
 119          },
 120         {
 121 #ifndef CONFIG_PCI_PNP
 122               config_table:pci_mpc83xxmitx_config_table,
 123 #endif
 124          }
 125 };
 126 #endif                          /* CONFIG_PCI */
 127
 128 int dram_init(void)
 129 {
 130         volatile immap_t *im = (immap_t *) CONFIG_SYS_IMMR;
 131         u32 msize = 0;
 132 #ifdef CONFIG_DDR_ECC
 133         volatile ddr83xx_t *ddr = &im->ddr;
 134 #endif
 135
 136         if ((im->sysconf.immrbar & IMMRBAR_BASE_ADDR) != (u32) im)
 137                 return -ENXIO;
 138
 139         /* DDR SDRAM - Main SODIMM */
 140         im->sysconf.ddrlaw[0].bar = CONFIG_SYS_SDRAM_BASE & LAWBAR_BAR;
 141 #ifdef CONFIG_SPD_EEPROM
 142         msize = spd_sdram();
 143 #else
 144         msize = fixed_sdram();
 145 #endif
 146
 147 #ifdef CONFIG_DDR_ECC
 148         if (ddr->sdram_cfg & SDRAM_CFG_ECC_EN)
 149                 /* Unlike every other board, on the 83xx spd_sdram() returns
 150                    megabytes instead of just bytes.  That's why we need to
 151                    multiple by 1MB when calling ddr_enable_ecc(). */
 152                 ddr_enable_ecc(msize * 1048576);
 153 #endif
 154
 155         /* return total bus RAM size(bytes) */
 156         gd->ram_size = msize * 1024 * 1024;
 157
 158         return 0;
 159 }
 160
 161 int checkboard(void)
 162 {
 163 #ifdef CONFIG_TARGET_MPC8349ITX
 164         puts("Board: Freescale MPC8349E-mITX\n");
 165 #else
 166         puts("Board: Freescale MPC8349E-mITX-GP\n");
 167 #endif
 168
 169         return 0;
 170 }
 171
 172 /*
 173  * Implement a work-around for a hardware problem with compact
 174  * flash.
 175  *
 176  * Program the UPM if compact flash is enabled.
 177  */
 178 int misc_init_f(void)
 179 {
 180 #ifdef CONFIG_VSC7385_ENET
 181         volatile u32 *vsc7385_cpuctrl;
 182
 183         /* 0x1c0c0 is the VSC7385 CPU Control (CPUCTRL) Register.  The power up
 184            default of VSC7385 L1_IRQ and L2_IRQ requests are active high.  That
 185            means it is 0 when the IRQ is not active.  This makes the wire-AND
 186            logic always assert IRQ7 to CPU even if there is no request from the
 187            switch.  Since the compact flash and the switch share the same IRQ,
 188            the Linux kernel will think that the compact flash is requesting irq
 189            and get stuck when it tries to clear the IRQ.  Thus we need to set
 190            the L2_IRQ0 and L2_IRQ1 to active low.
 191
 192            The following code sets the L1_IRQ and L2_IRQ polarity to active low.
 193            Without this code, compact flash will not work in Linux because
 194            unlike U-Boot, Linux uses the IRQ, so this code is necessary if we
 195            don't enable compact flash for U-Boot.
 196          */
 197
 198         vsc7385_cpuctrl = (volatile u32 *)(CONFIG_SYS_VSC7385_BASE + 0x1c0c0);
 199         *vsc7385_cpuctrl |= 0x0c;
 200 #endif
 201
 202 #ifdef CONFIG_COMPACT_FLASH
 203         /* UPM Table Configuration Code */
 204         static uint UPMATable[] = {
 205                 0xcffffc00, 0x0fffff00, 0x0fafff00, 0x0fafff00,
 206                 0x0faffd00, 0x0faffc04, 0x0ffffc00, 0x3ffffc01,
 207                 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00,
 208                 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00,
 209                 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfff7fc00,
 210                 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc01,
 211                 0xcffffc00, 0x0fffff00, 0x0ff3ff00, 0x0ff3ff00,
 212                 0x0ff3fe00, 0x0ffffc00, 0x3ffffc05, 0xfffffc00,
 213                 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00,
 214                 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00,
 215                 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00,
 216                 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc01,
 217                 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00,
 218                 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00,
 219                 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc01,
 220                 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc01
 221         };
 222         volatile immap_t *immap = (immap_t *) CONFIG_SYS_IMMR;
 223
 224         set_lbc_br(3, CONFIG_SYS_BR3_PRELIM);
 225         set_lbc_or(3, CONFIG_SYS_OR3_PRELIM);
 226
 227         /* Program the MAMR. RFEN=0, OP=00, UWPL=1, AM=000, DS=01, G0CL=000,
 228            GPL4=0, RLF=0001, WLF=0001, TLF=0001, MAD=000000
 229          */
 230         immap->im_lbc.mamr = 0x08404440;
 231
 232         upmconfig(0, UPMATable, sizeof(UPMATable) / sizeof(UPMATable[0]));
 233
 234         puts("UPMA:  Configured for compact flash\n");
 235 #endif
 236
 237         return 0;
 238 }
 239
 240 /*
 241  * Miscellaneous late-boot configurations
 242  *
 243  * Make sure the EEPROM has the HRCW correctly programmed.
 244  * Make sure the RTC is correctly programmed.
 245  *
 246  * The MPC8349E-mITX can be configured to load the HRCW from
 247  * EEPROM instead of flash.  This is controlled via jumpers
 248  * LGPL0, 1, and 3.  Normally, these jumpers are set to 000 (all
 249  * jumpered), but if they're set to 001 or 010, then the HRCW is
 250  * read from the "I2C EEPROM".
 251  *
 252  * This function makes sure that the I2C EEPROM is programmed
 253  * correctly.
 254  *
 255  * If a VSC7385 microcode image is present, then upload it.
 256  */
 257 int misc_init_r(void)
 258 {
 259         int rc = 0;
 260
 261 #if defined(CONFIG_SYS_I2C)
 262         unsigned int orig_bus = i2c_get_bus_num();
 263         u8 i2c_data;
 264
 265 #ifdef CONFIG_SYS_I2C_RTC_ADDR
 266         u8 ds1339_data[17];
 267 #endif
 268
 269 #ifdef CONFIG_SYS_I2C_EEPROM_ADDR
 270         static u8 eeprom_data[] =       /* HRCW data */
 271         {
 272                 0xAA, 0x55, 0xAA,       /* Preamble */
 273                 0x7C,                   /* ACS=0, BYTE_EN=1111, CONT=1 */
 274                 0x02, 0x40,             /* RCWL ADDR=0x0_0900 */
 275                 (CONFIG_SYS_HRCW_LOW >> 24) & 0xFF,
 276                 (CONFIG_SYS_HRCW_LOW >> 16) & 0xFF,
 277                 (CONFIG_SYS_HRCW_LOW >> 8) & 0xFF,
 278                 CONFIG_SYS_HRCW_LOW & 0xFF,
 279                 0x7C,                   /* ACS=0, BYTE_EN=1111, CONT=1 */
 280                 0x02, 0x41,             /* RCWH ADDR=0x0_0904 */
 281                 (CONFIG_SYS_HRCW_HIGH >> 24) & 0xFF,
 282                 (CONFIG_SYS_HRCW_HIGH >> 16) & 0xFF,
 283                 (CONFIG_SYS_HRCW_HIGH >> 8) & 0xFF,
 284                 CONFIG_SYS_HRCW_HIGH & 0xFF
 285         };
 286
 287         u8 data[sizeof(eeprom_data)];
 288 #endif
 289
 290         printf("Board revision: ");
 291         i2c_set_bus_num(1);
 292         if (i2c_read(CONFIG_SYS_I2C_8574A_ADDR2, 0, 0, &i2c_data, sizeof(i2c_data)) == 0)
 293                 printf("%u.%u (PCF8475A)\n", (i2c_data & 0x02) >> 1, i2c_data & 0x01);
 294         else if (i2c_read(CONFIG_SYS_I2C_8574_ADDR2, 0, 0, &i2c_data, sizeof(i2c_data)) == 0)
 295                 printf("%u.%u (PCF8475)\n",  (i2c_data & 0x02) >> 1, i2c_data & 0x01);
 296         else {
 297                 printf("Unknown\n");
 298                 rc = 1;
 299         }
 300
 301 #ifdef CONFIG_SYS_I2C_EEPROM_ADDR
 302         i2c_set_bus_num(0);
 303
 304         if (i2c_read(CONFIG_SYS_I2C_EEPROM_ADDR, 0, 2, data, sizeof(data)) == 0) {
 305                 if (memcmp(data, eeprom_data, sizeof(data)) != 0) {
 306                         if (i2c_write
 307                             (CONFIG_SYS_I2C_EEPROM_ADDR, 0, 2, eeprom_data,
 308                              sizeof(eeprom_data)) != 0) {
 309                                 puts("Failure writing the HRCW to EEPROM via I2C.\n");
 310                                 rc = 1;
 311                         }
 312                 }
 313         } else {
 314                 puts("Failure reading the HRCW from EEPROM via I2C.\n");
 315                 rc = 1;
 316         }
 317 #endif
 318
 319 #ifdef CONFIG_SYS_I2C_RTC_ADDR
 320         i2c_set_bus_num(1);
 321
 322         if (i2c_read(CONFIG_SYS_I2C_RTC_ADDR, 0, 1, ds1339_data, sizeof(ds1339_data))
 323             == 0) {
 324
 325                 /* Work-around for MPC8349E-mITX bug #13601.
 326                    If the RTC does not contain valid register values, the DS1339
 327                    Linux driver will not work.
 328                  */
 329
 330                 /* Make sure status register bits 6-2 are zero */
 331                 ds1339_data[0x0f] &= ~0x7c;
 332
 333                 /* Check for a valid day register value */
 334                 ds1339_data[0x03] &= ~0xf8;
 335                 if (ds1339_data[0x03] == 0) {
 336                         ds1339_data[0x03] = 1;
 337                 }
 338
 339                 /* Check for a valid date register value */
 340                 ds1339_data[0x04] &= ~0xc0;
 341                 if ((ds1339_data[0x04] == 0) ||
 342                     ((ds1339_data[0x04] & 0x0f) > 9) ||
 343                     (ds1339_data[0x04] >= 0x32)) {
 344                         ds1339_data[0x04] = 1;
 345                 }
 346
 347                 /* Check for a valid month register value */
 348                 ds1339_data[0x05] &= ~0x60;
 349
 350                 if ((ds1339_data[0x05] == 0) ||
 351                     ((ds1339_data[0x05] & 0x0f) > 9) ||
 352                     ((ds1339_data[0x05] >= 0x13)
 353                      && (ds1339_data[0x05] <= 0x19))) {
 354                         ds1339_data[0x05] = 1;
 355                 }
 356
 357                 /* Enable Oscillator and rate select */
 358                 ds1339_data[0x0e] = 0x1c;
 359
 360                 /* Work-around for MPC8349E-mITX bug #13330.
 361                    Ensure that the RTC control register contains the value 0x1c.
 362                    This affects SATA performance.
 363                  */
 364
 365                 if (i2c_write
 366                     (CONFIG_SYS_I2C_RTC_ADDR, 0, 1, ds1339_data,
 367                      sizeof(ds1339_data))) {
 368                         puts("Failure writing to the RTC via I2C.\n");
 369                         rc = 1;
 370                 }
 371         } else {
 372                 puts("Failure reading from the RTC via I2C.\n");
 373                 rc = 1;
 374         }
 375 #endif
 376
 377         i2c_set_bus_num(orig_bus);
 378 #endif
 379
 380 #ifdef CONFIG_VSC7385_IMAGE
 381         if (vsc7385_upload_firmware((void *) CONFIG_VSC7385_IMAGE,
 382                 CONFIG_VSC7385_IMAGE_SIZE)) {
 383                 puts("Failure uploading VSC7385 microcode.\n");
 384                 rc = 1;
 385         }
 386 #endif
 387
 388         return rc;
 389 }
 390
 391 #if defined(CONFIG_OF_BOARD_SETUP)
 392 int ft_board_setup(void *blob, struct bd_info *bd)
 393 {
 394         ft_cpu_setup(blob, bd);
 395 #ifdef CONFIG_PCI
 396         ft_pci_setup(blob, bd);
 397 #endif
 398
 399         return 0;
 400 }
 401 #endif