board/freescale/mpc8349itx/mpc8349itx.c

   1 // SPDX-License-Identifier: GPL-2.0+
   2 /*
   3  * Copyright (C) Freescale Semiconductor, Inc. 2006.
   4  */
   5
   6 #include <common.h>
   7 #include <fdt_support.h>
   8 #include <init.h>
   9 #include <ioports.h>
  10 #include <mpc83xx.h>
  11 #include <i2c.h>
  12 #include <miiphy.h>
  13 #include <vsc7385.h>
  14 #ifdef CONFIG_PCI
  15 #include <asm/mpc8349_pci.h>
  16 #include <pci.h>
  17 #endif
  18 #include <spd_sdram.h>
  19 #include <asm/mmu.h>
  20 #if defined(CONFIG_OF_LIBFDT)
  21 #include <linux/libfdt.h>
  22 #endif
  23
  24 #include "../../../arch/powerpc/cpu/mpc83xx/hrcw/hrcw.h"
  25 #include "../../../arch/powerpc/cpu/mpc83xx/elbc/elbc.h"
  26
  27 DECLARE_GLOBAL_DATA_PTR;
  28
  29 #ifndef CONFIG_SPD_EEPROM
  30 /*************************************************************************
  31  *  fixed sdram init -- doesn't use serial presence detect.
  32  ************************************************************************/
  33 int fixed_sdram(void)
  34 {
  35         volatile immap_t *im = (immap_t *) CONFIG_SYS_IMMR;
  36         /* The size of RAM, in bytes */
  37         u32 ddr_size = CONFIG_SYS_DDR_SIZE << 20;
  38         u32 ddr_size_log2 = __ilog2(ddr_size);
  39
  40         im->sysconf.ddrlaw[0].ar =
  41             LAWAR_EN | ((ddr_size_log2 - 1) & LAWAR_SIZE);
  42         im->sysconf.ddrlaw[0].bar = CONFIG_SYS_SDRAM_BASE & 0xfffff000;
  43
  44 #if ((CONFIG_SYS_SDRAM_BASE & 0x00FFFFFF) != 0)
  45 #warning Chip select bounds is only configurable in 16MB increments
  46 #endif
  47         im->ddr.csbnds[0].csbnds =
  48                 ((CONFIG_SYS_SDRAM_BASE >> CSBNDS_SA_SHIFT) & CSBNDS_SA) |
  49                 (((CONFIG_SYS_SDRAM_BASE + ddr_size - 1) >>
  50                                 CSBNDS_EA_SHIFT) & CSBNDS_EA);
  51         im->ddr.cs_config[0] = CONFIG_SYS_DDR_CS0_CONFIG;
  52
  53         /* Only one CS for DDR */
  54         im->ddr.cs_config[1] = 0;
  55         im->ddr.cs_config[2] = 0;
  56         im->ddr.cs_config[3] = 0;
  57
  58         debug("cs0_bnds = 0x%08x\n", im->ddr.csbnds[0].csbnds);
  59         debug("cs0_config = 0x%08x\n", im->ddr.cs_config[0]);
  60
  61         debug("DDR:bar=0x%08x\n", im->sysconf.ddrlaw[0].bar);
  62         debug("DDR:ar=0x%08x\n", im->sysconf.ddrlaw[0].ar);
  63
  64         im->ddr.timing_cfg_1 = CONFIG_SYS_DDR_TIMING_1;
  65         im->ddr.timing_cfg_2 = CONFIG_SYS_DDR_TIMING_2;/* Was "2 << TIMING_CFG2_WR_DATA_DELAY_SHIFT" */
  66         im->ddr.sdram_cfg = SDRAM_CFG_SREN | SDRAM_CFG_SDRAM_TYPE_DDR1;
  67         im->ddr.sdram_mode =
  68             (0x0000 << SDRAM_MODE_ESD_SHIFT) | (0x0032 << SDRAM_MODE_SD_SHIFT);
  69         im->ddr.sdram_interval =
  70             (0x0410 << SDRAM_INTERVAL_REFINT_SHIFT) | (0x0100 <<
  71                                                        SDRAM_INTERVAL_BSTOPRE_SHIFT);
  72         im->ddr.sdram_clk_cntl = CONFIG_SYS_DDR_SDRAM_CLK_CNTL;
  73
  74         udelay(200);
  75
  76         im->ddr.sdram_cfg |= SDRAM_CFG_MEM_EN;
  77
  78         debug("DDR:timing_cfg_1=0x%08x\n", im->ddr.timing_cfg_1);
  79         debug("DDR:timing_cfg_2=0x%08x\n", im->ddr.timing_cfg_2);
  80         debug("DDR:sdram_mode=0x%08x\n", im->ddr.sdram_mode);
  81         debug("DDR:sdram_interval=0x%08x\n", im->ddr.sdram_interval);
  82         debug("DDR:sdram_cfg=0x%08x\n", im->ddr.sdram_cfg);
  83
  84         return CONFIG_SYS_DDR_SIZE;
  85 }
  86 #endif
  87
  88 #ifdef CONFIG_PCI
  89 /*
  90  * Initialize PCI Devices, report devices found
  91  */
  92 #ifndef CONFIG_PCI_PNP
  93 static struct pci_config_table pci_mpc83xxmitx_config_table[] = {
  94         {
  95          PCI_ANY_ID,
  96          PCI_ANY_ID,
  97          PCI_ANY_ID,
  98          PCI_ANY_ID,
  99          0x0f,
 100          PCI_ANY_ID,
 101          pci_cfgfunc_config_device,
 102          {
 103           PCI_ENET0_IOADDR,
 104           PCI_ENET0_MEMADDR,
 105           PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER}
 106          },
 107         {}
 108 }
 109 #endif
 110
 111 volatile static struct pci_controller hose[] = {
 112         {
 113 #ifndef CONFIG_PCI_PNP
 114               config_table:pci_mpc83xxmitx_config_table,
 115 #endif
 116          },
 117         {
 118 #ifndef CONFIG_PCI_PNP
 119               config_table:pci_mpc83xxmitx_config_table,
 120 #endif
 121          }
 122 };
 123 #endif                          /* CONFIG_PCI */
 124
 125 int dram_init(void)
 126 {
 127         volatile immap_t *im = (immap_t *) CONFIG_SYS_IMMR;
 128         u32 msize = 0;
 129 #ifdef CONFIG_DDR_ECC
 130         volatile ddr83xx_t *ddr = &im->ddr;
 131 #endif
 132
 133         if ((im->sysconf.immrbar & IMMRBAR_BASE_ADDR) != (u32) im)
 134                 return -ENXIO;
 135
 136         /* DDR SDRAM - Main SODIMM */
 137         im->sysconf.ddrlaw[0].bar = CONFIG_SYS_SDRAM_BASE & LAWBAR_BAR;
 138 #ifdef CONFIG_SPD_EEPROM
 139         msize = spd_sdram();
 140 #else
 141         msize = fixed_sdram();
 142 #endif
 143
 144 #ifdef CONFIG_DDR_ECC
 145         if (ddr->sdram_cfg & SDRAM_CFG_ECC_EN)
 146                 /* Unlike every other board, on the 83xx spd_sdram() returns
 147                    megabytes instead of just bytes.  That's why we need to
 148                    multiple by 1MB when calling ddr_enable_ecc(). */
 149                 ddr_enable_ecc(msize * 1048576);
 150 #endif
 151
 152         /* return total bus RAM size(bytes) */
 153         gd->ram_size = msize * 1024 * 1024;
 154
 155         return 0;
 156 }
 157
 158 int checkboard(void)
 159 {
 160 #ifdef CONFIG_TARGET_MPC8349ITX
 161         puts("Board: Freescale MPC8349E-mITX\n");
 162 #else
 163         puts("Board: Freescale MPC8349E-mITX-GP\n");
 164 #endif
 165
 166         return 0;
 167 }
 168
 169 /*
 170  * Implement a work-around for a hardware problem with compact
 171  * flash.
 172  *
 173  * Program the UPM if compact flash is enabled.
 174  */
 175 int misc_init_f(void)
 176 {
 177 #ifdef CONFIG_VSC7385_ENET
 178         volatile u32 *vsc7385_cpuctrl;
 179
 180         /* 0x1c0c0 is the VSC7385 CPU Control (CPUCTRL) Register.  The power up
 181            default of VSC7385 L1_IRQ and L2_IRQ requests are active high.  That
 182            means it is 0 when the IRQ is not active.  This makes the wire-AND
 183            logic always assert IRQ7 to CPU even if there is no request from the
 184            switch.  Since the compact flash and the switch share the same IRQ,
 185            the Linux kernel will think that the compact flash is requesting irq
 186            and get stuck when it tries to clear the IRQ.  Thus we need to set
 187            the L2_IRQ0 and L2_IRQ1 to active low.
 188
 189            The following code sets the L1_IRQ and L2_IRQ polarity to active low.
 190            Without this code, compact flash will not work in Linux because
 191            unlike U-Boot, Linux uses the IRQ, so this code is necessary if we
 192            don't enable compact flash for U-Boot.
 193          */
 194
 195         vsc7385_cpuctrl = (volatile u32 *)(CONFIG_SYS_VSC7385_BASE + 0x1c0c0);
 196         *vsc7385_cpuctrl |= 0x0c;
 197 #endif
 198
 199 #ifdef CONFIG_COMPACT_FLASH
 200         /* UPM Table Configuration Code */
 201         static uint UPMATable[] = {
 202                 0xcffffc00, 0x0fffff00, 0x0fafff00, 0x0fafff00,
 203                 0x0faffd00, 0x0faffc04, 0x0ffffc00, 0x3ffffc01,
 204                 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00,
 205                 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00,
 206                 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfff7fc00,
 207                 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc01,
 208                 0xcffffc00, 0x0fffff00, 0x0ff3ff00, 0x0ff3ff00,
 209                 0x0ff3fe00, 0x0ffffc00, 0x3ffffc05, 0xfffffc00,
 210                 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00,
 211                 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00,
 212                 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00,
 213                 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc01,
 214                 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00,
 215                 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00,
 216                 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc01,
 217                 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc01
 218         };
 219         volatile immap_t *immap = (immap_t *) CONFIG_SYS_IMMR;
 220
 221         set_lbc_br(3, CONFIG_SYS_BR3_PRELIM);
 222         set_lbc_or(3, CONFIG_SYS_OR3_PRELIM);
 223
 224         /* Program the MAMR. RFEN=0, OP=00, UWPL=1, AM=000, DS=01, G0CL=000,
 225            GPL4=0, RLF=0001, WLF=0001, TLF=0001, MAD=000000
 226          */
 227         immap->im_lbc.mamr = 0x08404440;
 228
 229         upmconfig(0, UPMATable, sizeof(UPMATable) / sizeof(UPMATable[0]));
 230
 231         puts("UPMA:  Configured for compact flash\n");
 232 #endif
 233
 234         return 0;
 235 }
 236
 237 /*
 238  * Miscellaneous late-boot configurations
 239  *
 240  * Make sure the EEPROM has the HRCW correctly programmed.
 241  * Make sure the RTC is correctly programmed.
 242  *
 243  * The MPC8349E-mITX can be configured to load the HRCW from
 244  * EEPROM instead of flash.  This is controlled via jumpers
 245  * LGPL0, 1, and 3.  Normally, these jumpers are set to 000 (all
 246  * jumpered), but if they're set to 001 or 010, then the HRCW is
 247  * read from the "I2C EEPROM".
 248  *
 249  * This function makes sure that the I2C EEPROM is programmed
 250  * correctly.
 251  *
 252  * If a VSC7385 microcode image is present, then upload it.
 253  */
 254 int misc_init_r(void)
 255 {
 256         int rc = 0;
 257
 258 #if defined(CONFIG_SYS_I2C)
 259         unsigned int orig_bus = i2c_get_bus_num();
 260         u8 i2c_data;
 261
 262 #ifdef CONFIG_SYS_I2C_RTC_ADDR
 263         u8 ds1339_data[17];
 264 #endif
 265
 266 #ifdef CONFIG_SYS_I2C_EEPROM_ADDR
 267         static u8 eeprom_data[] =       /* HRCW data */
 268         {
 269                 0xAA, 0x55, 0xAA,       /* Preamble */
 270                 0x7C,                   /* ACS=0, BYTE_EN=1111, CONT=1 */
 271                 0x02, 0x40,             /* RCWL ADDR=0x0_0900 */
 272                 (CONFIG_SYS_HRCW_LOW >> 24) & 0xFF,
 273                 (CONFIG_SYS_HRCW_LOW >> 16) & 0xFF,
 274                 (CONFIG_SYS_HRCW_LOW >> 8) & 0xFF,
 275                 CONFIG_SYS_HRCW_LOW & 0xFF,
 276                 0x7C,                   /* ACS=0, BYTE_EN=1111, CONT=1 */
 277                 0x02, 0x41,             /* RCWH ADDR=0x0_0904 */
 278                 (CONFIG_SYS_HRCW_HIGH >> 24) & 0xFF,
 279                 (CONFIG_SYS_HRCW_HIGH >> 16) & 0xFF,
 280                 (CONFIG_SYS_HRCW_HIGH >> 8) & 0xFF,
 281                 CONFIG_SYS_HRCW_HIGH & 0xFF
 282         };
 283
 284         u8 data[sizeof(eeprom_data)];
 285 #endif
 286
 287         printf("Board revision: ");
 288         i2c_set_bus_num(1);
 289         if (i2c_read(CONFIG_SYS_I2C_8574A_ADDR2, 0, 0, &i2c_data, sizeof(i2c_data)) == 0)
 290                 printf("%u.%u (PCF8475A)\n", (i2c_data & 0x02) >> 1, i2c_data & 0x01);
 291         else if (i2c_read(CONFIG_SYS_I2C_8574_ADDR2, 0, 0, &i2c_data, sizeof(i2c_data)) == 0)
 292                 printf("%u.%u (PCF8475)\n",  (i2c_data & 0x02) >> 1, i2c_data & 0x01);
 293         else {
 294                 printf("Unknown\n");
 295                 rc = 1;
 296         }
 297
 298 #ifdef CONFIG_SYS_I2C_EEPROM_ADDR
 299         i2c_set_bus_num(0);
 300
 301         if (i2c_read(CONFIG_SYS_I2C_EEPROM_ADDR, 0, 2, data, sizeof(data)) == 0) {
 302                 if (memcmp(data, eeprom_data, sizeof(data)) != 0) {
 303                         if (i2c_write
 304                             (CONFIG_SYS_I2C_EEPROM_ADDR, 0, 2, eeprom_data,
 305                              sizeof(eeprom_data)) != 0) {
 306                                 puts("Failure writing the HRCW to EEPROM via I2C.\n");
 307                                 rc = 1;
 308                         }
 309                 }
 310         } else {
 311                 puts("Failure reading the HRCW from EEPROM via I2C.\n");
 312                 rc = 1;
 313         }
 314 #endif
 315
 316 #ifdef CONFIG_SYS_I2C_RTC_ADDR
 317         i2c_set_bus_num(1);
 318
 319         if (i2c_read(CONFIG_SYS_I2C_RTC_ADDR, 0, 1, ds1339_data, sizeof(ds1339_data))
 320             == 0) {
 321
 322                 /* Work-around for MPC8349E-mITX bug #13601.
 323                    If the RTC does not contain valid register values, the DS1339
 324                    Linux driver will not work.
 325                  */
 326
 327                 /* Make sure status register bits 6-2 are zero */
 328                 ds1339_data[0x0f] &= ~0x7c;
 329
 330                 /* Check for a valid day register value */
 331                 ds1339_data[0x03] &= ~0xf8;
 332                 if (ds1339_data[0x03] == 0) {
 333                         ds1339_data[0x03] = 1;
 334                 }
 335
 336                 /* Check for a valid date register value */
 337                 ds1339_data[0x04] &= ~0xc0;
 338                 if ((ds1339_data[0x04] == 0) ||
 339                     ((ds1339_data[0x04] & 0x0f) > 9) ||
 340                     (ds1339_data[0x04] >= 0x32)) {
 341                         ds1339_data[0x04] = 1;
 342                 }
 343
 344                 /* Check for a valid month register value */
 345                 ds1339_data[0x05] &= ~0x60;
 346
 347                 if ((ds1339_data[0x05] == 0) ||
 348                     ((ds1339_data[0x05] & 0x0f) > 9) ||
 349                     ((ds1339_data[0x05] >= 0x13)
 350                      && (ds1339_data[0x05] <= 0x19))) {
 351                         ds1339_data[0x05] = 1;
 352                 }
 353
 354                 /* Enable Oscillator and rate select */
 355                 ds1339_data[0x0e] = 0x1c;
 356
 357                 /* Work-around for MPC8349E-mITX bug #13330.
 358                    Ensure that the RTC control register contains the value 0x1c.
 359                    This affects SATA performance.
 360                  */
 361
 362                 if (i2c_write
 363                     (CONFIG_SYS_I2C_RTC_ADDR, 0, 1, ds1339_data,
 364                      sizeof(ds1339_data))) {
 365                         puts("Failure writing to the RTC via I2C.\n");
 366                         rc = 1;
 367                 }
 368         } else {
 369                 puts("Failure reading from the RTC via I2C.\n");
 370                 rc = 1;
 371         }
 372 #endif
 373
 374         i2c_set_bus_num(orig_bus);
 375 #endif
 376
 377 #ifdef CONFIG_VSC7385_IMAGE
 378         if (vsc7385_upload_firmware((void *) CONFIG_VSC7385_IMAGE,
 379                 CONFIG_VSC7385_IMAGE_SIZE)) {
 380                 puts("Failure uploading VSC7385 microcode.\n");
 381                 rc = 1;
 382         }
 383 #endif
 384
 385         return rc;
 386 }
 387
 388 #if defined(CONFIG_OF_BOARD_SETUP)
 389 int ft_board_setup(void *blob, bd_t *bd)
 390 {
 391         ft_cpu_setup(blob, bd);
 392 #ifdef CONFIG_PCI
 393         ft_pci_setup(blob, bd);
 394 #endif
 395
 396         return 0;
 397 }
 398 #endif