1 // SPDX-License-Identifier: GPL-2.0+
4 * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
8 #include <fdt_support.h>
12 #include <asm/mpc8349_pci.h>
16 #ifdef CONFIG_SYS_FSL_DDR2
17 #include <fsl_ddr_sdram.h>
19 #include <spd_sdram.h>
21 #include <linux/delay.h>
23 #if defined(CONFIG_OF_LIBFDT)
24 #include <linux/libfdt.h>
27 DECLARE_GLOBAL_DATA_PTR;
29 int fixed_sdram(void);
30 void sdram_init(void);
32 #if defined(CONFIG_DDR_ECC) && defined(CONFIG_MPC83xx)
33 void ddr_enable_ecc(unsigned int dram_size);
36 int board_early_init_f (void)
38 volatile u8* bcsr = (volatile u8*)CONFIG_SYS_BCSR;
40 /* Enable flash write */
43 #ifdef CONFIG_SYS_USE_MPC834XSYS_USB_PHY
44 /* Use USB PHY on SYS board */
51 #define ns2clk(ns) (ns / (1000000000 / CONFIG_8349_CLKIN) + 1)
55 volatile immap_t *im = (immap_t *)CONFIG_SYS_IMMR;
56 phys_size_t msize = 0;
58 if ((im->sysconf.immrbar & IMMRBAR_BASE_ADDR) != (u32)im)
61 /* DDR SDRAM - Main SODIMM */
62 im->sysconf.ddrlaw[0].bar = CONFIG_SYS_SDRAM_BASE & LAWBAR_BAR;
63 #if defined(CONFIG_SPD_EEPROM)
64 #ifndef CONFIG_SYS_FSL_DDR2
65 msize = spd_sdram() * 1024 * 1024;
66 #if defined(CONFIG_DDR_ECC) && !defined(CONFIG_ECC_INIT_VIA_DDRCONTROLLER)
67 ddr_enable_ecc(msize);
70 msize = fsl_ddr_sdram();
73 msize = fixed_sdram() * 1024 * 1024;
76 * Initialize SDRAM if it is on local bus.
80 /* set total bus SDRAM size(bytes) -- DDR */
86 #if !defined(CONFIG_SPD_EEPROM)
87 /*************************************************************************
88 * fixed sdram init -- doesn't use serial presence detect.
89 ************************************************************************/
92 volatile immap_t *im = (immap_t *)CONFIG_SYS_IMMR;
93 u32 msize = CONFIG_SYS_DDR_SIZE;
94 u32 ddr_size = msize << 20; /* DDR size in bytes */
95 u32 ddr_size_log2 = __ilog2(ddr_size);
97 im->sysconf.ddrlaw[0].bar = CONFIG_SYS_SDRAM_BASE & 0xfffff000;
98 im->sysconf.ddrlaw[0].ar = LAWAR_EN | ((ddr_size_log2 - 1) & LAWAR_SIZE);
100 #if (CONFIG_SYS_DDR_SIZE != 256)
101 #warning Currenly any ddr size other than 256 is not supported
104 im->ddr.csbnds[2].csbnds = CONFIG_SYS_DDR_CS2_BNDS;
105 im->ddr.cs_config[2] = CONFIG_SYS_DDR_CS2_CONFIG;
106 im->ddr.timing_cfg_0 = CONFIG_SYS_DDR_TIMING_0;
107 im->ddr.timing_cfg_1 = CONFIG_SYS_DDR_TIMING_1;
108 im->ddr.timing_cfg_2 = CONFIG_SYS_DDR_TIMING_2;
109 im->ddr.timing_cfg_3 = CONFIG_SYS_DDR_TIMING_3;
110 im->ddr.sdram_cfg = CONFIG_SYS_DDR_SDRAM_CFG;
111 im->ddr.sdram_cfg2 = CONFIG_SYS_DDR_SDRAM_CFG2;
112 im->ddr.sdram_mode = CONFIG_SYS_DDR_MODE;
113 im->ddr.sdram_mode2 = CONFIG_SYS_DDR_MODE2;
114 im->ddr.sdram_interval = CONFIG_SYS_DDR_INTERVAL;
115 im->ddr.sdram_clk_cntl = CONFIG_SYS_DDR_CLK_CNTL;
118 #if ((CONFIG_SYS_SDRAM_BASE & 0x00FFFFFF) != 0)
119 #warning Chip select bounds is only configurable in 16MB increments
121 im->ddr.csbnds[2].csbnds =
122 ((CONFIG_SYS_SDRAM_BASE >> CSBNDS_SA_SHIFT) & CSBNDS_SA) |
123 (((CONFIG_SYS_SDRAM_BASE + ddr_size - 1) >>
124 CSBNDS_EA_SHIFT) & CSBNDS_EA);
125 im->ddr.cs_config[2] = CONFIG_SYS_DDR_CS2_CONFIG;
127 /* currently we use only one CS, so disable the other banks */
128 im->ddr.cs_config[0] = 0;
129 im->ddr.cs_config[1] = 0;
130 im->ddr.cs_config[3] = 0;
132 im->ddr.timing_cfg_1 = CONFIG_SYS_DDR_TIMING_1;
133 im->ddr.timing_cfg_2 = CONFIG_SYS_DDR_TIMING_2;
137 #if defined(CONFIG_DDR_2T_TIMING)
140 | 2 << SDRAM_CFG_SDRAM_TYPE_SHIFT;
141 #if defined (CONFIG_DDR_32BIT)
142 /* for 32-bit mode burst length is 8 */
143 im->ddr.sdram_cfg |= (SDRAM_CFG_32_BE | SDRAM_CFG_8_BE);
145 im->ddr.sdram_mode = CONFIG_SYS_DDR_MODE;
147 im->ddr.sdram_interval = CONFIG_SYS_DDR_INTERVAL;
151 /* enable DDR controller */
152 im->ddr.sdram_cfg |= SDRAM_CFG_MEM_EN;
155 #endif/*!CONFIG_SYS_SPD_EEPROM*/
158 int checkboard (void)
161 * Warning: do not read the BCSR registers here
163 * There is a timing bug in the 8349E and 8349EA BCSR code
164 * version 1.2 (read from BCSR 11) that will cause the CFI
165 * flash initialization code to overwrite BCSR 0, disabling
166 * the serial ports and gigabit ethernet
169 puts("Board: Freescale MPC8349EMDS\n");
174 * if MPC8349EMDS is soldered with SDRAM
176 #if defined(CONFIG_SYS_BR2_PRELIM) \
177 && defined(CONFIG_SYS_OR2_PRELIM) \
178 && defined(CONFIG_SYS_LBLAWBAR2_PRELIM) \
179 && defined(CONFIG_SYS_LBLAWAR2_PRELIM)
181 * Initialize SDRAM memory on the Local Bus.
184 void sdram_init(void)
186 volatile immap_t *immap = (immap_t *)CONFIG_SYS_IMMR;
187 volatile fsl_lbc_t *lbc = &immap->im_lbc;
188 uint *sdram_addr = (uint *)CONFIG_SYS_LBC_SDRAM_BASE;
189 const u32 lsdmr_common = LSDMR_RFEN | LSDMR_BSMA1516 | LSDMR_RFCR8 |
190 LSDMR_PRETOACT6 | LSDMR_ACTTORW3 | LSDMR_BL8 |
191 LSDMR_WRC3 | LSDMR_CL3;
193 * Setup SDRAM Base and Option Registers, already done in cpu_init.c
196 /* setup mtrpt, lsrt and lbcr for LB bus */
197 lbc->lbcr = 0x00000000;
198 /* LB refresh timer prescal, 266MHz/32 */
199 lbc->mrtpr = 0x20000000;
200 /* LB sdram refresh timer, about 6us */
201 lbc->lsrt = 0x32000000;
205 * Configure the SDRAM controller Machine Mode Register.
208 /* 0x40636733; normal operation */
209 lbc->lsdmr = lsdmr_common | LSDMR_OP_NORMAL;
211 /* 0x68636733; precharge all the banks */
212 lbc->lsdmr = lsdmr_common | LSDMR_OP_PCHALL;
217 /* 0x48636733; auto refresh */
218 lbc->lsdmr = lsdmr_common | LSDMR_OP_ARFRSH;
245 /* 0x58636733; mode register write operation */
246 lbc->lsdmr = lsdmr_common | LSDMR_OP_MRW;
251 /* 0x40636733; normal operation */
252 lbc->lsdmr = lsdmr_common | LSDMR_OP_NORMAL;
258 void sdram_init(void)
264 * The following are used to control the SPI chip selects for the SPI command.
266 #ifdef CONFIG_MPC8XXX_SPI
268 #define SPI_CS_MASK 0x80000000
270 int spi_cs_is_valid(unsigned int bus, unsigned int cs)
272 return bus == 0 && cs == 0;
275 void spi_cs_activate(struct spi_slave *slave)
277 volatile gpio83xx_t *iopd = &((immap_t *)CONFIG_SYS_IMMR)->gpio[0];
279 iopd->dat &= ~SPI_CS_MASK;
282 void spi_cs_deactivate(struct spi_slave *slave)
284 volatile gpio83xx_t *iopd = &((immap_t *)CONFIG_SYS_IMMR)->gpio[0];
286 iopd->dat |= SPI_CS_MASK;
290 #if defined(CONFIG_OF_BOARD_SETUP)
291 int ft_board_setup(void *blob, bd_t *bd)
293 ft_cpu_setup(blob, bd);
295 ft_pci_setup(blob, bd);