1 // SPDX-License-Identifier: GPL-2.0+
4 * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
8 #include <fdt_support.h>
12 #include <asm/mpc8349_pci.h>
16 #ifdef CONFIG_SYS_FSL_DDR2
17 #include <fsl_ddr_sdram.h>
19 #include <spd_sdram.h>
22 #if defined(CONFIG_OF_LIBFDT)
23 #include <linux/libfdt.h>
26 DECLARE_GLOBAL_DATA_PTR;
28 int fixed_sdram(void);
29 void sdram_init(void);
31 #if defined(CONFIG_DDR_ECC) && defined(CONFIG_MPC83xx)
32 void ddr_enable_ecc(unsigned int dram_size);
35 int board_early_init_f (void)
37 volatile u8* bcsr = (volatile u8*)CONFIG_SYS_BCSR;
39 /* Enable flash write */
42 #ifdef CONFIG_SYS_USE_MPC834XSYS_USB_PHY
43 /* Use USB PHY on SYS board */
50 #define ns2clk(ns) (ns / (1000000000 / CONFIG_8349_CLKIN) + 1)
54 volatile immap_t *im = (immap_t *)CONFIG_SYS_IMMR;
55 phys_size_t msize = 0;
57 if ((im->sysconf.immrbar & IMMRBAR_BASE_ADDR) != (u32)im)
60 /* DDR SDRAM - Main SODIMM */
61 im->sysconf.ddrlaw[0].bar = CONFIG_SYS_SDRAM_BASE & LAWBAR_BAR;
62 #if defined(CONFIG_SPD_EEPROM)
63 #ifndef CONFIG_SYS_FSL_DDR2
64 msize = spd_sdram() * 1024 * 1024;
65 #if defined(CONFIG_DDR_ECC) && !defined(CONFIG_ECC_INIT_VIA_DDRCONTROLLER)
66 ddr_enable_ecc(msize);
69 msize = fsl_ddr_sdram();
72 msize = fixed_sdram() * 1024 * 1024;
75 * Initialize SDRAM if it is on local bus.
79 /* set total bus SDRAM size(bytes) -- DDR */
85 #if !defined(CONFIG_SPD_EEPROM)
86 /*************************************************************************
87 * fixed sdram init -- doesn't use serial presence detect.
88 ************************************************************************/
91 volatile immap_t *im = (immap_t *)CONFIG_SYS_IMMR;
92 u32 msize = CONFIG_SYS_DDR_SIZE;
93 u32 ddr_size = msize << 20; /* DDR size in bytes */
94 u32 ddr_size_log2 = __ilog2(ddr_size);
96 im->sysconf.ddrlaw[0].bar = CONFIG_SYS_SDRAM_BASE & 0xfffff000;
97 im->sysconf.ddrlaw[0].ar = LAWAR_EN | ((ddr_size_log2 - 1) & LAWAR_SIZE);
99 #if (CONFIG_SYS_DDR_SIZE != 256)
100 #warning Currenly any ddr size other than 256 is not supported
103 im->ddr.csbnds[2].csbnds = CONFIG_SYS_DDR_CS2_BNDS;
104 im->ddr.cs_config[2] = CONFIG_SYS_DDR_CS2_CONFIG;
105 im->ddr.timing_cfg_0 = CONFIG_SYS_DDR_TIMING_0;
106 im->ddr.timing_cfg_1 = CONFIG_SYS_DDR_TIMING_1;
107 im->ddr.timing_cfg_2 = CONFIG_SYS_DDR_TIMING_2;
108 im->ddr.timing_cfg_3 = CONFIG_SYS_DDR_TIMING_3;
109 im->ddr.sdram_cfg = CONFIG_SYS_DDR_SDRAM_CFG;
110 im->ddr.sdram_cfg2 = CONFIG_SYS_DDR_SDRAM_CFG2;
111 im->ddr.sdram_mode = CONFIG_SYS_DDR_MODE;
112 im->ddr.sdram_mode2 = CONFIG_SYS_DDR_MODE2;
113 im->ddr.sdram_interval = CONFIG_SYS_DDR_INTERVAL;
114 im->ddr.sdram_clk_cntl = CONFIG_SYS_DDR_CLK_CNTL;
117 #if ((CONFIG_SYS_SDRAM_BASE & 0x00FFFFFF) != 0)
118 #warning Chip select bounds is only configurable in 16MB increments
120 im->ddr.csbnds[2].csbnds =
121 ((CONFIG_SYS_SDRAM_BASE >> CSBNDS_SA_SHIFT) & CSBNDS_SA) |
122 (((CONFIG_SYS_SDRAM_BASE + ddr_size - 1) >>
123 CSBNDS_EA_SHIFT) & CSBNDS_EA);
124 im->ddr.cs_config[2] = CONFIG_SYS_DDR_CS2_CONFIG;
126 /* currently we use only one CS, so disable the other banks */
127 im->ddr.cs_config[0] = 0;
128 im->ddr.cs_config[1] = 0;
129 im->ddr.cs_config[3] = 0;
131 im->ddr.timing_cfg_1 = CONFIG_SYS_DDR_TIMING_1;
132 im->ddr.timing_cfg_2 = CONFIG_SYS_DDR_TIMING_2;
136 #if defined(CONFIG_DDR_2T_TIMING)
139 | 2 << SDRAM_CFG_SDRAM_TYPE_SHIFT;
140 #if defined (CONFIG_DDR_32BIT)
141 /* for 32-bit mode burst length is 8 */
142 im->ddr.sdram_cfg |= (SDRAM_CFG_32_BE | SDRAM_CFG_8_BE);
144 im->ddr.sdram_mode = CONFIG_SYS_DDR_MODE;
146 im->ddr.sdram_interval = CONFIG_SYS_DDR_INTERVAL;
150 /* enable DDR controller */
151 im->ddr.sdram_cfg |= SDRAM_CFG_MEM_EN;
154 #endif/*!CONFIG_SYS_SPD_EEPROM*/
157 int checkboard (void)
160 * Warning: do not read the BCSR registers here
162 * There is a timing bug in the 8349E and 8349EA BCSR code
163 * version 1.2 (read from BCSR 11) that will cause the CFI
164 * flash initialization code to overwrite BCSR 0, disabling
165 * the serial ports and gigabit ethernet
168 puts("Board: Freescale MPC8349EMDS\n");
173 * if MPC8349EMDS is soldered with SDRAM
175 #if defined(CONFIG_SYS_BR2_PRELIM) \
176 && defined(CONFIG_SYS_OR2_PRELIM) \
177 && defined(CONFIG_SYS_LBLAWBAR2_PRELIM) \
178 && defined(CONFIG_SYS_LBLAWAR2_PRELIM)
180 * Initialize SDRAM memory on the Local Bus.
183 void sdram_init(void)
185 volatile immap_t *immap = (immap_t *)CONFIG_SYS_IMMR;
186 volatile fsl_lbc_t *lbc = &immap->im_lbc;
187 uint *sdram_addr = (uint *)CONFIG_SYS_LBC_SDRAM_BASE;
188 const u32 lsdmr_common = LSDMR_RFEN | LSDMR_BSMA1516 | LSDMR_RFCR8 |
189 LSDMR_PRETOACT6 | LSDMR_ACTTORW3 | LSDMR_BL8 |
190 LSDMR_WRC3 | LSDMR_CL3;
192 * Setup SDRAM Base and Option Registers, already done in cpu_init.c
195 /* setup mtrpt, lsrt and lbcr for LB bus */
196 lbc->lbcr = 0x00000000;
197 /* LB refresh timer prescal, 266MHz/32 */
198 lbc->mrtpr = 0x20000000;
199 /* LB sdram refresh timer, about 6us */
200 lbc->lsrt = 0x32000000;
204 * Configure the SDRAM controller Machine Mode Register.
207 /* 0x40636733; normal operation */
208 lbc->lsdmr = lsdmr_common | LSDMR_OP_NORMAL;
210 /* 0x68636733; precharge all the banks */
211 lbc->lsdmr = lsdmr_common | LSDMR_OP_PCHALL;
216 /* 0x48636733; auto refresh */
217 lbc->lsdmr = lsdmr_common | LSDMR_OP_ARFRSH;
244 /* 0x58636733; mode register write operation */
245 lbc->lsdmr = lsdmr_common | LSDMR_OP_MRW;
250 /* 0x40636733; normal operation */
251 lbc->lsdmr = lsdmr_common | LSDMR_OP_NORMAL;
257 void sdram_init(void)
263 * The following are used to control the SPI chip selects for the SPI command.
265 #ifdef CONFIG_MPC8XXX_SPI
267 #define SPI_CS_MASK 0x80000000
269 int spi_cs_is_valid(unsigned int bus, unsigned int cs)
271 return bus == 0 && cs == 0;
274 void spi_cs_activate(struct spi_slave *slave)
276 volatile gpio83xx_t *iopd = &((immap_t *)CONFIG_SYS_IMMR)->gpio[0];
278 iopd->dat &= ~SPI_CS_MASK;
281 void spi_cs_deactivate(struct spi_slave *slave)
283 volatile gpio83xx_t *iopd = &((immap_t *)CONFIG_SYS_IMMR)->gpio[0];
285 iopd->dat |= SPI_CS_MASK;
289 #if defined(CONFIG_OF_BOARD_SETUP)
290 int ft_board_setup(void *blob, bd_t *bd)
292 ft_cpu_setup(blob, bd);
294 ft_pci_setup(blob, bd);