1 // SPDX-License-Identifier: GPL-2.0+
3 * Copyright (C) 2010 Freescale Semiconductor, Inc.
4 * Copyright (C) 2010 Ilya Yanok, Emcraft Systems, yanok@emcraft.com
13 #include <linux/libfdt.h>
14 #include <fdt_support.h>
19 #include <fsl_esdhc.h>
21 #include <asm/fsl_serdes.h>
22 #include <asm/fsl_mpc83xx_serdes.h>
25 * The following are used to control the SPI chip selects for the SPI command.
27 #ifdef CONFIG_MPC8XXX_SPI
29 #define SPI_CS_MASK 0x00400000
31 int spi_cs_is_valid(unsigned int bus, unsigned int cs)
33 return bus == 0 && cs == 0;
36 void spi_cs_activate(struct spi_slave *slave)
38 immap_t *immr = (immap_t *)CONFIG_SYS_IMMR;
41 clrbits_be32(&immr->gpio[0].dat, SPI_CS_MASK);
44 void spi_cs_deactivate(struct spi_slave *slave)
46 immap_t *immr = (immap_t *)CONFIG_SYS_IMMR;
49 setbits_be32(&immr->gpio[0].dat, SPI_CS_MASK);
51 #endif /* CONFIG_MPC8XXX_SPI */
53 #ifdef CONFIG_FSL_ESDHC
54 int board_mmc_init(bd_t *bd)
56 return fsl_esdhc_mmc_init(bd);
60 static u8 read_board_info(void)
65 if (i2c_read(CONFIG_SYS_I2C_PCF8574A_ADDR, 0, 0, &val8, 1) == 0)
73 static const char * const rev_str[] = {
83 info = read_board_info();
84 i = (!info) ? 4 : info & 0x03;
86 printf("Board: Freescale MPC8308RDB Rev %s\n", rev_str[i]);
91 static struct pci_region pcie_regions_0[] = {
93 .bus_start = CONFIG_SYS_PCIE1_MEM_BASE,
94 .phys_start = CONFIG_SYS_PCIE1_MEM_PHYS,
95 .size = CONFIG_SYS_PCIE1_MEM_SIZE,
96 .flags = PCI_REGION_MEM,
99 .bus_start = CONFIG_SYS_PCIE1_IO_BASE,
100 .phys_start = CONFIG_SYS_PCIE1_IO_PHYS,
101 .size = CONFIG_SYS_PCIE1_IO_SIZE,
102 .flags = PCI_REGION_IO,
106 void pci_init_board(void)
108 immap_t *immr = (immap_t *)CONFIG_SYS_IMMR;
109 sysconf83xx_t *sysconf = &immr->sysconf;
110 law83xx_t *pcie_law = sysconf->pcielaw;
111 struct pci_region *pcie_reg[] = { pcie_regions_0 };
113 fsl_setup_serdes(CONFIG_FSL_SERDES1, FSL_SERDES_PROTO_PEX,
114 FSL_SERDES_CLK_100, FSL_SERDES_VDD_1V);
116 /* Deassert the resets in the control register */
117 out_be32(&sysconf->pecr1, 0xE0008000);
120 /* Configure PCI Express Local Access Windows */
121 out_be32(&pcie_law[0].bar, CONFIG_SYS_PCIE1_BASE & LAWBAR_BAR);
122 out_be32(&pcie_law[0].ar, LBLAWAR_EN | LBLAWAR_512MB);
124 mpc83xx_pcie_init(1, pcie_reg);
127 * Miscellaneous late-boot configurations
129 * If a VSC7385 microcode image is present, then upload it.
131 int misc_init_r(void)
133 #ifdef CONFIG_MPC8XXX_SPI
134 immap_t *immr = (immap_t *)CONFIG_SYS_IMMR;
135 sysconf83xx_t *sysconf = &immr->sysconf;
138 * Set proper bits in SICRH to allow SPI on header J8
140 * NOTE: this breaks the TSEC2 interface, attached to the Vitesse
141 * switch. The pinmux configuration does not have a fine enough
142 * granularity to support both simultaneously.
144 clrsetbits_be32(&sysconf->sicrh, SICRH_GPIO_A_TSEC2, SICRH_GPIO_A_GPIO);
145 puts("WARNING: SPI enabled, TSEC2 support is broken\n");
147 /* Set header J8 SPI chip select output, disabled */
148 setbits_be32(&immr->gpio[0].dir, SPI_CS_MASK);
149 setbits_be32(&immr->gpio[0].dat, SPI_CS_MASK);
152 #ifdef CONFIG_VSC7385_IMAGE
153 if (vsc7385_upload_firmware((void *) CONFIG_VSC7385_IMAGE,
154 CONFIG_VSC7385_IMAGE_SIZE)) {
155 puts("Failure uploading VSC7385 microcode.\n");
162 #if defined(CONFIG_OF_BOARD_SETUP)
163 int ft_board_setup(void *blob, bd_t *bd)
165 ft_cpu_setup(blob, bd);
166 fsl_fdt_fixup_dr_usb(blob, bd);
167 fdt_fixup_esdhc(blob, bd);
173 int board_eth_init(bd_t *bis)
177 /* Initialize TSECs first */
178 rv = cpu_eth_init(bis);
182 printf("ERROR: failed to initialize TSECs.\n");
184 rv = pci_eth_init(bis);
188 printf("ERROR: failed to initialize PCI Ethernet.\n");