2 * (C) Copyright 2000-2003
3 * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
5 * Copyright (C) 2004-2007 Freescale Semiconductor, Inc.
6 * TsiChung Liew (Tsi-Chung.Liew@freescale.com)
8 * See file CREDITS for list of people who contributed to this
11 * This program is free software; you can redistribute it and/or
12 * modify it under the terms of the GNU General Public License as
13 * published by the Free Software Foundation; either version 2 of
14 * the License, or (at your option) any later version.
16 * This program is distributed in the hope that it will be useful,
17 * but WITHOUT ANY WARRANTY; without even the implied warranty of
18 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
19 * GNU General Public License for more details.
21 * You should have received a copy of the GNU General Public License
22 * along with this program; if not, write to the Free Software
23 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
29 #include <asm/immap.h>
31 DECLARE_GLOBAL_DATA_PTR;
36 puts("Freescale M54455 EVB\n");
40 phys_size_t initdram(int board_type)
42 volatile sdramc_t *sdram = (volatile sdramc_t *)(MMAP_SDRAM);
43 volatile gpio_t *gpio = (volatile gpio_t *)(MMAP_GPIO);
46 dramsize = CFG_SDRAM_SIZE * 0x100000 >> 1;
48 for (i = 0x13; i < 0x20; i++) {
49 if (dramsize == (1 << i))
54 gpio->mscr_sdram = 0xAA;
56 sdram->sdcs0 = (CFG_SDRAM_BASE | i);
57 sdram->sdcs1 = (CFG_SDRAM_BASE1 | i);
59 sdram->sdcfg1 = CFG_SDRAM_CFG1;
60 sdram->sdcfg2 = CFG_SDRAM_CFG2;
63 sdram->sdcr = CFG_SDRAM_CTRL | 2;
66 sdram->sdmr = CFG_SDRAM_EMOD | 0x408;
67 sdram->sdmr = CFG_SDRAM_MODE | 0x300;
72 sdram->sdcr = CFG_SDRAM_CTRL | 2;
74 /* Perform two refresh cycles */
75 sdram->sdcr = CFG_SDRAM_CTRL | 4;
76 sdram->sdcr = CFG_SDRAM_CTRL | 4;
78 sdram->sdmr = CFG_SDRAM_MODE | 0x200;
80 sdram->sdcr = (CFG_SDRAM_CTRL & ~0x80000000) | 0x10000c00;
84 return (dramsize << 1);
89 /* TODO: XXX XXX XXX */
90 printf("DRAM test not implemented!\n");
95 #if defined(CONFIG_CMD_IDE)
100 volatile gpio_t *gpio = (gpio_t *) MMAP_GPIO;
102 gpio->par_fec |= (gpio->par_fec & GPIO_PAR_FEC_FEC1_MASK) | 0x10;
104 (gpio->par_feci2c & 0xF0FF) | (GPIO_PAR_FECI2C_MDC1_ATA_DIOR |
105 GPIO_PAR_FECI2C_MDIO1_ATA_DIOW);
107 (GPIO_PAR_ATA_BUFEN | GPIO_PAR_ATA_CS1 | GPIO_PAR_ATA_CS0 |
108 GPIO_PAR_ATA_DA2 | GPIO_PAR_ATA_DA1 | GPIO_PAR_ATA_DA0
109 | GPIO_PAR_ATA_RESET_RESET | GPIO_PAR_ATA_DMARQ_DMARQ |
110 GPIO_PAR_ATA_IORDY_IORDY);
112 (GPIO_PAR_PCI_GNT3_ATA_DMACK | GPIO_PAR_PCI_REQ3_ATA_INTRQ);
117 void ide_set_reset(int idereset)
119 volatile atac_t *ata = (atac_t *) MMAP_ATA;
121 /* t1, t2, t3, t4, t5, t6, t9, tRD, tA */
123 {70, 165, 60, 30, 50, 5, 20, 0, 35}, /* PIO 0 */
124 {50, 125, 45, 20, 35, 5, 15, 0, 35}, /* PIO 1 */
125 {30, 100, 30, 15, 20, 5, 10, 0, 35}, /* PIO 2 */
126 {30, 80, 30, 10, 20, 5, 10, 0, 35}, /* PIO 3 */
127 {25, 70, 20, 10, 20, 5, 10, 0, 35}
131 ata->cr = 0; /* control reset */
134 #define CALC_TIMING(t) (t + period - 1) / period
135 period = 1000000000 / gd->bus_clk; /* period in ns */
137 /*ata->ton = CALC_TIMING (180); */
138 ata->t1 = CALC_TIMING(piotms[2][0]);
139 ata->t2w = CALC_TIMING(piotms[2][1]);
140 ata->t2r = CALC_TIMING(piotms[2][1]);
141 ata->ta = CALC_TIMING(piotms[2][8]);
142 ata->trd = CALC_TIMING(piotms[2][7]);
143 ata->t4 = CALC_TIMING(piotms[2][3]);
144 ata->t9 = CALC_TIMING(piotms[2][6]);
146 ata->cr = 0x40; /* IORDY enable */
148 ata->cr |= 0x01; /* IORDY enable */
153 #if defined(CONFIG_PCI)
155 * Initialize PCI devices, report devices found.
157 static struct pci_controller hose;
158 extern void pci_mcf5445x_init(struct pci_controller *hose);
160 void pci_init_board(void)
162 pci_mcf5445x_init(&hose);
164 #endif /* CONFIG_PCI */
166 #if defined(CFG_FLASH_CFI)
168 ulong board_flash_get_legacy (ulong base, int banknum, flash_info_t * info)
170 int sect[] = CFG_ATMEL_SECT;
171 int sectsz[] = CFG_ATMEL_SECTSZ;
174 if (base != CFG_ATMEL_BASE)
177 info->flash_id = 0x01000000;
180 info->buffer_size = 32;
181 info->erase_blk_tout = 16384;
182 info->write_tout = 2;
183 info->buffer_write_tout = 5;
184 info->vendor = 2; /* CFI_CMDSET_AMD_STANDARD */
185 info->cmd_reset = 0x00F0;
186 info->interface = FLASH_CFI_X8;
187 info->legacy_unlock = 0;
188 info->manufacturer_id = (u16) ATM_MANUFACT;
189 info->device_id = ATM_ID_LV040;
190 info->device_id2 = 0;
193 info->cfi_version = 0x3133;
194 info->cfi_offset = 0x0055;
195 info->addr_unlock1 = 0x00000555;
196 info->addr_unlock2 = 0x000002AA;
197 info->name = "CFI conformant";
201 info->sector_count = CFG_ATMEL_TOTALSECT;
202 info->start[0] = base;
203 for (k = 0, i = 0; i < CFG_ATMEL_REGION; i++) {
204 info->size += sect[i] * sectsz[i];
206 for (j = 0; j < sect[i]; j++, k++) {
207 info->start[k + 1] = info->start[k] + sectsz[i];
208 info->protect[k] = 0;
214 #endif /* CFG_FLASH_CFI */