board/freescale/m54455evb/flash.c

   1 /*
   2  * (C) Copyright 2000-2003
   3  * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
   4  *
   5  * Copyright (C) 2004-2007 Freescale Semiconductor, Inc.
   6  * TsiChung Liew (Tsi-Chung.Liew@freescale.com)
   7  *
   8  * See file CREDITS for list of people who contributed to this
   9  * project.
  10  *
  11  * This program is free software; you can redistribute it and/or
  12  * modify it under the terms of the GNU General Public License as
  13  * published by the Free Software Foundation; either version 2 of
  14  * the License, or (at your option) any later version.
  15  *
  16  * This program is distributed in the hope that it will be useful,
  17  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  18  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  19  * GNU General Public License for more details.
  20  *
  21  * You should have received a copy of the GNU General Public License
  22  * along with this program; if not, write to the Free Software
  23  * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  24  * MA 02111-1307 USA
  25  */
  26
  27 #include <common.h>
  28
  29 #include <asm/immap.h>
  30
  31 #ifndef CFG_FLASH_CFI
  32 typedef unsigned char FLASH_PORT_WIDTH;
  33 typedef volatile unsigned char FLASH_PORT_WIDTHV;
  34
  35 #define FPW             FLASH_PORT_WIDTH
  36 #define FPWV            FLASH_PORT_WIDTHV
  37
  38 #define CFG_FLASH_CFI_WIDTH     FLASH_CFI_8BIT
  39 #define CFG_FLASH_NONCFI_WIDTH  FLASH_CFI_8BIT
  40
  41 /* Intel-compatible flash commands */
  42 #define INTEL_PROGRAM   0x00100010
  43 #define INTEL_ERASE     0x00200020
  44 #define INTEL_WRSETUP   0x00400040
  45 #define INTEL_CLEAR     0x00500050
  46 #define INTEL_LOCKBIT   0x00600060
  47 #define INTEL_PROTECT   0x00010001
  48 #define INTEL_STATUS    0x00700070
  49 #define INTEL_READID    0x00900090
  50 #define INTEL_CFIQRY    0x00980098
  51 #define INTEL_SUSERASE  0x00B000B0
  52 #define INTEL_PROTPROG  0x00C000C0
  53 #define INTEL_CONFIRM   0x00D000D0
  54 #define INTEL_WRBLK     0x00e800e8
  55 #define INTEL_RESET     0x00FF00FF
  56
  57 /* Intel-compatible flash status bits */
  58 #define INTEL_FINISHED  0x00800080
  59 #define INTEL_OK        0x00800080
  60 #define INTEL_ERASESUS  0x00600060
  61 #define INTEL_WSM_SUS   (INTEL_FINISHED | INTEL_ERASESUS)
  62
  63 /* 28F160C3B CFI Data offset - This could vary */
  64 #define INTEL_CFI_MFG   0x00    /* Manufacturer ID */
  65 #define INTEL_CFI_PART  0x01    /* Product ID */
  66 #define INTEL_CFI_LOCK  0x02    /* */
  67 #define INTEL_CFI_TWPRG 0x1F    /* Typical Single Word Program Timeout 2^n us */
  68 #define INTEL_CFI_MBUFW 0x20    /* Typical Max Buffer Write Timeout 2^n us */
  69 #define INTEL_CFI_TERB  0x21    /* Typical Block Erase Timeout 2^n ms */
  70 #define INTEL_CFI_MWPRG 0x23    /* Maximum Word program timeout 2^n us */
  71 #define INTEL_CFI_MERB  0x25    /* Maximum Block Erase Timeout 2^n s */
  72 #define INTEL_CFI_SIZE  0x27    /* Device size 2^n bytes */
  73 #define INTEL_CFI_CAP   0x28
  74 #define INTEL_CFI_WRBUF 0x2A
  75 #define INTEL_CFI_BANK  0x2C    /* Number of Bank */
  76 #define INTEL_CFI_BLK1A 0x2D    /* Number of Blocks */
  77 #define INTEL_CFI_BLK1B 0x2E    /* Number of Blocks */
  78 #define INTEL_CFI_SZ1A  0x2F    /* Block Region Size */
  79 #define INTEL_CFI_SZ1B  0x30
  80 #define INTEL_CFI_BLK2A 0x31
  81 #define INTEL_CFI_BLK2B 0x32
  82 #define INTEL_CFI_SZ2A  0x33
  83 #define INTEL_CFI_SZ2B  0x34
  84
  85 #define FLASH_CYCLE1    0x0555
  86 #define FLASH_CYCLE2    0x0aaa
  87
  88 #define WR_BLOCK        0x20
  89
  90 /* not in the flash.h yet */
  91 #define FLASH_28F64P30T         0x00B9  /* Intel 28F64P30T   (  64M)            */
  92 #define FLASH_28F64P30B         0x00BA  /* Intel 28F64P30B   (  64M)            */
  93 #define FLASH_28F128P30T        0x00BB  /* Intel 28F128P30T  ( 128M = 8M x 16 ) */
  94 #define FLASH_28F128P30B        0x00BC  /* Intel 28F128P30B  ( 128M = 8M x 16 ) */
  95 #define FLASH_28F256P30T        0x00BD  /* Intel 28F256P30T  ( 256M = 16M x 16 )        */
  96 #define FLASH_28F256P30B        0x00BE  /* Intel 28F256P30B  ( 256M = 16M x 16 )        */
  97
  98 #if defined(CONFIG_SERIAL_FLASH) && defined(CONFIG_CF_DSPI)
  99 #define STM_ID_M25P16           0x20152015
 100 #define FLASH_M25P16            0x0055
 101 #endif
 102
 103 #define SYNC                    __asm__("nop")
 104
 105 /*-----------------------------------------------------------------------
 106  * Functions
 107  */
 108
 109 ulong flash_get_size(FPWV * addr, flash_info_t * info);
 110 int flash_get_offsets(ulong base, flash_info_t * info);
 111 int flash_cmd_rd(volatile u16 * addr, int index);
 112 int write_data(flash_info_t * info, ulong dest, FPW data);
 113 int write_data_block(flash_info_t * info, ulong src, ulong dest);
 114 int write_word_atm(flash_info_t * info, volatile u8 * dest, u16 data);
 115 void inline spin_wheel(void);
 116 void flash_sync_real_protect(flash_info_t * info);
 117 uchar intel_sector_protected(flash_info_t * info, ushort sector);
 118
 119 #if defined(CONFIG_SERIAL_FLASH) && defined(CONFIG_CF_DSPI)
 120 int write_ser_data(flash_info_t * info, ulong dest, uchar * data, ulong cnt);
 121 int serial_flash_read_status(int chipsel);
 122 static int ser_flash_cs = 0;
 123 #endif
 124
 125 flash_info_t flash_info[CFG_MAX_FLASH_BANKS];
 126
 127 ulong flash_init(void)
 128 {
 129         int i;
 130         ulong size = 0;
 131         ulong fbase = 0;
 132
 133 #if defined(CONFIG_SERIAL_FLASH) && defined(CONFIG_CF_DSPI)
 134         dspi_init();
 135 #endif
 136
 137         for (i = 0; i < CFG_MAX_FLASH_BANKS; i++) {
 138                 memset(&flash_info[i], 0, sizeof(flash_info_t));
 139
 140                 switch (i) {
 141                 case 0:
 142                         fbase = (ulong) CFG_FLASH0_BASE;
 143                         break;
 144                 case 1:
 145                         fbase = (ulong) CFG_FLASH1_BASE;
 146                         break;
 147 #if defined(CONFIG_SERIAL_FLASH) && defined(CONFIG_CF_DSPI)
 148                 case 2:
 149                         fbase = (ulong) CFG_FLASH2_BASE;
 150                         break;
 151 #endif
 152                 }
 153
 154                 flash_get_size((FPWV *) fbase, &flash_info[i]);
 155                 flash_get_offsets((ulong) fbase, &flash_info[i]);
 156                 fbase += flash_info[i].size;
 157                 size += flash_info[i].size;
 158
 159                 /* get the h/w and s/w protection status in sync */
 160                 flash_sync_real_protect(&flash_info[i]);
 161         }
 162
 163         /* Protect monitor and environment sectors */
 164         flash_protect(FLAG_PROTECT_SET,
 165                       CFG_MONITOR_BASE,
 166                       CFG_MONITOR_BASE + monitor_flash_len - 1, &flash_info[0]);
 167
 168         return size;
 169 }
 170
 171 int flash_get_offsets(ulong base, flash_info_t * info)
 172 {
 173         int i, j, k;
 174         int sectors, bs, banks;
 175
 176         if ((info->flash_id & FLASH_VENDMASK) == FLASH_MAN_ATM) {
 177                 int sect[] = CFG_ATMEL_SECT;
 178                 int sectsz[] = CFG_ATMEL_SECTSZ;
 179
 180                 info->start[0] = base;
 181                 for (k = 0, i = 0; i < CFG_ATMEL_REGION; i++) {
 182                         for (j = 0; j < sect[i]; j++, k++) {
 183                                 info->start[k + 1] = info->start[k] + sectsz[i];
 184                                 info->protect[k] = 0;
 185                         }
 186                 }
 187         }
 188
 189         if ((info->flash_id & FLASH_VENDMASK) == FLASH_MAN_INTEL) {
 190                 volatile u16 *addr16 = (volatile u16 *)base;
 191
 192                 *addr16 = (FPW) INTEL_RESET;    /* restore read mode */
 193                 *addr16 = (FPW) INTEL_READID;
 194
 195                 banks = addr16[INTEL_CFI_BANK] & 0xff;
 196
 197                 sectors = 0;
 198                 info->start[0] = base;
 199
 200                 for (k = 0, i = 0; i < banks; i++) {
 201                         /* Geometry y1 = y1 + 1, y2 = y2 + 1, CFI spec.
 202                          * To be exact, Z = [0x2f 0x30] (LE) * 256 bytes * [0x2D 0x2E] block count
 203                          * Z = [0x33 0x34] (LE) * 256 bytes * [0x31 0x32] block count
 204                          */
 205                         bs = ((((addr16[INTEL_CFI_SZ1B + (i * 4)] & 0xff) << 8)
 206                                | (addr16[INTEL_CFI_SZ1A + (i * 4)] & 0xff)) *
 207                               0x100);
 208                         sectors =
 209                             (addr16[INTEL_CFI_BLK1A + (i * 4)] & 0xff) + 1;
 210
 211                         for (j = 0; j < sectors; j++, k++) {
 212                                 info->start[k + 1] = info->start[k] + bs;
 213                         }
 214                 }
 215
 216                 *addr16 = (FPW) INTEL_RESET;    /* restore read mode */
 217         }
 218 #if defined(CONFIG_SERIAL_FLASH) && defined(CONFIG_CF_DSPI)
 219         if ((info->flash_id & FLASH_VENDMASK) == FLASH_MAN_STM) {
 220                 info->start[0] = CFG_FLASH2_BASE;
 221                 for (k = 0, i = 0; i < CFG_STM_SECT; i++, k++) {
 222                         info->start[k + 1] = info->start[k] + CFG_STM_SECTSZ;
 223                         info->protect[k] = 0;
 224                 }
 225         }
 226 #endif
 227
 228         return ERR_OK;
 229 }
 230
 231 void flash_print_info(flash_info_t * info)
 232 {
 233         int i;
 234
 235         switch (info->flash_id & FLASH_VENDMASK) {
 236         case FLASH_MAN_INTEL:
 237                 printf("INTEL ");
 238                 break;
 239         case FLASH_MAN_ATM:
 240                 printf("ATMEL ");
 241                 break;
 242 #if defined(CONFIG_SERIAL_FLASH) && defined(CONFIG_CF_DSPI)
 243         case FLASH_MAN_STM:
 244                 printf("ST ");
 245                 break;
 246 #endif
 247         default:
 248                 printf("Unknown Vendor ");
 249                 break;
 250         }
 251
 252         switch (info->flash_id & FLASH_TYPEMASK) {
 253         case FLASH_AT040:
 254                 printf("AT49BV040A\n");
 255                 break;
 256         case FLASH_28F128J3A:
 257                 printf("28F128J3A\n");
 258                 break;
 259 #if defined(CONFIG_SERIAL_FLASH) && defined(CONFIG_CF_DSPI)
 260         case FLASH_M25P16:
 261                 printf("M25P16\n");
 262                 break;
 263 #endif
 264         default:
 265                 printf("Unknown Chip Type\n");
 266                 return;
 267         }
 268
 269         if (info->size > 0x100000) {
 270                 int remainder;
 271
 272                 printf("  Size: %ld", info->size >> 20);
 273
 274                 remainder = (info->size % 0x100000);
 275                 if (remainder) {
 276                         remainder >>= 10;
 277                         remainder = (int)((float)
 278                                           (((float)remainder / (float)1024) *
 279                                            10000));
 280                         printf(".%d ", remainder);
 281                 }
 282
 283                 printf("MB in %d Sectors\n", info->sector_count);
 284         } else
 285                 printf("  Size: %ld KB in %d Sectors\n",
 286                        info->size >> 10, info->sector_count);
 287
 288         printf("  Sector Start Addresses:");
 289         for (i = 0; i < info->sector_count; ++i) {
 290                 if ((i % 5) == 0)
 291                         printf("\n   ");
 292                 printf(" %08lX%s",
 293                        info->start[i], info->protect[i] ? " (RO)" : "     ");
 294         }
 295         printf("\n");
 296 }
 297
 298 /*
 299  * The following code cannot be run from FLASH!
 300  */
 301 ulong flash_get_size(FPWV * addr, flash_info_t * info)
 302 {
 303         volatile u16 *addr16 = (volatile u16 *)addr;
 304         int intel = 0, banks = 0;
 305         u16 value;
 306         int i;
 307
 308 #if defined(CONFIG_SERIAL_FLASH) && defined(CONFIG_CF_DSPI)
 309         if ((ulong) addr == CFG_FLASH2_BASE) {
 310                 int manufactId = 0;
 311                 int deviceId = 0;
 312
 313                 ser_flash_cs = 1;
 314
 315                 dspi_tx(ser_flash_cs, 0x80, SER_RDID);
 316                 dspi_tx(ser_flash_cs, 0x80, 0);
 317                 dspi_tx(ser_flash_cs, 0x80, 0);
 318                 dspi_tx(ser_flash_cs, 0x80, 0);
 319
 320                 dspi_rx();
 321                 manufactId = dspi_rx();
 322                 deviceId = dspi_rx() << 8;
 323                 deviceId |= dspi_rx();
 324
 325                 dspi_tx(ser_flash_cs, 0x00, 0);
 326                 dspi_rx();
 327
 328                 switch (manufactId) {
 329                 case (u8) STM_MANUFACT:
 330                         info->flash_id = FLASH_MAN_STM;
 331                         break;
 332                 }
 333
 334                 switch (deviceId) {
 335                 case (u16) STM_ID_M25P16:
 336                         info->flash_id += FLASH_M25P16;
 337                         break;
 338                 }
 339
 340                 info->sector_count = CFG_STM_SECT;
 341                 info->size = CFG_STM_SECT * CFG_STM_SECTSZ;
 342
 343                 return (info->size);
 344         }
 345 #endif
 346
 347         addr[FLASH_CYCLE1] = (FPWV) 0x00AA00AA; /* for Atmel, Intel ignores this */
 348         addr[FLASH_CYCLE2] = (FPWV) 0x00550055; /* for Atmel, Intel ignores this */
 349         addr[FLASH_CYCLE1] = (FPWV) 0x00900090; /* selects Intel or Atmel */
 350
 351         switch (addr[0] & 0xff) {
 352         case (u8) ATM_MANUFACT:
 353                 info->flash_id = FLASH_MAN_ATM;
 354                 value = addr[1];
 355                 break;
 356         case (u8) INTEL_MANUFACT:
 357                 /* Terminate Atmel ID read */
 358                 addr[0] = (FPWV) 0x00F000F0;
 359                 /* Write auto select command: read Manufacturer ID */
 360                 /* Write auto select command sequence and test FLASH answer */
 361                 *addr16 = (FPW) INTEL_RESET;    /* restore read mode */
 362                 *addr16 = (FPW) INTEL_READID;
 363
 364                 info->flash_id = FLASH_MAN_INTEL;
 365                 value = (addr16[INTEL_CFI_MFG] << 8);
 366                 value |= addr16[INTEL_CFI_PART] & 0xff;
 367                 intel = 1;
 368                 break;
 369         default:
 370                 printf("Unknown Flash\n");
 371                 info->flash_id = FLASH_UNKNOWN;
 372                 info->sector_count = 0;
 373                 info->size = 0;
 374
 375                 *addr = (FPW) 0x00F000F0;
 376                 *addr = (FPW) INTEL_RESET;      /* restore read mode */
 377                 return (0);     /* no or unknown flash  */
 378         }
 379
 380         switch (value) {
 381         case (u8) ATM_ID_LV040:
 382                 info->flash_id += FLASH_AT040;
 383                 break;
 384         case (u16) INTEL_ID_28F128J3:
 385                 info->flash_id += FLASH_28F128J3A;
 386                 break;
 387         case (u16) INTEL_ID_28F64P30T:
 388                 info->flash_id += FLASH_28F64P30T;
 389                 break;
 390         case (u16) INTEL_ID_28F64P30B:
 391                 info->flash_id += FLASH_28F64P30B;
 392                 break;
 393         case (u16) INTEL_ID_28F128P30T:
 394                 info->flash_id += FLASH_28F128P30T;
 395                 break;
 396         case (u16) INTEL_ID_28F128P30B:
 397                 info->flash_id += FLASH_28F128P30B;
 398                 break;
 399         case (u16) INTEL_ID_28F256P30T:
 400                 info->flash_id += FLASH_28F256P30T;
 401                 break;
 402         case (u16) INTEL_ID_28F256P30B:
 403                 info->flash_id += FLASH_28F256P30B;
 404                 break;
 405         default:
 406                 info->flash_id = FLASH_UNKNOWN;
 407                 break;
 408         }
 409
 410         if (intel) {
 411                 /* Intel spec. under CFI section */
 412                 u32 sz;
 413                 int sectors, bs;
 414
 415                 banks = addr16[INTEL_CFI_BANK] & 0xff;
 416
 417                 sectors = sz = 0;
 418                 for (i = 0; i < banks; i++) {
 419                         /* Geometry y1 = y1 + 1, y2 = y2 + 1, CFI spec.
 420                          * To be exact, Z = [0x2f 0x30] (LE) * 256 bytes * [0x2D 0x2E] block count
 421                          * Z = [0x33 0x34] (LE) * 256 bytes * [0x31 0x32] block count
 422                          */
 423                         bs = ((((addr16[INTEL_CFI_SZ1B + (i * 4)] & 0xff) << 8)
 424                                | (addr16[INTEL_CFI_SZ1A + (i * 4)] & 0xff)) *
 425                               0x100);
 426                         sectors +=
 427                             (addr16[INTEL_CFI_BLK1A + (i * 4)] & 0xff) + 1;
 428                         sz += (bs * sectors);
 429                 }
 430
 431                 info->sector_count = sectors;
 432                 info->size = sz;
 433                 *addr = (FPW) INTEL_RESET;      /* restore read mode */
 434         } else {
 435                 int sect[] = CFG_ATMEL_SECT;
 436                 int sectsz[] = CFG_ATMEL_SECTSZ;
 437
 438                 info->sector_count = 0;
 439                 info->size = 0;
 440                 for (i = 0; i < CFG_ATMEL_REGION; i++) {
 441                         info->sector_count += sect[i];
 442                         info->size += sect[i] * sectsz[i];
 443                 }
 444
 445                 /* reset ID mode */
 446                 addr[0] = (FPWV) 0x00F000F0;
 447         }
 448
 449         if (info->sector_count > CFG_MAX_FLASH_SECT) {
 450                 printf("** ERROR: sector count %d > max (%d) **\n",
 451                        info->sector_count, CFG_MAX_FLASH_SECT);
 452                 info->sector_count = CFG_MAX_FLASH_SECT;
 453         }
 454
 455         return (info->size);
 456 }
 457
 458 int flash_cmd_rd(volatile u16 * addr, int index)
 459 {
 460         return (int)addr[index];
 461 }
 462
 463 #if defined(CONFIG_SERIAL_FLASH) && defined(CONFIG_CF_DSPI)
 464 int serial_flash_read_status(int chipsel)
 465 {
 466         u16 status;
 467
 468         dspi_tx(chipsel, 0x80, SER_RDSR);
 469         dspi_rx();
 470
 471         dspi_tx(chipsel, 0x00, 0);
 472         status = dspi_rx();
 473
 474         return status;
 475 }
 476 #endif
 477
 478 /*
 479  * This function gets the u-boot flash sector protection status
 480  * (flash_info_t.protect[]) in sync with the sector protection
 481  * status stored in hardware.
 482  */
 483 void flash_sync_real_protect(flash_info_t * info)
 484 {
 485         int i;
 486
 487         switch (info->flash_id & FLASH_TYPEMASK) {
 488         case FLASH_28F160C3B:
 489         case FLASH_28F160C3T:
 490         case FLASH_28F320C3B:
 491         case FLASH_28F320C3T:
 492         case FLASH_28F640C3B:
 493         case FLASH_28F640C3T:
 494                 for (i = 0; i < info->sector_count; ++i) {
 495                         info->protect[i] = intel_sector_protected(info, i);
 496                 }
 497                 break;
 498         default:
 499                 /* no h/w protect support */
 500                 break;
 501         }
 502 }
 503
 504 /*
 505  * checks if "sector" in bank "info" is protected. Should work on intel
 506  * strata flash chips 28FxxxJ3x in 8-bit mode.
 507  * Returns 1 if sector is protected (or timed-out while trying to read
 508  * protection status), 0 if it is not.
 509  */
 510 uchar intel_sector_protected(flash_info_t * info, ushort sector)
 511 {
 512         FPWV *addr;
 513         FPWV *lock_conf_addr;
 514         ulong start;
 515         unsigned char ret;
 516
 517         /*
 518          * first, wait for the WSM to be finished. The rationale for
 519          * waiting for the WSM to become idle for at most
 520          * CFG_FLASH_ERASE_TOUT is as follows. The WSM can be busy
 521          * because of: (1) erase, (2) program or (3) lock bit
 522          * configuration. So we just wait for the longest timeout of
 523          * the (1)-(3), i.e. the erase timeout.
 524          */
 525
 526         /* wait at least 35ns (W12) before issuing Read Status Register */
 527         /*udelay(1); */
 528         addr = (FPWV *) info->start[sector];
 529         *addr = (FPW) INTEL_STATUS;
 530
 531         start = get_timer(0);
 532         while ((*addr & (FPW) INTEL_FINISHED) != (FPW) INTEL_FINISHED) {
 533                 if (get_timer(start) > CFG_FLASH_UNLOCK_TOUT) {
 534                         *addr = (FPW) INTEL_RESET;      /* restore read mode */
 535                         printf("WSM busy too long, can't get prot status\n");
 536                         return 1;
 537                 }
 538         }
 539
 540         /* issue the Read Identifier Codes command */
 541         *addr = (FPW) INTEL_READID;
 542
 543         /* Intel example code uses offset of 4 for 8-bit flash */
 544         lock_conf_addr = (FPWV *) info->start[sector];
 545         ret = (lock_conf_addr[INTEL_CFI_LOCK] & (FPW) INTEL_PROTECT) ? 1 : 0;
 546
 547         /* put flash back in read mode */
 548         *addr = (FPW) INTEL_RESET;
 549
 550         return ret;
 551 }
 552
 553 int flash_erase(flash_info_t * info, int s_first, int s_last)
 554 {
 555         int flag, prot, sect;
 556         ulong type, start, last;
 557         int rcode = 0, flashtype = 0;
 558 #if defined(CONFIG_SERIAL_FLASH) && defined(CONFIG_CF_DSPI)
 559         int count;
 560         u16 status;
 561 #endif
 562         if ((s_first < 0) || (s_first > s_last)) {
 563                 if (info->flash_id == FLASH_UNKNOWN)
 564                         printf("- missing\n");
 565                 else
 566                         printf("- no sectors to erase\n");
 567                 return 1;
 568         }
 569
 570         type = (info->flash_id & FLASH_VENDMASK);
 571
 572         switch (type) {
 573         case FLASH_MAN_ATM:
 574                 flashtype = 1;
 575                 break;
 576         case FLASH_MAN_INTEL:
 577                 flashtype = 2;
 578                 break;
 579 #if defined(CONFIG_SERIAL_FLASH) && defined(CONFIG_CF_DSPI)
 580         case FLASH_MAN_STM:
 581                 flashtype = 3;
 582                 break;
 583 #endif
 584         default:
 585                 type = (info->flash_id & FLASH_VENDMASK);
 586                 printf("Can't erase unknown flash type %08lx - aborted\n",
 587                        info->flash_id);
 588                 return 1;
 589         }
 590
 591         prot = 0;
 592         for (sect = s_first; sect <= s_last; ++sect) {
 593                 if (info->protect[sect]) {
 594                         prot++;
 595                 }
 596         }
 597
 598         if (prot)
 599                 printf("- Warning: %d protected sectors will not be erased!\n",
 600                        prot);
 601         else
 602                 printf("\n");
 603
 604         start = get_timer(0);
 605         last = start;
 606
 607 #if defined(CONFIG_SERIAL_FLASH) && defined(CONFIG_CF_DSPI)
 608         /* Perform bulk erase */
 609         if (flashtype == 3) {
 610                 if ((s_last - s_first) == (CFG_STM_SECT - 1)) {
 611                         if (prot == 0) {
 612                                 dspi_tx(ser_flash_cs, 0x00, SER_WREN);
 613                                 dspi_rx();
 614
 615                                 status = serial_flash_read_status(ser_flash_cs);
 616                                 if (((status & 0x9C) != 0)
 617                                     && ((status & 0x02) != 0x02)) {
 618                                         printf("Can't erase flash\n");
 619                                         return 1;
 620                                 }
 621
 622                                 dspi_tx(ser_flash_cs, 0x00, SER_BULK_ERASE);
 623                                 dspi_rx();
 624
 625                                 count = 0;
 626                                 start = get_timer(0);
 627                                 do {
 628                                         status =
 629                                             serial_flash_read_status
 630                                             (ser_flash_cs);
 631
 632                                         if (count++ > 0x10000) {
 633                                                 spin_wheel();
 634                                                 count = 0;
 635                                         }
 636
 637                                         if (get_timer(start) >
 638                                             CFG_FLASH_ERASE_TOUT) {
 639                                                 printf("Timeout\n");
 640                                                 return 1;
 641                                         }
 642                                 } while (status & 0x01);
 643
 644                                 printf("\b. done\n");
 645                                 return 0;
 646                         } else if (prot == CFG_STM_SECT) {
 647                                 return 1;
 648                         }
 649                 }
 650         }
 651 #endif
 652         /* Start erase on unprotected sectors */
 653         for (sect = s_first; sect <= s_last; sect++) {
 654                 if (info->protect[sect] == 0) { /* not protected */
 655
 656                         FPWV *addr = (FPWV *) (info->start[sect]);
 657                         int min = 0;
 658
 659                         printf(".");
 660
 661                         /* arm simple, non interrupt dependent timer */
 662                         start = get_timer(0);
 663
 664                         switch (flashtype) {
 665                         case 1:
 666                                 {
 667                                         FPWV *base;     /* first address in bank */
 668                                         FPWV *atmeladdr;
 669
 670                                         flag = disable_interrupts();
 671
 672                                         atmeladdr = (FPWV *) addr;      /* concatenate to 8 bit */
 673                                         base = (FPWV *) (CFG_ATMEL_BASE);       /* First sector */
 674
 675                                         base[FLASH_CYCLE1] = (u8) 0x00AA00AA;   /* unlock */
 676                                         base[FLASH_CYCLE2] = (u8) 0x00550055;   /* unlock */
 677                                         base[FLASH_CYCLE1] = (u8) 0x00800080;   /* erase mode */
 678                                         base[FLASH_CYCLE1] = (u8) 0x00AA00AA;   /* unlock */
 679                                         base[FLASH_CYCLE2] = (u8) 0x00550055;   /* unlock */
 680                                         *atmeladdr = (u8) 0x00300030;   /* erase sector */
 681
 682                                         if (flag)
 683                                                 enable_interrupts();
 684
 685                                         while ((*atmeladdr & (u8) 0x00800080) !=
 686                                                (u8) 0x00800080) {
 687                                                 if (get_timer(start) >
 688                                                     CFG_FLASH_ERASE_TOUT) {
 689                                                         printf("Timeout\n");
 690                                                         *atmeladdr = (u8) 0x00F000F0;   /* reset to read mode */
 691
 692                                                         rcode = 1;
 693                                                         break;
 694                                                 }
 695                                         }
 696
 697                                         *atmeladdr = (u8) 0x00F000F0;   /* reset to read mode */
 698                                         break;
 699                                 }
 700
 701                         case 2:
 702                                 {
 703                                         *addr = (FPW) INTEL_READID;
 704                                         min = addr[INTEL_CFI_TERB] & 0xff;
 705                                         min = 1 << min; /* ms */
 706                                         min = (min / info->sector_count) * 1000;
 707
 708                                         /* start erase block */
 709                                         *addr = (FPW) INTEL_CLEAR;      /* clear status register */
 710                                         *addr = (FPW) INTEL_ERASE;      /* erase setup */
 711                                         *addr = (FPW) INTEL_CONFIRM;    /* erase confirm */
 712
 713                                         while ((*addr & (FPW) INTEL_FINISHED) !=
 714                                                (FPW) INTEL_FINISHED) {
 715
 716                                                 if (get_timer(start) >
 717                                                     CFG_FLASH_ERASE_TOUT) {
 718                                                         printf("Timeout\n");
 719                                                         *addr = (FPW) INTEL_SUSERASE;   /* suspend erase     */
 720                                                         *addr = (FPW) INTEL_RESET;      /* reset to read mode */
 721
 722                                                         rcode = 1;
 723                                                         break;
 724                                                 }
 725                                         }
 726
 727                                         *addr = (FPW) INTEL_RESET;      /* resest to read mode          */
 728                                         break;
 729                                 }
 730
 731 #if defined(CONFIG_SERIAL_FLASH) && defined(CONFIG_CF_DSPI)
 732                         case 3:
 733                                 {
 734                                         u8 sec = ((ulong) addr >> 16) & 0xFF;
 735
 736                                         dspi_tx(ser_flash_cs, 0x00, SER_WREN);
 737                                         dspi_rx();
 738                                         status =
 739                                             serial_flash_read_status
 740                                             (ser_flash_cs);
 741                                         if (((status & 0x9C) != 0)
 742                                             && ((status & 0x02) != 0x02)) {
 743                                                 printf("Error Programming\n");
 744                                                 return 1;
 745                                         }
 746
 747                                         dspi_tx(ser_flash_cs, 0x80,
 748                                                 SER_SECT_ERASE);
 749                                         dspi_tx(ser_flash_cs, 0x80, sec);
 750                                         dspi_tx(ser_flash_cs, 0x80, 0);
 751                                         dspi_tx(ser_flash_cs, 0x00, 0);
 752
 753                                         dspi_rx();
 754                                         dspi_rx();
 755                                         dspi_rx();
 756                                         dspi_rx();
 757
 758                                         do {
 759                                                 status =
 760                                                     serial_flash_read_status
 761                                                     (ser_flash_cs);
 762
 763                                                 if (get_timer(start) >
 764                                                     CFG_FLASH_ERASE_TOUT) {
 765                                                         printf("Timeout\n");
 766                                                         return 1;
 767                                                 }
 768                                         } while (status & 0x01);
 769
 770                                         break;
 771                                 }
 772 #endif
 773                         }       /* switch (flashtype) */
 774                 }
 775         }
 776         printf(" done\n");
 777
 778         return rcode;
 779 }
 780
 781 int write_buff(flash_info_t * info, uchar * src, ulong addr, ulong cnt)
 782 {
 783         int count;
 784
 785         if (info->flash_id == FLASH_UNKNOWN)
 786                 return 4;
 787
 788         switch (info->flash_id & FLASH_VENDMASK) {
 789         case FLASH_MAN_ATM:
 790                 {
 791                         u16 data = 0;
 792                         int bytes;      /* number of bytes to program in current word */
 793                         int left;       /* number of bytes left to program */
 794                         int i, res;
 795
 796                         for (left = cnt, res = 0;
 797                              left > 0 && res == 0;
 798                              addr += sizeof(data), left -=
 799                              sizeof(data) - bytes) {
 800
 801                                 bytes = addr & (sizeof(data) - 1);
 802                                 addr &= ~(sizeof(data) - 1);
 803
 804                                 /* combine source and destination data so can program
 805                                  * an entire word of 16 or 32 bits
 806                                  */
 807                                 for (i = 0; i < sizeof(data); i++) {
 808                                         data <<= 8;
 809                                         if (i < bytes || i - bytes >= left)
 810                                                 data += *((uchar *) addr + i);
 811                                         else
 812                                                 data += *src++;
 813                                 }
 814
 815                                 data = (data >> 8) | (data << 8);
 816                                 res = write_word_atm(info, (FPWV *) addr, data);
 817                         }
 818                         return res;
 819                 }               /* case FLASH_MAN_ATM */
 820
 821         case FLASH_MAN_INTEL:
 822                 {
 823                         ulong cp, wp;
 824                         u16 data;
 825                         int i, l, rc, port_width;
 826
 827                         /* get lower word aligned address */
 828                         wp = addr;
 829                         port_width = sizeof(FPW);
 830
 831                         /*
 832                          * handle unaligned start bytes
 833                          */
 834                         if ((l = addr - wp) != 0) {
 835                                 data = 0;
 836                                 for (i = 0, cp = wp; i < l; ++i, ++cp) {
 837                                         data = (data << 8) | (*(uchar *) cp);
 838                                 }
 839
 840                                 for (; i < port_width && cnt > 0; ++i) {
 841                                         data = (data << 8) | *src++;
 842                                         --cnt;
 843                                         ++cp;
 844                                 }
 845
 846                                 for (; cnt == 0 && i < port_width; ++i, ++cp)
 847                                         data = (data << 8) | (*(uchar *) cp);
 848
 849                                 if ((rc = write_data(info, wp, data)) != 0)
 850                                         return (rc);
 851
 852                                 wp += port_width;
 853                         }
 854
 855                         if (cnt > WR_BLOCK) {
 856                                 /*
 857                                  * handle word aligned part
 858                                  */
 859                                 count = 0;
 860                                 while (cnt >= WR_BLOCK) {
 861
 862                                         if ((rc =
 863                                              write_data_block(info,
 864                                                               (ulong) src,
 865                                                               wp)) != 0)
 866                                                 return (rc);
 867
 868                                         wp += WR_BLOCK;
 869                                         src += WR_BLOCK;
 870                                         cnt -= WR_BLOCK;
 871
 872                                         if (count++ > 0x800) {
 873                                                 spin_wheel();
 874                                                 count = 0;
 875                                         }
 876                                 }
 877                         }
 878
 879                         /* handle word aligned part */
 880                         if (cnt < WR_BLOCK) {
 881                                 /*
 882                                  * handle word aligned part
 883                                  */
 884                                 count = 0;
 885                                 while (cnt >= port_width) {
 886                                         data = 0;
 887                                         for (i = 0; i < port_width; ++i)
 888                                                 data = (data << 8) | *src++;
 889
 890                                         if ((rc =
 891                                              write_data(info,
 892                                                         (ulong) ((FPWV *) wp),
 893                                                         (FPW) (data))) != 0)
 894                                                 return (rc);
 895
 896                                         wp += port_width;
 897                                         cnt -= port_width;
 898                                         if (count++ > 0x800) {
 899                                                 spin_wheel();
 900                                                 count = 0;
 901                                         }
 902                                 }
 903                         }
 904
 905                         if (cnt == 0)
 906                                 return ERR_OK;
 907
 908                         /*
 909                          * handle unaligned tail bytes
 910                          */
 911                         data = 0;
 912                         for (i = 0, cp = wp; i < port_width && cnt > 0;
 913                              ++i, ++cp) {
 914                                 data = (data << 8) | (*src++);
 915                                 --cnt;
 916                         }
 917                         for (; i < port_width; ++i, ++cp) {
 918                                 data = (data << 8) | (*(uchar *) cp);
 919                         }
 920
 921                         return write_data(info, (ulong) ((FPWV *) wp),
 922                                           (FPW) data);
 923
 924                 }               /* case FLASH_MAN_INTEL */
 925
 926 #if defined(CONFIG_SERIAL_FLASH) && defined(CONFIG_CF_DSPI)
 927         case FLASH_MAN_STM:
 928                 {
 929                         ulong wp;
 930                         u8 *data = (u8 *) src;
 931                         int left;       /* number of bytes left to program */
 932
 933                         wp = addr;
 934
 935                         /* page align, each page is 256 bytes */
 936                         if ((wp % 0x100) != 0) {
 937                                 left = (0x100 - (wp & 0xFF));
 938                                 write_ser_data(info, wp, data, left);
 939                                 cnt -= left;
 940                                 wp += left;
 941                                 data += left;
 942                         }
 943
 944                         /* page program - 256 bytes at a time */
 945                         if (cnt > 255) {
 946                                 count = 0;
 947                                 while (cnt >= 0x100) {
 948                                         write_ser_data(info, wp, data, 0x100);
 949                                         cnt -= 0x100;
 950                                         wp += 0x100;
 951                                         data += 0x100;
 952
 953                                         if (count++ > 0x400) {
 954                                                 spin_wheel();
 955                                                 count = 0;
 956                                         }
 957                                 }
 958                         }
 959
 960                         /* remainint bytes */
 961                         if (cnt && (cnt < 256)) {
 962                                 write_ser_data(info, wp, data, cnt);
 963                                 wp += cnt;
 964                                 data += cnt;
 965                                 cnt -= cnt;
 966                         }
 967
 968                         printf("\b.");
 969                 }
 970 #endif
 971         }                       /* switch */
 972
 973         return ERR_OK;
 974 }
 975
 976 /*-----------------------------------------------------------------------
 977  * Write a word or halfword to Flash, returns:
 978  * 0 - OK
 979  * 1 - write timeout
 980  * 2 - Flash not erased
 981  */
 982 int write_data_block(flash_info_t * info, ulong src, ulong dest)
 983 {
 984         FPWV *srcaddr = (FPWV *) src;
 985         FPWV *dstaddr = (FPWV *) dest;
 986         ulong start;
 987         int flag, i;
 988
 989         /* Check if Flash is (sufficiently) erased */
 990         for (i = 0; i < WR_BLOCK; i++)
 991                 if ((*dstaddr++ & 0xff) != 0xff) {
 992                         printf("not erased at %08lx (%lx)\n",
 993                                (ulong) dstaddr, *dstaddr);
 994                         return (2);
 995                 }
 996
 997         dstaddr = (FPWV *) dest;
 998
 999         /* Disable interrupts which might cause a timeout here */
1000         flag = disable_interrupts();
1001
1002         *dstaddr = (FPW) INTEL_WRBLK;   /* write block setup */
1003
1004         if (flag)
1005                 enable_interrupts();
1006
1007         /* arm simple, non interrupt dependent timer */
1008         start = get_timer(0);
1009
1010         /* wait while polling the status register */
1011         while ((*dstaddr & (FPW) INTEL_FINISHED) != (FPW) INTEL_OK) {
1012                 if (get_timer(start) > CFG_FLASH_WRITE_TOUT) {
1013                         *dstaddr = (FPW) INTEL_RESET;   /* restore read mode */
1014                         return (1);
1015                 }
1016         }
1017
1018         *dstaddr = (FPW) WR_BLOCK - 1;  /* write 32 to buffer */
1019         for (i = 0; i < WR_BLOCK; i++)
1020                 *dstaddr++ = *srcaddr++;
1021
1022         dstaddr -= 1;
1023         *dstaddr = (FPW) INTEL_CONFIRM; /* write 32 to buffer */
1024
1025         /* arm simple, non interrupt dependent timer */
1026         start = get_timer(0);
1027
1028         /* wait while polling the status register */
1029         while ((*dstaddr & (FPW) INTEL_FINISHED) != (FPW) INTEL_OK) {
1030                 if (get_timer(start) > CFG_FLASH_WRITE_TOUT) {
1031                         *dstaddr = (FPW) INTEL_RESET;   /* restore read mode */
1032                         return (1);
1033                 }
1034         }
1035
1036         *dstaddr = (FPW) INTEL_RESET;   /* restore read mode */
1037
1038         return (0);
1039 }
1040
1041 /*-----------------------------------------------------------------------
1042  * Write a word or halfword to Flash, returns:
1043  * 0 - OK
1044  * 1 - write timeout
1045  * 2 - Flash not erased
1046  */
1047 int write_data(flash_info_t * info, ulong dest, FPW data)
1048 {
1049         FPWV *addr = (FPWV *) dest;
1050         ulong start;
1051         int flag;
1052
1053         /* Check if Flash is (sufficiently) erased */
1054         if ((*addr & data) != data) {
1055                 printf("not erased at %08lx (%lx)\n", (ulong) addr,
1056                        (ulong) * addr);
1057                 return (2);
1058         }
1059
1060         /* Disable interrupts which might cause a timeout here */
1061         flag = (int)disable_interrupts();
1062
1063         *addr = (FPW) INTEL_CLEAR;
1064         *addr = (FPW) INTEL_RESET;
1065
1066         *addr = (FPW) INTEL_WRSETUP;    /* write setup */
1067         *addr = data;
1068
1069         if (flag)
1070                 enable_interrupts();
1071
1072         /* arm simple, non interrupt dependent timer */
1073         start = get_timer(0);
1074
1075         /* wait while polling the status register */
1076         while ((*addr & (FPW) INTEL_OK) != (FPW) INTEL_OK) {
1077                 if (get_timer(start) > CFG_FLASH_WRITE_TOUT) {
1078                         *addr = (FPW) INTEL_SUSERASE;   /* suspend mode */
1079                         *addr = (FPW) INTEL_CLEAR;      /* clear status */
1080                         *addr = (FPW) INTEL_RESET;      /* reset */
1081                         return (1);
1082                 }
1083         }
1084
1085         *addr = (FPW) INTEL_CLEAR;      /* clear status */
1086         *addr = (FPW) INTEL_RESET;      /* restore read mode */
1087
1088         return (0);
1089 }
1090
1091 #if defined(CONFIG_SERIAL_FLASH) && defined(CONFIG_CF_DSPI)
1092 int write_ser_data(flash_info_t * info, ulong dest, uchar * data, ulong cnt)
1093 {
1094         ulong start;
1095         int status, i;
1096         u8 flashdata;
1097
1098         /* Check if Flash is (sufficiently) erased */
1099         dspi_tx(ser_flash_cs, 0x80, SER_READ);
1100         dspi_tx(ser_flash_cs, 0x80, (dest >> 16) & 0xFF);
1101         dspi_tx(ser_flash_cs, 0x80, (dest >> 8) & 0xFF);
1102         dspi_tx(ser_flash_cs, 0x80, dest & 0xFF);
1103         dspi_rx();
1104         dspi_rx();
1105         dspi_rx();
1106         dspi_rx();
1107         dspi_tx(ser_flash_cs, 0x80, 0);
1108         flashdata = dspi_rx();
1109         dspi_tx(ser_flash_cs, 0x00, 0);
1110         dspi_rx();
1111
1112         if ((flashdata & *data) != *data) {
1113                 printf("not erased at %08lx (%lx)\n", (ulong) dest,
1114                        (ulong) flashdata);
1115                 return (2);
1116         }
1117
1118         dspi_tx(ser_flash_cs, 0x00, SER_WREN);
1119         dspi_rx();
1120
1121         status = serial_flash_read_status(ser_flash_cs);
1122         if (((status & 0x9C) != 0) && ((status & 0x02) != 0x02)) {
1123                 printf("Error Programming\n");
1124                 return 1;
1125         }
1126
1127         start = get_timer(0);
1128
1129         dspi_tx(ser_flash_cs, 0x80, SER_PAGE_PROG);
1130         dspi_tx(ser_flash_cs, 0x80, ((dest & 0xFF0000) >> 16));
1131         dspi_tx(ser_flash_cs, 0x80, ((dest & 0xFF00) >> 8));
1132         dspi_tx(ser_flash_cs, 0x80, (dest & 0xFF));
1133         dspi_rx();
1134         dspi_rx();
1135         dspi_rx();
1136         dspi_rx();
1137
1138         for (i = 0; i < (cnt - 1); i++) {
1139                 dspi_tx(ser_flash_cs, 0x80, *data);
1140                 dspi_rx();
1141                 data++;
1142         }
1143
1144         dspi_tx(ser_flash_cs, 0x00, *data);
1145         dspi_rx();
1146
1147         do {
1148                 status = serial_flash_read_status(ser_flash_cs);
1149
1150                 if (get_timer(start) > CFG_FLASH_ERASE_TOUT) {
1151                         printf("Timeout\n");
1152                         return 1;
1153                 }
1154         } while (status & 0x01);
1155
1156         return (0);
1157 }
1158 #endif
1159
1160 /*-----------------------------------------------------------------------
1161  * Write a word to Flash for ATMEL FLASH
1162  * A word is 16 bits, whichever the bus width of the flash bank
1163  * (not an individual chip) is.
1164  *
1165  * returns:
1166  * 0 - OK
1167  * 1 - write timeout
1168  * 2 - Flash not erased
1169  */
1170 int write_word_atm(flash_info_t * info, volatile u8 * dest, u16 data)
1171 {
1172         ulong start;
1173         int flag, i;
1174         int res = 0;            /* result, assume success */
1175         FPWV *base;             /* first address in flash bank */
1176
1177         /* Check if Flash is (sufficiently) erased */
1178         if ((*((volatile u16 *)dest) & data) != data) {
1179                 return (2);
1180         }
1181
1182         base = (FPWV *) (CFG_ATMEL_BASE);
1183
1184         for (i = 0; i < sizeof(u16); i++) {
1185                 /* Disable interrupts which might cause a timeout here */
1186                 flag = disable_interrupts();
1187
1188                 base[FLASH_CYCLE1] = (u8) 0x00AA00AA;   /* unlock */
1189                 base[FLASH_CYCLE2] = (u8) 0x00550055;   /* unlock */
1190                 base[FLASH_CYCLE1] = (u8) 0x00A000A0;   /* selects program mode */
1191
1192                 *dest = data;   /* start programming the data */
1193
1194                 /* re-enable interrupts if necessary */
1195                 if (flag)
1196                         enable_interrupts();
1197
1198                 start = get_timer(0);
1199
1200                 /* data polling for D7 */
1201                 while (res == 0
1202                        && (*dest & (u8) 0x00800080) !=
1203                        (data & (u8) 0x00800080)) {
1204                         if (get_timer(start) > CFG_FLASH_WRITE_TOUT) {
1205                                 *dest = (u8) 0x00F000F0;        /* reset bank */
1206                                 res = 1;
1207                         }
1208                 }
1209
1210                 *dest++ = (u8) 0x00F000F0;      /* reset bank */
1211                 data >>= 8;
1212         }
1213
1214         return (res);
1215 }
1216
1217 void inline spin_wheel(void)
1218 {
1219         static int p = 0;
1220         static char w[] = "\\/-";
1221
1222         printf("\010%c", w[p]);
1223         (++p == 3) ? (p = 0) : 0;
1224 }
1225
1226 #ifdef CFG_FLASH_PROTECTION
1227 /*-----------------------------------------------------------------------
1228  */
1229 int flash_real_protect(flash_info_t * info, long sector, int prot)
1230 {
1231         int rcode = 0;          /* assume success */
1232         FPWV *addr;             /* address of sector */
1233         FPW value;
1234
1235         addr = (FPWV *) (info->start[sector]);
1236
1237         switch (info->flash_id & FLASH_TYPEMASK) {
1238         case FLASH_28F160C3B:
1239         case FLASH_28F160C3T:
1240         case FLASH_28F320C3B:
1241         case FLASH_28F320C3T:
1242         case FLASH_28F640C3B:
1243         case FLASH_28F640C3T:
1244                 *addr = (FPW) INTEL_RESET;      /* make sure in read mode */
1245                 *addr = (FPW) INTEL_LOCKBIT;    /* lock command setup */
1246
1247                 if (prot)
1248                         *addr = (FPW) INTEL_PROTECT;    /* lock sector */
1249                 else
1250                         *addr = (FPW) INTEL_CONFIRM;    /* unlock sector */
1251
1252                 /* now see if it really is locked/unlocked as requested */
1253                 *addr = (FPW) INTEL_READID;
1254
1255                 /* read sector protection at sector address, (A7 .. A0) = 0x02.
1256                  * D0 = 1 for each device if protected.
1257                  * If at least one device is protected the sector is marked
1258                  * protected, but return failure. Mixed protected and
1259                  * unprotected devices within a sector should never happen.
1260                  */
1261                 value = addr[2] & (FPW) INTEL_PROTECT;
1262                 if (value == 0)
1263                         info->protect[sector] = 0;
1264                 else if (value == (FPW) INTEL_PROTECT)
1265                         info->protect[sector] = 1;
1266                 else {
1267                         /* error, mixed protected and unprotected */
1268                         rcode = 1;
1269                         info->protect[sector] = 1;
1270                 }
1271                 if (info->protect[sector] != prot)
1272                         rcode = 1;      /* failed to protect/unprotect as requested */
1273
1274                 /* reload all protection bits from hardware for now */
1275                 flash_sync_real_protect(info);
1276                 break;
1277
1278         default:
1279                 /* no hardware protect that we support */
1280                 info->protect[sector] = prot;
1281                 break;
1282         }
1283
1284         return rcode;
1285 }
1286 #endif
1287 #endif