1 // SPDX-License-Identifier: GPL-2.0+
3 * (C) Copyright 2000-2003
4 * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
9 #include <asm/global_data.h>
10 #include <asm/immap.h>
12 DECLARE_GLOBAL_DATA_PTR;
16 puts ("Board: Freescale M5282EVB Evaluation Board\n");
22 u32 dramsize, i, dramclk;
24 dramsize = CONFIG_SYS_SDRAM_SIZE * 0x100000;
25 for (i = 0x13; i < 0x20; i++) {
26 if (dramsize == (1 << i))
31 if (!(MCFSDRAMC_DACR0 & MCFSDRAMC_DACR_RE))
33 dramclk = gd->bus_clk / (CONFIG_SYS_HZ * CONFIG_SYS_HZ);
35 /* Initialize DRAM Control Register: DCR */
37 | MCFSDRAMC_DCR_RTIM_6
38 | MCFSDRAMC_DCR_RC((15 * dramclk)>>4));
41 /* Initialize DACR0 */
43 | MCFSDRAMC_DACR_BASE(CONFIG_SYS_SDRAM_BASE)
44 | MCFSDRAMC_DACR_CASL(1)
45 | MCFSDRAMC_DACR_CBM(3)
46 | MCFSDRAMC_DACR_PS_32);
51 | ((dramsize - 1) & 0xFFFC0000)
55 /* Set IP (bit 3) in DACR */
56 MCFSDRAMC_DACR0 |= MCFSDRAMC_DACR_IP;
59 /* Wait 30ns to allow banks to precharge */
60 for (i = 0; i < 5; i++) {
64 /* Write to this block to initiate precharge */
65 *(u32 *)(CONFIG_SYS_SDRAM_BASE) = 0xA5A59696;
68 /* Set RE (bit 15) in DACR */
69 MCFSDRAMC_DACR0 |= MCFSDRAMC_DACR_RE;
72 /* Wait for at least 8 auto refresh cycles to occur */
73 for (i = 0; i < 2000; i++) {
77 /* Finish the configuration by issuing the IMRS. */
78 MCFSDRAMC_DACR0 |= MCFSDRAMC_DACR_IMRS;
81 /* Write to the SDRAM Mode Register */
82 *(u32 *)(CONFIG_SYS_SDRAM_BASE + 0x400) = 0xA5A59696;
84 gd->ram_size = dramsize;