board/freescale/lx2160a/lx2160a.c

   1 // SPDX-License-Identifier: GPL-2.0+
   2 /*
   3  * Copyright 2018-2020 NXP
   4  */
   5
   6 #include <common.h>
   7 #include <clock_legacy.h>
   8 #include <dm.h>
   9 #include <dm/platform_data/serial_pl01x.h>
  10 #include <i2c.h>
  11 #include <malloc.h>
  12 #include <errno.h>
  13 #include <netdev.h>
  14 #include <fsl_ddr.h>
  15 #include <fsl_sec.h>
  16 #include <asm/io.h>
  17 #include <fdt_support.h>
  18 #include <linux/libfdt.h>
  19 #include <fsl-mc/fsl_mc.h>
  20 #include <env_internal.h>
  21 #include <efi_loader.h>
  22 #include <asm/arch/mmu.h>
  23 #include <hwconfig.h>
  24 #include <asm/arch/clock.h>
  25 #include <asm/arch/config.h>
  26 #include <asm/arch/fsl_serdes.h>
  27 #include <asm/arch/soc.h>
  28 #include "../common/qixis.h"
  29 #include "../common/vid.h"
  30 #include <fsl_immap.h>
  31 #include <asm/arch-fsl-layerscape/fsl_icid.h>
  32
  33 #ifdef CONFIG_EMC2305
  34 #include "../common/emc2305.h"
  35 #endif
  36
  37 #ifdef CONFIG_TARGET_LX2160AQDS
  38 #define CFG_MUX_I2C_SDHC(reg, value)            ((reg & 0x3f) | value)
  39 #define SET_CFG_MUX1_SDHC1_SDHC(reg)            (reg & 0x3f)
  40 #define SET_CFG_MUX2_SDHC1_SPI(reg, value)      ((reg & 0xcf) | value)
  41 #define SET_CFG_MUX3_SDHC1_SPI(reg, value)      ((reg & 0xf8) | value)
  42 #define SET_CFG_MUX_SDHC2_DSPI(reg, value)      ((reg & 0xf8) | value)
  43 #define SET_CFG_MUX1_SDHC1_DSPI(reg, value)     ((reg & 0x3f) | value)
  44 #define SDHC1_BASE_PMUX_DSPI                    2
  45 #define SDHC2_BASE_PMUX_DSPI                    2
  46 #define IIC5_PMUX_SPI3                          3
  47 #endif /* CONFIG_TARGET_LX2160AQDS */
  48
  49 DECLARE_GLOBAL_DATA_PTR;
  50
  51 static struct pl01x_serial_platdata serial0 = {
  52 #if CONFIG_CONS_INDEX == 0
  53         .base = CONFIG_SYS_SERIAL0,
  54 #elif CONFIG_CONS_INDEX == 1
  55         .base = CONFIG_SYS_SERIAL1,
  56 #else
  57 #error "Unsupported console index value."
  58 #endif
  59         .type = TYPE_PL011,
  60 };
  61
  62 U_BOOT_DEVICE(nxp_serial0) = {
  63         .name = "serial_pl01x",
  64         .platdata = &serial0,
  65 };
  66
  67 static struct pl01x_serial_platdata serial1 = {
  68         .base = CONFIG_SYS_SERIAL1,
  69         .type = TYPE_PL011,
  70 };
  71
  72 U_BOOT_DEVICE(nxp_serial1) = {
  73         .name = "serial_pl01x",
  74         .platdata = &serial1,
  75 };
  76
  77 int select_i2c_ch_pca9547(u8 ch)
  78 {
  79         int ret;
  80
  81 #ifndef CONFIG_DM_I2C
  82         ret = i2c_write(I2C_MUX_PCA_ADDR_PRI, 0, 1, &ch, 1);
  83 #else
  84         struct udevice *dev;
  85
  86         ret = i2c_get_chip_for_busnum(0, I2C_MUX_PCA_ADDR_PRI, 1, &dev);
  87         if (!ret)
  88                 ret = dm_i2c_write(dev, 0, &ch, 1);
  89 #endif
  90         if (ret) {
  91                 puts("PCA: failed to select proper channel\n");
  92                 return ret;
  93         }
  94
  95         return 0;
  96 }
  97
  98 static void uart_get_clock(void)
  99 {
 100         serial0.clock = get_serial_clock();
 101         serial1.clock = get_serial_clock();
 102 }
 103
 104 int board_early_init_f(void)
 105 {
 106 #ifdef CONFIG_SYS_I2C_EARLY_INIT
 107         i2c_early_init_f();
 108 #endif
 109         /* get required clock for UART IP */
 110         uart_get_clock();
 111
 112 #ifdef CONFIG_EMC2305
 113         select_i2c_ch_pca9547(I2C_MUX_CH_EMC2305);
 114         emc2305_init();
 115         set_fan_speed(I2C_EMC2305_PWM);
 116         select_i2c_ch_pca9547(I2C_MUX_CH_DEFAULT);
 117 #endif
 118
 119         fsl_lsch3_early_init_f();
 120         return 0;
 121 }
 122
 123 #ifdef CONFIG_OF_BOARD_FIXUP
 124 int board_fix_fdt(void *fdt)
 125 {
 126         char *reg_names, *reg_name;
 127         int names_len, old_name_len, new_name_len, remaining_names_len;
 128         struct str_map {
 129                 char *old_str;
 130                 char *new_str;
 131         } reg_names_map[] = {
 132                 { "ccsr", "dbi" },
 133                 { "pf_ctrl", "ctrl" }
 134         };
 135         int off = -1, i = 0;
 136
 137         if (IS_SVR_REV(get_svr(), 1, 0))
 138                 return 0;
 139
 140         off = fdt_node_offset_by_compatible(fdt, -1, "fsl,lx2160a-pcie");
 141         while (off != -FDT_ERR_NOTFOUND) {
 142                 fdt_setprop(fdt, off, "compatible", "fsl,ls-pcie",
 143                             strlen("fsl,ls-pcie") + 1);
 144
 145                 reg_names = (char *)fdt_getprop(fdt, off, "reg-names",
 146                                                 &names_len);
 147                 if (!reg_names)
 148                         continue;
 149
 150                 reg_name = reg_names;
 151                 remaining_names_len = names_len - (reg_name - reg_names);
 152                 i = 0;
 153                 while ((i < ARRAY_SIZE(reg_names_map)) && remaining_names_len) {
 154                         old_name_len = strlen(reg_names_map[i].old_str);
 155                         new_name_len = strlen(reg_names_map[i].new_str);
 156                         if (memcmp(reg_name, reg_names_map[i].old_str,
 157                                    old_name_len) == 0) {
 158                                 /* first only leave required bytes for new_str
 159                                  * and copy rest of the string after it
 160                                  */
 161                                 memcpy(reg_name + new_name_len,
 162                                        reg_name + old_name_len,
 163                                        remaining_names_len - old_name_len);
 164                                 /* Now copy new_str */
 165                                 memcpy(reg_name, reg_names_map[i].new_str,
 166                                        new_name_len);
 167                                 names_len -= old_name_len;
 168                                 names_len += new_name_len;
 169                                 i++;
 170                         }
 171
 172                         reg_name = memchr(reg_name, '\0', remaining_names_len);
 173                         if (!reg_name)
 174                                 break;
 175
 176                         reg_name += 1;
 177
 178                         remaining_names_len = names_len -
 179                                               (reg_name - reg_names);
 180                 }
 181
 182                 fdt_setprop(fdt, off, "reg-names", reg_names, names_len);
 183                 off = fdt_node_offset_by_compatible(fdt, off,
 184                                                     "fsl,lx2160a-pcie");
 185         }
 186
 187         return 0;
 188 }
 189 #endif
 190
 191 #if defined(CONFIG_TARGET_LX2160AQDS)
 192 void esdhc_dspi_status_fixup(void *blob)
 193 {
 194         const char esdhc0_path[] = "/soc/esdhc@2140000";
 195         const char esdhc1_path[] = "/soc/esdhc@2150000";
 196         const char dspi0_path[] = "/soc/spi@2100000";
 197         const char dspi1_path[] = "/soc/spi@2110000";
 198         const char dspi2_path[] = "/soc/spi@2120000";
 199
 200         struct ccsr_gur __iomem *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR);
 201         u32 sdhc1_base_pmux;
 202         u32 sdhc2_base_pmux;
 203         u32 iic5_pmux;
 204
 205         /* Check RCW field sdhc1_base_pmux to enable/disable
 206          * esdhc0/dspi0 DT node
 207          */
 208         sdhc1_base_pmux = gur_in32(&gur->rcwsr[FSL_CHASSIS3_RCWSR12_REGSR - 1])
 209                 & FSL_CHASSIS3_SDHC1_BASE_PMUX_MASK;
 210         sdhc1_base_pmux >>= FSL_CHASSIS3_SDHC1_BASE_PMUX_SHIFT;
 211
 212         if (sdhc1_base_pmux == SDHC1_BASE_PMUX_DSPI) {
 213                 do_fixup_by_path(blob, dspi0_path, "status", "okay",
 214                                  sizeof("okay"), 1);
 215                 do_fixup_by_path(blob, esdhc0_path, "status", "disabled",
 216                                  sizeof("disabled"), 1);
 217         } else {
 218                 do_fixup_by_path(blob, esdhc0_path, "status", "okay",
 219                                  sizeof("okay"), 1);
 220                 do_fixup_by_path(blob, dspi0_path, "status", "disabled",
 221                                  sizeof("disabled"), 1);
 222         }
 223
 224         /* Check RCW field sdhc2_base_pmux to enable/disable
 225          * esdhc1/dspi1 DT node
 226          */
 227         sdhc2_base_pmux = gur_in32(&gur->rcwsr[FSL_CHASSIS3_RCWSR13_REGSR - 1])
 228                 & FSL_CHASSIS3_SDHC2_BASE_PMUX_MASK;
 229         sdhc2_base_pmux >>= FSL_CHASSIS3_SDHC2_BASE_PMUX_SHIFT;
 230
 231         if (sdhc2_base_pmux == SDHC2_BASE_PMUX_DSPI) {
 232                 do_fixup_by_path(blob, dspi1_path, "status", "okay",
 233                                  sizeof("okay"), 1);
 234                 do_fixup_by_path(blob, esdhc1_path, "status", "disabled",
 235                                  sizeof("disabled"), 1);
 236         } else {
 237                 do_fixup_by_path(blob, esdhc1_path, "status", "okay",
 238                                  sizeof("okay"), 1);
 239                 do_fixup_by_path(blob, dspi1_path, "status", "disabled",
 240                                  sizeof("disabled"), 1);
 241         }
 242
 243         /* Check RCW field IIC5 to enable dspi2 DT node */
 244         iic5_pmux = gur_in32(&gur->rcwsr[FSL_CHASSIS3_RCWSR12_REGSR - 1])
 245                 & FSL_CHASSIS3_IIC5_PMUX_MASK;
 246         iic5_pmux >>= FSL_CHASSIS3_IIC5_PMUX_SHIFT;
 247
 248         if (iic5_pmux == IIC5_PMUX_SPI3)
 249                 do_fixup_by_path(blob, dspi2_path, "status", "okay",
 250                                  sizeof("okay"), 1);
 251         else
 252                 do_fixup_by_path(blob, dspi2_path, "status", "disabled",
 253                                  sizeof("disabled"), 1);
 254 }
 255 #endif
 256
 257 int esdhc_status_fixup(void *blob, const char *compat)
 258 {
 259 #if defined(CONFIG_TARGET_LX2160AQDS)
 260         /* Enable esdhc and dspi DT nodes based on RCW fields */
 261         esdhc_dspi_status_fixup(blob);
 262 #else
 263         /* Enable both esdhc DT nodes for LX2160ARDB */
 264         do_fixup_by_compat(blob, compat, "status", "okay",
 265                            sizeof("okay"), 1);
 266 #endif
 267         return 0;
 268 }
 269
 270 #if defined(CONFIG_VID)
 271 int i2c_multiplexer_select_vid_channel(u8 channel)
 272 {
 273         return select_i2c_ch_pca9547(channel);
 274 }
 275
 276 int init_func_vid(void)
 277 {
 278         int set_vid;
 279
 280         if (IS_SVR_REV(get_svr(), 1, 0))
 281                 set_vid = adjust_vdd(800);
 282         else
 283                 set_vid = adjust_vdd(0);
 284
 285         if (set_vid < 0)
 286                 printf("core voltage not adjusted\n");
 287
 288         return 0;
 289 }
 290 #endif
 291
 292 int checkboard(void)
 293 {
 294         enum boot_src src = get_boot_src();
 295         char buf[64];
 296         u8 sw;
 297 #ifdef CONFIG_TARGET_LX2160AQDS
 298         int clock;
 299         static const char *const freq[] = {"100", "125", "156.25",
 300                                            "161.13", "322.26", "", "", "",
 301                                            "", "", "", "", "", "", "",
 302                                            "100 separate SSCG"};
 303 #endif
 304
 305         cpu_name(buf);
 306 #ifdef CONFIG_TARGET_LX2160AQDS
 307         printf("Board: %s-QDS, ", buf);
 308 #else
 309         printf("Board: %s-RDB, ", buf);
 310 #endif
 311
 312         sw = QIXIS_READ(arch);
 313         printf("Board version: %c, boot from ", (sw & 0xf) - 1 + 'A');
 314
 315         if (src == BOOT_SOURCE_SD_MMC) {
 316                 puts("SD\n");
 317         } else if (src == BOOT_SOURCE_SD_MMC2) {
 318                 puts("eMMC\n");
 319         } else {
 320                 sw = QIXIS_READ(brdcfg[0]);
 321                 sw = (sw >> QIXIS_XMAP_SHIFT) & QIXIS_XMAP_MASK;
 322                 switch (sw) {
 323                 case 0:
 324                 case 4:
 325                         puts("FlexSPI DEV#0\n");
 326                         break;
 327                 case 1:
 328                         puts("FlexSPI DEV#1\n");
 329                         break;
 330                 case 2:
 331                 case 3:
 332                         puts("FlexSPI EMU\n");
 333                         break;
 334                 default:
 335                         printf("invalid setting, xmap: %d\n", sw);
 336                         break;
 337                 }
 338         }
 339 #ifdef CONFIG_TARGET_LX2160AQDS
 340         printf("FPGA: v%d (%s), build %d",
 341                (int)QIXIS_READ(scver), qixis_read_tag(buf),
 342                (int)qixis_read_minor());
 343         /* the timestamp string contains "\n" at the end */
 344         printf(" on %s", qixis_read_time(buf));
 345
 346         puts("SERDES1 Reference : ");
 347         sw = QIXIS_READ(brdcfg[2]);
 348         clock = sw >> 4;
 349         printf("Clock1 = %sMHz ", freq[clock]);
 350         clock = sw & 0x0f;
 351         printf("Clock2 = %sMHz", freq[clock]);
 352
 353         sw = QIXIS_READ(brdcfg[3]);
 354         puts("\nSERDES2 Reference : ");
 355         clock = sw >> 4;
 356         printf("Clock1 = %sMHz ", freq[clock]);
 357         clock = sw & 0x0f;
 358         printf("Clock2 = %sMHz", freq[clock]);
 359
 360         sw = QIXIS_READ(brdcfg[12]);
 361         puts("\nSERDES3 Reference : ");
 362         clock = sw >> 4;
 363         printf("Clock1 = %sMHz Clock2 = %sMHz\n", freq[clock], freq[clock]);
 364 #else
 365         printf("FPGA: v%d.%d\n", QIXIS_READ(scver), QIXIS_READ(tagdata));
 366
 367         puts("SERDES1 Reference: Clock1 = 161.13MHz Clock2 = 161.13MHz\n");
 368         puts("SERDES2 Reference: Clock1 = 100MHz Clock2 = 100MHz\n");
 369         puts("SERDES3 Reference: Clock1 = 100MHz Clock2 = 100MHz\n");
 370 #endif
 371         return 0;
 372 }
 373
 374 #ifdef CONFIG_TARGET_LX2160AQDS
 375 /*
 376  * implementation of CONFIG_ESDHC_DETECT_QUIRK Macro.
 377  */
 378 u8 qixis_esdhc_detect_quirk(void)
 379 {
 380         /* for LX2160AQDS res1[1] @ offset 0x1A is SDHC1 Control/Status (SDHC1)
 381          * SDHC1 Card ID:
 382          * Specifies the type of card installed in the SDHC1 adapter slot.
 383          * 000= (reserved)
 384          * 001= eMMC V4.5 adapter is installed.
 385          * 010= SD/MMC 3.3V adapter is installed.
 386          * 011= eMMC V4.4 adapter is installed.
 387          * 100= eMMC V5.0 adapter is installed.
 388          * 101= MMC card/Legacy (3.3V) adapter is installed.
 389          * 110= SDCard V2/V3 adapter installed.
 390          * 111= no adapter is installed.
 391          */
 392         return ((QIXIS_READ(res1[1]) & QIXIS_SDID_MASK) !=
 393                  QIXIS_ESDHC_NO_ADAPTER);
 394 }
 395
 396 int config_board_mux(void)
 397 {
 398         u8 reg11, reg5, reg13;
 399         struct ccsr_gur __iomem *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR);
 400         u32 sdhc1_base_pmux;
 401         u32 sdhc2_base_pmux;
 402         u32 iic5_pmux;
 403
 404         /* Routes {I2C2_SCL, I2C2_SDA} to SDHC1 as {SDHC1_CD_B, SDHC1_WP}.
 405          * Routes {I2C3_SCL, I2C3_SDA} to CAN transceiver as {CAN1_TX,CAN1_RX}.
 406          * Routes {I2C4_SCL, I2C4_SDA} to CAN transceiver as {CAN2_TX,CAN2_RX}.
 407          * Qixis and remote systems are isolated from the I2C1 bus.
 408          * Processor connections are still available.
 409          * SPI2 CS2_B controls EN25S64 SPI memory device.
 410          * SPI3 CS2_B controls EN25S64 SPI memory device.
 411          * EC2 connects to PHY #2 using RGMII protocol.
 412          * CLK_OUT connects to FPGA for clock measurement.
 413          */
 414
 415         reg5 = QIXIS_READ(brdcfg[5]);
 416         reg5 = CFG_MUX_I2C_SDHC(reg5, 0x40);
 417         QIXIS_WRITE(brdcfg[5], reg5);
 418
 419         /* Check RCW field sdhc1_base_pmux
 420          * esdhc0 : sdhc1_base_pmux = 0
 421          * dspi0  : sdhc1_base_pmux = 2
 422          */
 423         sdhc1_base_pmux = gur_in32(&gur->rcwsr[FSL_CHASSIS3_RCWSR12_REGSR - 1])
 424                 & FSL_CHASSIS3_SDHC1_BASE_PMUX_MASK;
 425         sdhc1_base_pmux >>= FSL_CHASSIS3_SDHC1_BASE_PMUX_SHIFT;
 426
 427         if (sdhc1_base_pmux == SDHC1_BASE_PMUX_DSPI) {
 428                 reg11 = QIXIS_READ(brdcfg[11]);
 429                 reg11 = SET_CFG_MUX1_SDHC1_DSPI(reg11, 0x40);
 430                 QIXIS_WRITE(brdcfg[11], reg11);
 431         } else {
 432                 /* - Routes {SDHC1_CMD, SDHC1_CLK } to SDHC1 adapter slot.
 433                  *          {SDHC1_DAT3, SDHC1_DAT2} to SDHC1 adapter slot.
 434                  *          {SDHC1_DAT1, SDHC1_DAT0} to SDHC1 adapter slot.
 435                  */
 436                 reg11 = QIXIS_READ(brdcfg[11]);
 437                 reg11 = SET_CFG_MUX1_SDHC1_SDHC(reg11);
 438                 QIXIS_WRITE(brdcfg[11], reg11);
 439         }
 440
 441         /* Check RCW field sdhc2_base_pmux
 442          * esdhc1 : sdhc2_base_pmux = 0 (default)
 443          * dspi1  : sdhc2_base_pmux = 2
 444          */
 445         sdhc2_base_pmux = gur_in32(&gur->rcwsr[FSL_CHASSIS3_RCWSR13_REGSR - 1])
 446                 & FSL_CHASSIS3_SDHC2_BASE_PMUX_MASK;
 447         sdhc2_base_pmux >>= FSL_CHASSIS3_SDHC2_BASE_PMUX_SHIFT;
 448
 449         if (sdhc2_base_pmux == SDHC2_BASE_PMUX_DSPI) {
 450                 reg13 = QIXIS_READ(brdcfg[13]);
 451                 reg13 = SET_CFG_MUX_SDHC2_DSPI(reg13, 0x01);
 452                 QIXIS_WRITE(brdcfg[13], reg13);
 453         } else {
 454                 reg13 = QIXIS_READ(brdcfg[13]);
 455                 reg13 = SET_CFG_MUX_SDHC2_DSPI(reg13, 0x00);
 456                 QIXIS_WRITE(brdcfg[13], reg13);
 457         }
 458
 459         /* Check RCW field IIC5 to enable dspi2 DT nodei
 460          * dspi2: IIC5 = 3
 461          */
 462         iic5_pmux = gur_in32(&gur->rcwsr[FSL_CHASSIS3_RCWSR12_REGSR - 1])
 463                 & FSL_CHASSIS3_IIC5_PMUX_MASK;
 464         iic5_pmux >>= FSL_CHASSIS3_IIC5_PMUX_SHIFT;
 465
 466         if (iic5_pmux == IIC5_PMUX_SPI3) {
 467                 /* - Routes {SDHC1_DAT4} to SPI3 devices as {SPI3_M_CS0_B}. */
 468                 reg11 = QIXIS_READ(brdcfg[11]);
 469                 reg11 = SET_CFG_MUX2_SDHC1_SPI(reg11, 0x10);
 470                 QIXIS_WRITE(brdcfg[11], reg11);
 471
 472                 /* - Routes {SDHC1_DAT5, SDHC1_DAT6} nowhere.
 473                  * {SDHC1_DAT7, SDHC1_DS } to {nothing, SPI3_M0_CLK }.
 474                  * {I2C5_SCL, I2C5_SDA } to {SPI3_M0_MOSI, SPI3_M0_MISO}.
 475                  */
 476                 reg11 = QIXIS_READ(brdcfg[11]);
 477                 reg11 = SET_CFG_MUX3_SDHC1_SPI(reg11, 0x01);
 478                 QIXIS_WRITE(brdcfg[11], reg11);
 479         } else {
 480                 /*
 481                  * If {SDHC1_DAT4} has been configured to route to SDHC1_VS,
 482                  * do not change it.
 483                  * Otherwise route {SDHC1_DAT4} to SDHC1 adapter slot.
 484                  */
 485                 reg11 = QIXIS_READ(brdcfg[11]);
 486                 if ((reg11 & 0x30) != 0x30) {
 487                         reg11 = SET_CFG_MUX2_SDHC1_SPI(reg11, 0x00);
 488                         QIXIS_WRITE(brdcfg[11], reg11);
 489                 }
 490
 491                 /* - Routes {SDHC1_DAT5, SDHC1_DAT6} to SDHC1 adapter slot.
 492                  * {SDHC1_DAT7, SDHC1_DS } to SDHC1 adapter slot.
 493                  * {I2C5_SCL, I2C5_SDA } to SDHC1 adapter slot.
 494                  */
 495                 reg11 = QIXIS_READ(brdcfg[11]);
 496                 reg11 = SET_CFG_MUX3_SDHC1_SPI(reg11, 0x00);
 497                 QIXIS_WRITE(brdcfg[11], reg11);
 498         }
 499
 500         return 0;
 501 }
 502 #elif defined(CONFIG_TARGET_LX2160ARDB)
 503 int config_board_mux(void)
 504 {
 505         u8 brdcfg;
 506
 507         brdcfg = QIXIS_READ(brdcfg[4]);
 508         /* The BRDCFG4 register controls general board configuration.
 509          *|-------------------------------------------|
 510          *|Field  | Function                          |
 511          *|-------------------------------------------|
 512          *|5      | CAN I/O Enable (net CFG_CAN_EN_B):|
 513          *|CAN_EN | 0= CAN transceivers are disabled. |
 514          *|       | 1= CAN transceivers are enabled.  |
 515          *|-------------------------------------------|
 516          */
 517         brdcfg |= BIT_MASK(5);
 518         QIXIS_WRITE(brdcfg[4], brdcfg);
 519
 520         return 0;
 521 }
 522 #else
 523 int config_board_mux(void)
 524 {
 525         return 0;
 526 }
 527 #endif
 528
 529 unsigned long get_board_sys_clk(void)
 530 {
 531 #ifdef CONFIG_TARGET_LX2160AQDS
 532         u8 sysclk_conf = QIXIS_READ(brdcfg[1]);
 533
 534         switch (sysclk_conf & 0x03) {
 535         case QIXIS_SYSCLK_100:
 536                 return 100000000;
 537         case QIXIS_SYSCLK_125:
 538                 return 125000000;
 539         case QIXIS_SYSCLK_133:
 540                 return 133333333;
 541         }
 542         return 100000000;
 543 #else
 544         return 100000000;
 545 #endif
 546 }
 547
 548 unsigned long get_board_ddr_clk(void)
 549 {
 550 #ifdef CONFIG_TARGET_LX2160AQDS
 551         u8 ddrclk_conf = QIXIS_READ(brdcfg[1]);
 552
 553         switch ((ddrclk_conf & 0x30) >> 4) {
 554         case QIXIS_DDRCLK_100:
 555                 return 100000000;
 556         case QIXIS_DDRCLK_125:
 557                 return 125000000;
 558         case QIXIS_DDRCLK_133:
 559                 return 133333333;
 560         }
 561         return 100000000;
 562 #else
 563         return 100000000;
 564 #endif
 565 }
 566
 567 int board_init(void)
 568 {
 569 #if defined(CONFIG_FSL_MC_ENET) && defined(CONFIG_TARGET_LX2160ARDB)
 570         u32 __iomem *irq_ccsr = (u32 __iomem *)ISC_BASE;
 571 #endif
 572 #ifdef CONFIG_ENV_IS_NOWHERE
 573         gd->env_addr = (ulong)&default_environment[0];
 574 #endif
 575
 576         select_i2c_ch_pca9547(I2C_MUX_CH_DEFAULT);
 577
 578 #if defined(CONFIG_FSL_MC_ENET) && defined(CONFIG_TARGET_LX2160ARDB)
 579         /* invert AQR107 IRQ pins polarity */
 580         out_le32(irq_ccsr + IRQCR_OFFSET / 4, AQR107_IRQ_MASK);
 581 #endif
 582
 583 #ifdef CONFIG_FSL_CAAM
 584         sec_init();
 585 #endif
 586
 587         return 0;
 588 }
 589
 590 void detail_board_ddr_info(void)
 591 {
 592         int i;
 593         u64 ddr_size = 0;
 594
 595         puts("\nDDR    ");
 596         for (i = 0; i < CONFIG_NR_DRAM_BANKS; i++)
 597                 ddr_size += gd->bd->bi_dram[i].size;
 598         print_size(ddr_size, "");
 599         print_ddr_info(0);
 600 }
 601
 602 #ifdef CONFIG_MISC_INIT_R
 603 int misc_init_r(void)
 604 {
 605         config_board_mux();
 606
 607         return 0;
 608 }
 609 #endif
 610
 611 #ifdef CONFIG_FSL_MC_ENET
 612 extern int fdt_fixup_board_phy(void *fdt);
 613
 614 void fdt_fixup_board_enet(void *fdt)
 615 {
 616         int offset;
 617
 618         offset = fdt_path_offset(fdt, "/soc/fsl-mc");
 619
 620         if (offset < 0)
 621                 offset = fdt_path_offset(fdt, "/fsl-mc");
 622
 623         if (offset < 0) {
 624                 printf("%s: fsl-mc node not found in device tree (error %d)\n",
 625                        __func__, offset);
 626                 return;
 627         }
 628
 629         if (get_mc_boot_status() == 0 &&
 630             (is_lazy_dpl_addr_valid() || get_dpl_apply_status() == 0)) {
 631                 fdt_status_okay(fdt, offset);
 632                 fdt_fixup_board_phy(fdt);
 633         } else {
 634                 fdt_status_fail(fdt, offset);
 635         }
 636 }
 637
 638 void board_quiesce_devices(void)
 639 {
 640         fsl_mc_ldpaa_exit(gd->bd);
 641 }
 642 #endif
 643
 644 #ifdef CONFIG_OF_BOARD_SETUP
 645 int ft_board_setup(void *blob, bd_t *bd)
 646 {
 647         int i;
 648         u16 mc_memory_bank = 0;
 649
 650         u64 *base;
 651         u64 *size;
 652         u64 mc_memory_base = 0;
 653         u64 mc_memory_size = 0;
 654         u16 total_memory_banks;
 655
 656         ft_cpu_setup(blob, bd);
 657
 658         fdt_fixup_mc_ddr(&mc_memory_base, &mc_memory_size);
 659
 660         if (mc_memory_base != 0)
 661                 mc_memory_bank++;
 662
 663         total_memory_banks = CONFIG_NR_DRAM_BANKS + mc_memory_bank;
 664
 665         base = calloc(total_memory_banks, sizeof(u64));
 666         size = calloc(total_memory_banks, sizeof(u64));
 667
 668         /* fixup DT for the three GPP DDR banks */
 669         for (i = 0; i < CONFIG_NR_DRAM_BANKS; i++) {
 670                 base[i] = gd->bd->bi_dram[i].start;
 671                 size[i] = gd->bd->bi_dram[i].size;
 672         }
 673
 674 #ifdef CONFIG_RESV_RAM
 675         /* reduce size if reserved memory is within this bank */
 676         if (gd->arch.resv_ram >= base[0] &&
 677             gd->arch.resv_ram < base[0] + size[0])
 678                 size[0] = gd->arch.resv_ram - base[0];
 679         else if (gd->arch.resv_ram >= base[1] &&
 680                  gd->arch.resv_ram < base[1] + size[1])
 681                 size[1] = gd->arch.resv_ram - base[1];
 682         else if (gd->arch.resv_ram >= base[2] &&
 683                  gd->arch.resv_ram < base[2] + size[2])
 684                 size[2] = gd->arch.resv_ram - base[2];
 685 #endif
 686
 687         if (mc_memory_base != 0) {
 688                 for (i = 0; i <= total_memory_banks; i++) {
 689                         if (base[i] == 0 && size[i] == 0) {
 690                                 base[i] = mc_memory_base;
 691                                 size[i] = mc_memory_size;
 692                                 break;
 693                         }
 694                 }
 695         }
 696
 697         fdt_fixup_memory_banks(blob, base, size, total_memory_banks);
 698
 699 #ifdef CONFIG_USB
 700         fsl_fdt_fixup_dr_usb(blob, bd);
 701 #endif
 702
 703 #ifdef CONFIG_FSL_MC_ENET
 704         fdt_fsl_mc_fixup_iommu_map_entry(blob);
 705         fdt_fixup_board_enet(blob);
 706 #endif
 707         fdt_fixup_icid(blob);
 708
 709         return 0;
 710 }
 711 #endif
 712
 713 void qixis_dump_switch(void)
 714 {
 715         int i, nr_of_cfgsw;
 716
 717         QIXIS_WRITE(cms[0], 0x00);
 718         nr_of_cfgsw = QIXIS_READ(cms[1]);
 719
 720         puts("DIP switch settings dump:\n");
 721         for (i = 1; i <= nr_of_cfgsw; i++) {
 722                 QIXIS_WRITE(cms[0], i);
 723                 printf("SW%d = (0x%02x)\n", i, QIXIS_READ(cms[1]));
 724         }
 725 }