board/freescale/lx2160a/lx2160a.c

   1 // SPDX-License-Identifier: GPL-2.0+
   2 /*
   3  * Copyright 2018-2019 NXP
   4  */
   5
   6 #include <common.h>
   7 #include <dm.h>
   8 #include <dm/platform_data/serial_pl01x.h>
   9 #include <i2c.h>
  10 #include <malloc.h>
  11 #include <errno.h>
  12 #include <netdev.h>
  13 #include <fsl_ddr.h>
  14 #include <fsl_sec.h>
  15 #include <asm/io.h>
  16 #include <fdt_support.h>
  17 #include <linux/libfdt.h>
  18 #include <fsl-mc/fsl_mc.h>
  19 #include <env_internal.h>
  20 #include <efi_loader.h>
  21 #include <asm/arch/mmu.h>
  22 #include <hwconfig.h>
  23 #include <asm/arch/clock.h>
  24 #include <asm/arch/config.h>
  25 #include <asm/arch/fsl_serdes.h>
  26 #include <asm/arch/soc.h>
  27 #include "../common/qixis.h"
  28 #include "../common/vid.h"
  29 #include <fsl_immap.h>
  30
  31 #ifdef CONFIG_EMC2305
  32 #include "../common/emc2305.h"
  33 #endif
  34
  35 #ifdef CONFIG_TARGET_LX2160AQDS
  36 #define CFG_MUX_I2C_SDHC(reg, value)            ((reg & 0x3f) | value)
  37 #define SET_CFG_MUX1_SDHC1_SDHC(reg)            (reg & 0x3f)
  38 #define SET_CFG_MUX2_SDHC1_SPI(reg, value)      ((reg & 0xcf) | value)
  39 #define SET_CFG_MUX3_SDHC1_SPI(reg, value)      ((reg & 0xf8) | value)
  40 #define SET_CFG_MUX_SDHC2_DSPI(reg, value)      ((reg & 0xf8) | value)
  41 #define SET_CFG_MUX1_SDHC1_DSPI(reg, value)     ((reg & 0x3f) | value)
  42 #define SDHC1_BASE_PMUX_DSPI                    2
  43 #define SDHC2_BASE_PMUX_DSPI                    2
  44 #define IIC5_PMUX_SPI3                          3
  45 #endif /* CONFIG_TARGET_LX2160AQDS */
  46
  47 DECLARE_GLOBAL_DATA_PTR;
  48
  49 static struct pl01x_serial_platdata serial0 = {
  50 #if CONFIG_CONS_INDEX == 0
  51         .base = CONFIG_SYS_SERIAL0,
  52 #elif CONFIG_CONS_INDEX == 1
  53         .base = CONFIG_SYS_SERIAL1,
  54 #else
  55 #error "Unsupported console index value."
  56 #endif
  57         .type = TYPE_PL011,
  58 };
  59
  60 U_BOOT_DEVICE(nxp_serial0) = {
  61         .name = "serial_pl01x",
  62         .platdata = &serial0,
  63 };
  64
  65 static struct pl01x_serial_platdata serial1 = {
  66         .base = CONFIG_SYS_SERIAL1,
  67         .type = TYPE_PL011,
  68 };
  69
  70 U_BOOT_DEVICE(nxp_serial1) = {
  71         .name = "serial_pl01x",
  72         .platdata = &serial1,
  73 };
  74
  75 int select_i2c_ch_pca9547(u8 ch)
  76 {
  77         int ret;
  78
  79 #ifndef CONFIG_DM_I2C
  80         ret = i2c_write(I2C_MUX_PCA_ADDR_PRI, 0, 1, &ch, 1);
  81 #else
  82         struct udevice *dev;
  83
  84         ret = i2c_get_chip_for_busnum(0, I2C_MUX_PCA_ADDR_PRI, 1, &dev);
  85         if (!ret)
  86                 ret = dm_i2c_write(dev, 0, &ch, 1);
  87 #endif
  88         if (ret) {
  89                 puts("PCA: failed to select proper channel\n");
  90                 return ret;
  91         }
  92
  93         return 0;
  94 }
  95
  96 static void uart_get_clock(void)
  97 {
  98         serial0.clock = get_serial_clock();
  99         serial1.clock = get_serial_clock();
 100 }
 101
 102 int board_early_init_f(void)
 103 {
 104 #ifdef CONFIG_SYS_I2C_EARLY_INIT
 105         i2c_early_init_f();
 106 #endif
 107         /* get required clock for UART IP */
 108         uart_get_clock();
 109
 110 #ifdef CONFIG_EMC2305
 111         select_i2c_ch_pca9547(I2C_MUX_CH_EMC2305);
 112         emc2305_init();
 113         set_fan_speed(I2C_EMC2305_PWM);
 114         select_i2c_ch_pca9547(I2C_MUX_CH_DEFAULT);
 115 #endif
 116
 117         fsl_lsch3_early_init_f();
 118         return 0;
 119 }
 120
 121 #ifdef CONFIG_OF_BOARD_FIXUP
 122 int board_fix_fdt(void *fdt)
 123 {
 124         char *reg_names, *reg_name;
 125         int names_len, old_name_len, new_name_len, remaining_names_len;
 126         struct str_map {
 127                 char *old_str;
 128                 char *new_str;
 129         } reg_names_map[] = {
 130                 { "ccsr", "dip" },
 131                 { "pf_ctrl", "ctrl" }
 132         };
 133         int off = -1, i;
 134
 135         if (IS_SVR_REV(get_svr(), 1, 0))
 136                 return 0;
 137
 138         off = fdt_node_offset_by_compatible(fdt, -1, "fsl,lx2160a-pcie");
 139         while (off != -FDT_ERR_NOTFOUND) {
 140                 fdt_setprop(fdt, off, "compatible", "fsl,ls-pcie",
 141                             strlen("fsl,ls-pcie") + 1);
 142
 143                 reg_names = (char *)fdt_getprop(fdt, off, "reg-names",
 144                                                 &names_len);
 145                 if (!reg_names)
 146                         continue;
 147
 148                 reg_name = reg_names;
 149                 remaining_names_len = names_len - (reg_name - reg_names);
 150                 for (i = 0; (i < ARRAY_SIZE(reg_names_map)) && names_len; i++) {
 151                         old_name_len = strlen(reg_names_map[i].old_str);
 152                         new_name_len = strlen(reg_names_map[i].new_str);
 153                         if (memcmp(reg_name, reg_names_map[i].old_str,
 154                                    old_name_len) == 0) {
 155                                 /* first only leave required bytes for new_str
 156                                  * and copy rest of the string after it
 157                                  */
 158                                 memcpy(reg_name + new_name_len,
 159                                        reg_name + old_name_len,
 160                                        remaining_names_len - old_name_len);
 161                                 /* Now copy new_str */
 162                                 memcpy(reg_name, reg_names_map[i].new_str,
 163                                        new_name_len);
 164                                 names_len -= old_name_len;
 165                                 names_len += new_name_len;
 166                         }
 167
 168                         reg_name = memchr(reg_name, '\0', remaining_names_len);
 169                         if (!reg_name)
 170                                 break;
 171
 172                         reg_name += 1;
 173
 174                         remaining_names_len = names_len -
 175                                               (reg_name - reg_names);
 176                 }
 177
 178                 fdt_setprop(fdt, off, "reg-names", reg_names, names_len);
 179                 off = fdt_node_offset_by_compatible(fdt, off,
 180                                                     "fsl,lx2160a-pcie");
 181         }
 182
 183         return 0;
 184 }
 185 #endif
 186
 187 #if defined(CONFIG_TARGET_LX2160AQDS)
 188 void esdhc_dspi_status_fixup(void *blob)
 189 {
 190         const char esdhc0_path[] = "/soc/esdhc@2140000";
 191         const char esdhc1_path[] = "/soc/esdhc@2150000";
 192         const char dspi0_path[] = "/soc/dspi@2100000";
 193         const char dspi1_path[] = "/soc/dspi@2110000";
 194         const char dspi2_path[] = "/soc/dspi@2120000";
 195
 196         struct ccsr_gur __iomem *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR);
 197         u32 sdhc1_base_pmux;
 198         u32 sdhc2_base_pmux;
 199         u32 iic5_pmux;
 200
 201         /* Check RCW field sdhc1_base_pmux to enable/disable
 202          * esdhc0/dspi0 DT node
 203          */
 204         sdhc1_base_pmux = gur_in32(&gur->rcwsr[FSL_CHASSIS3_RCWSR12_REGSR - 1])
 205                 & FSL_CHASSIS3_SDHC1_BASE_PMUX_MASK;
 206         sdhc1_base_pmux >>= FSL_CHASSIS3_SDHC1_BASE_PMUX_SHIFT;
 207
 208         if (sdhc1_base_pmux == SDHC1_BASE_PMUX_DSPI) {
 209                 do_fixup_by_path(blob, dspi0_path, "status", "okay",
 210                                  sizeof("okay"), 1);
 211                 do_fixup_by_path(blob, esdhc0_path, "status", "disabled",
 212                                  sizeof("disabled"), 1);
 213         } else {
 214                 do_fixup_by_path(blob, esdhc0_path, "status", "okay",
 215                                  sizeof("okay"), 1);
 216                 do_fixup_by_path(blob, dspi0_path, "status", "disabled",
 217                                  sizeof("disabled"), 1);
 218         }
 219
 220         /* Check RCW field sdhc2_base_pmux to enable/disable
 221          * esdhc1/dspi1 DT node
 222          */
 223         sdhc2_base_pmux = gur_in32(&gur->rcwsr[FSL_CHASSIS3_RCWSR13_REGSR - 1])
 224                 & FSL_CHASSIS3_SDHC2_BASE_PMUX_MASK;
 225         sdhc2_base_pmux >>= FSL_CHASSIS3_SDHC2_BASE_PMUX_SHIFT;
 226
 227         if (sdhc2_base_pmux == SDHC2_BASE_PMUX_DSPI) {
 228                 do_fixup_by_path(blob, dspi1_path, "status", "okay",
 229                                  sizeof("okay"), 1);
 230                 do_fixup_by_path(blob, esdhc1_path, "status", "disabled",
 231                                  sizeof("disabled"), 1);
 232         } else {
 233                 do_fixup_by_path(blob, esdhc1_path, "status", "okay",
 234                                  sizeof("okay"), 1);
 235                 do_fixup_by_path(blob, dspi1_path, "status", "disabled",
 236                                  sizeof("disabled"), 1);
 237         }
 238
 239         /* Check RCW field IIC5 to enable dspi2 DT node */
 240         iic5_pmux = gur_in32(&gur->rcwsr[FSL_CHASSIS3_RCWSR12_REGSR - 1])
 241                 & FSL_CHASSIS3_IIC5_PMUX_MASK;
 242         iic5_pmux >>= FSL_CHASSIS3_IIC5_PMUX_SHIFT;
 243
 244         if (iic5_pmux == IIC5_PMUX_SPI3) {
 245                 do_fixup_by_path(blob, dspi2_path, "status", "okay",
 246                                  sizeof("okay"), 1);
 247         }
 248 }
 249 #endif
 250
 251 int esdhc_status_fixup(void *blob, const char *compat)
 252 {
 253 #if defined(CONFIG_TARGET_LX2160AQDS)
 254         /* Enable esdhc and dspi DT nodes based on RCW fields */
 255         esdhc_dspi_status_fixup(blob);
 256 #else
 257         /* Enable both esdhc DT nodes for LX2160ARDB */
 258         do_fixup_by_compat(blob, compat, "status", "okay",
 259                            sizeof("okay"), 1);
 260 #endif
 261         return 0;
 262 }
 263
 264 #if defined(CONFIG_VID)
 265 int i2c_multiplexer_select_vid_channel(u8 channel)
 266 {
 267         return select_i2c_ch_pca9547(channel);
 268 }
 269
 270 int init_func_vid(void)
 271 {
 272         if (adjust_vdd(0) < 0)
 273                 printf("core voltage not adjusted\n");
 274
 275         return 0;
 276 }
 277 #endif
 278
 279 int checkboard(void)
 280 {
 281         enum boot_src src = get_boot_src();
 282         char buf[64];
 283         u8 sw;
 284 #ifdef CONFIG_TARGET_LX2160AQDS
 285         int clock;
 286         static const char *const freq[] = {"100", "125", "156.25",
 287                                            "161.13", "322.26", "", "", "",
 288                                            "", "", "", "", "", "", "",
 289                                            "100 separate SSCG"};
 290 #endif
 291
 292         cpu_name(buf);
 293 #ifdef CONFIG_TARGET_LX2160AQDS
 294         printf("Board: %s-QDS, ", buf);
 295 #else
 296         printf("Board: %s-RDB, ", buf);
 297 #endif
 298
 299         sw = QIXIS_READ(arch);
 300         printf("Board version: %c, boot from ", (sw & 0xf) - 1 + 'A');
 301
 302         if (src == BOOT_SOURCE_SD_MMC) {
 303                 puts("SD\n");
 304         } else {
 305                 sw = QIXIS_READ(brdcfg[0]);
 306                 sw = (sw >> QIXIS_XMAP_SHIFT) & QIXIS_XMAP_MASK;
 307                 switch (sw) {
 308                 case 0:
 309                 case 4:
 310                         puts("FlexSPI DEV#0\n");
 311                         break;
 312                 case 1:
 313                         puts("FlexSPI DEV#1\n");
 314                         break;
 315                 case 2:
 316                 case 3:
 317                         puts("FlexSPI EMU\n");
 318                         break;
 319                 default:
 320                         printf("invalid setting, xmap: %d\n", sw);
 321                         break;
 322                 }
 323         }
 324 #ifdef CONFIG_TARGET_LX2160AQDS
 325         printf("FPGA: v%d (%s), build %d",
 326                (int)QIXIS_READ(scver), qixis_read_tag(buf),
 327                (int)qixis_read_minor());
 328         /* the timestamp string contains "\n" at the end */
 329         printf(" on %s", qixis_read_time(buf));
 330
 331         puts("SERDES1 Reference : ");
 332         sw = QIXIS_READ(brdcfg[2]);
 333         clock = sw >> 4;
 334         printf("Clock1 = %sMHz ", freq[clock]);
 335         clock = sw & 0x0f;
 336         printf("Clock2 = %sMHz", freq[clock]);
 337
 338         sw = QIXIS_READ(brdcfg[3]);
 339         puts("\nSERDES2 Reference : ");
 340         clock = sw >> 4;
 341         printf("Clock1 = %sMHz ", freq[clock]);
 342         clock = sw & 0x0f;
 343         printf("Clock2 = %sMHz", freq[clock]);
 344
 345         sw = QIXIS_READ(brdcfg[12]);
 346         puts("\nSERDES3 Reference : ");
 347         clock = sw >> 4;
 348         printf("Clock1 = %sMHz Clock2 = %sMHz\n", freq[clock], freq[clock]);
 349 #else
 350         printf("FPGA: v%d.%d\n", QIXIS_READ(scver), QIXIS_READ(tagdata));
 351
 352         puts("SERDES1 Reference: Clock1 = 161.13MHz Clock2 = 161.13MHz\n");
 353         puts("SERDES2 Reference: Clock1 = 100MHz Clock2 = 100MHz\n");
 354         puts("SERDES3 Reference: Clock1 = 100MHz Clock2 = 100MHz\n");
 355 #endif
 356         return 0;
 357 }
 358
 359 #ifdef CONFIG_TARGET_LX2160AQDS
 360 /*
 361  * implementation of CONFIG_ESDHC_DETECT_QUIRK Macro.
 362  */
 363 u8 qixis_esdhc_detect_quirk(void)
 364 {
 365         /* for LX2160AQDS res1[1] @ offset 0x1A is SDHC1 Control/Status (SDHC1)
 366          * SDHC1 Card ID:
 367          * Specifies the type of card installed in the SDHC1 adapter slot.
 368          * 000= (reserved)
 369          * 001= eMMC V4.5 adapter is installed.
 370          * 010= SD/MMC 3.3V adapter is installed.
 371          * 011= eMMC V4.4 adapter is installed.
 372          * 100= eMMC V5.0 adapter is installed.
 373          * 101= MMC card/Legacy (3.3V) adapter is installed.
 374          * 110= SDCard V2/V3 adapter installed.
 375          * 111= no adapter is installed.
 376          */
 377         return ((QIXIS_READ(res1[1]) & QIXIS_SDID_MASK) !=
 378                  QIXIS_ESDHC_NO_ADAPTER);
 379 }
 380
 381 int config_board_mux(void)
 382 {
 383         u8 reg11, reg5, reg13;
 384         struct ccsr_gur __iomem *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR);
 385         u32 sdhc1_base_pmux;
 386         u32 sdhc2_base_pmux;
 387         u32 iic5_pmux;
 388
 389         /* Routes {I2C2_SCL, I2C2_SDA} to SDHC1 as {SDHC1_CD_B, SDHC1_WP}.
 390          * Routes {I2C3_SCL, I2C3_SDA} to CAN transceiver as {CAN1_TX,CAN1_RX}.
 391          * Routes {I2C4_SCL, I2C4_SDA} to CAN transceiver as {CAN2_TX,CAN2_RX}.
 392          * Qixis and remote systems are isolated from the I2C1 bus.
 393          * Processor connections are still available.
 394          * SPI2 CS2_B controls EN25S64 SPI memory device.
 395          * SPI3 CS2_B controls EN25S64 SPI memory device.
 396          * EC2 connects to PHY #2 using RGMII protocol.
 397          * CLK_OUT connects to FPGA for clock measurement.
 398          */
 399
 400         reg5 = QIXIS_READ(brdcfg[5]);
 401         reg5 = CFG_MUX_I2C_SDHC(reg5, 0x40);
 402         QIXIS_WRITE(brdcfg[5], reg5);
 403
 404         /* Check RCW field sdhc1_base_pmux
 405          * esdhc0 : sdhc1_base_pmux = 0
 406          * dspi0  : sdhc1_base_pmux = 2
 407          */
 408         sdhc1_base_pmux = gur_in32(&gur->rcwsr[FSL_CHASSIS3_RCWSR12_REGSR - 1])
 409                 & FSL_CHASSIS3_SDHC1_BASE_PMUX_MASK;
 410         sdhc1_base_pmux >>= FSL_CHASSIS3_SDHC1_BASE_PMUX_SHIFT;
 411
 412         if (sdhc1_base_pmux == SDHC1_BASE_PMUX_DSPI) {
 413                 reg11 = QIXIS_READ(brdcfg[11]);
 414                 reg11 = SET_CFG_MUX1_SDHC1_DSPI(reg11, 0x40);
 415                 QIXIS_WRITE(brdcfg[11], reg11);
 416         } else {
 417                 /* - Routes {SDHC1_CMD, SDHC1_CLK } to SDHC1 adapter slot.
 418                  *          {SDHC1_DAT3, SDHC1_DAT2} to SDHC1 adapter slot.
 419                  *          {SDHC1_DAT1, SDHC1_DAT0} to SDHC1 adapter slot.
 420                  */
 421                 reg11 = QIXIS_READ(brdcfg[11]);
 422                 reg11 = SET_CFG_MUX1_SDHC1_SDHC(reg11);
 423                 QIXIS_WRITE(brdcfg[11], reg11);
 424         }
 425
 426         /* Check RCW field sdhc2_base_pmux
 427          * esdhc1 : sdhc2_base_pmux = 0 (default)
 428          * dspi1  : sdhc2_base_pmux = 2
 429          */
 430         sdhc2_base_pmux = gur_in32(&gur->rcwsr[FSL_CHASSIS3_RCWSR13_REGSR - 1])
 431                 & FSL_CHASSIS3_SDHC2_BASE_PMUX_MASK;
 432         sdhc2_base_pmux >>= FSL_CHASSIS3_SDHC2_BASE_PMUX_SHIFT;
 433
 434         if (sdhc2_base_pmux == SDHC2_BASE_PMUX_DSPI) {
 435                 reg13 = QIXIS_READ(brdcfg[13]);
 436                 reg13 = SET_CFG_MUX_SDHC2_DSPI(reg13, 0x01);
 437                 QIXIS_WRITE(brdcfg[13], reg13);
 438         } else {
 439                 reg13 = QIXIS_READ(brdcfg[13]);
 440                 reg13 = SET_CFG_MUX_SDHC2_DSPI(reg13, 0x00);
 441                 QIXIS_WRITE(brdcfg[13], reg13);
 442         }
 443
 444         /* Check RCW field IIC5 to enable dspi2 DT nodei
 445          * dspi2: IIC5 = 3
 446          */
 447         iic5_pmux = gur_in32(&gur->rcwsr[FSL_CHASSIS3_RCWSR12_REGSR - 1])
 448                 & FSL_CHASSIS3_IIC5_PMUX_MASK;
 449         iic5_pmux >>= FSL_CHASSIS3_IIC5_PMUX_SHIFT;
 450
 451         if (iic5_pmux == IIC5_PMUX_SPI3) {
 452                 /* - Routes {SDHC1_DAT4} to SPI3 devices as {SPI3_M_CS0_B}. */
 453                 reg11 = QIXIS_READ(brdcfg[11]);
 454                 reg11 = SET_CFG_MUX2_SDHC1_SPI(reg11, 0x10);
 455                 QIXIS_WRITE(brdcfg[11], reg11);
 456
 457                 /* - Routes {SDHC1_DAT5, SDHC1_DAT6} nowhere.
 458                  * {SDHC1_DAT7, SDHC1_DS } to {nothing, SPI3_M0_CLK }.
 459                  * {I2C5_SCL, I2C5_SDA } to {SPI3_M0_MOSI, SPI3_M0_MISO}.
 460                  */
 461                 reg11 = QIXIS_READ(brdcfg[11]);
 462                 reg11 = SET_CFG_MUX3_SDHC1_SPI(reg11, 0x01);
 463                 QIXIS_WRITE(brdcfg[11], reg11);
 464         } else {
 465                 /*  Routes {SDHC1_DAT4} to SDHC1 adapter slot */
 466                 reg11 = QIXIS_READ(brdcfg[11]);
 467                 reg11 = SET_CFG_MUX2_SDHC1_SPI(reg11, 0x00);
 468                 QIXIS_WRITE(brdcfg[11], reg11);
 469
 470                 /* - Routes {SDHC1_DAT5, SDHC1_DAT6} to SDHC1 adapter slot.
 471                  * {SDHC1_DAT7, SDHC1_DS } to SDHC1 adapter slot.
 472                  * {I2C5_SCL, I2C5_SDA } to SDHC1 adapter slot.
 473                  */
 474                 reg11 = QIXIS_READ(brdcfg[11]);
 475                 reg11 = SET_CFG_MUX3_SDHC1_SPI(reg11, 0x00);
 476                 QIXIS_WRITE(brdcfg[11], reg11);
 477         }
 478
 479         return 0;
 480 }
 481 #elif defined(CONFIG_TARGET_LX2160ARDB)
 482 int config_board_mux(void)
 483 {
 484         u8 brdcfg;
 485
 486         brdcfg = QIXIS_READ(brdcfg[4]);
 487         /* The BRDCFG4 register controls general board configuration.
 488          *|-------------------------------------------|
 489          *|Field  | Function                          |
 490          *|-------------------------------------------|
 491          *|5      | CAN I/O Enable (net CFG_CAN_EN_B):|
 492          *|CAN_EN | 0= CAN transceivers are disabled. |
 493          *|       | 1= CAN transceivers are enabled.  |
 494          *|-------------------------------------------|
 495          */
 496         brdcfg |= BIT_MASK(5);
 497         QIXIS_WRITE(brdcfg[4], brdcfg);
 498
 499         return 0;
 500 }
 501 #else
 502 int config_board_mux(void)
 503 {
 504         return 0;
 505 }
 506 #endif
 507
 508 unsigned long get_board_sys_clk(void)
 509 {
 510 #ifdef CONFIG_TARGET_LX2160AQDS
 511         u8 sysclk_conf = QIXIS_READ(brdcfg[1]);
 512
 513         switch (sysclk_conf & 0x03) {
 514         case QIXIS_SYSCLK_100:
 515                 return 100000000;
 516         case QIXIS_SYSCLK_125:
 517                 return 125000000;
 518         case QIXIS_SYSCLK_133:
 519                 return 133333333;
 520         }
 521         return 100000000;
 522 #else
 523         return 100000000;
 524 #endif
 525 }
 526
 527 unsigned long get_board_ddr_clk(void)
 528 {
 529 #ifdef CONFIG_TARGET_LX2160AQDS
 530         u8 ddrclk_conf = QIXIS_READ(brdcfg[1]);
 531
 532         switch ((ddrclk_conf & 0x30) >> 4) {
 533         case QIXIS_DDRCLK_100:
 534                 return 100000000;
 535         case QIXIS_DDRCLK_125:
 536                 return 125000000;
 537         case QIXIS_DDRCLK_133:
 538                 return 133333333;
 539         }
 540         return 100000000;
 541 #else
 542         return 100000000;
 543 #endif
 544 }
 545
 546 int board_init(void)
 547 {
 548 #if defined(CONFIG_FSL_MC_ENET) && defined(CONFIG_TARGET_LX2160ARDB)
 549         u32 __iomem *irq_ccsr = (u32 __iomem *)ISC_BASE;
 550 #endif
 551 #ifdef CONFIG_ENV_IS_NOWHERE
 552         gd->env_addr = (ulong)&default_environment[0];
 553 #endif
 554
 555         select_i2c_ch_pca9547(I2C_MUX_CH_DEFAULT);
 556
 557 #if defined(CONFIG_FSL_MC_ENET) && defined(CONFIG_TARGET_LX2160ARDB)
 558         /* invert AQR107 IRQ pins polarity */
 559         out_le32(irq_ccsr + IRQCR_OFFSET / 4, AQR107_IRQ_MASK);
 560 #endif
 561
 562 #ifdef CONFIG_FSL_CAAM
 563         sec_init();
 564 #endif
 565
 566         return 0;
 567 }
 568
 569 void detail_board_ddr_info(void)
 570 {
 571         int i;
 572         u64 ddr_size = 0;
 573
 574         puts("\nDDR    ");
 575         for (i = 0; i < CONFIG_NR_DRAM_BANKS; i++)
 576                 ddr_size += gd->bd->bi_dram[i].size;
 577         print_size(ddr_size, "");
 578         print_ddr_info(0);
 579 }
 580
 581 #if defined(CONFIG_ARCH_MISC_INIT)
 582 int arch_misc_init(void)
 583 {
 584         config_board_mux();
 585
 586         return 0;
 587 }
 588 #endif
 589
 590 #ifdef CONFIG_FSL_MC_ENET
 591 extern int fdt_fixup_board_phy(void *fdt);
 592
 593 void fdt_fixup_board_enet(void *fdt)
 594 {
 595         int offset;
 596
 597         offset = fdt_path_offset(fdt, "/soc/fsl-mc");
 598
 599         if (offset < 0)
 600                 offset = fdt_path_offset(fdt, "/fsl-mc");
 601
 602         if (offset < 0) {
 603                 printf("%s: fsl-mc node not found in device tree (error %d)\n",
 604                        __func__, offset);
 605                 return;
 606         }
 607
 608         if (get_mc_boot_status() == 0 &&
 609             (is_lazy_dpl_addr_valid() || get_dpl_apply_status() == 0)) {
 610                 fdt_status_okay(fdt, offset);
 611                 fdt_fixup_board_phy(fdt);
 612         } else {
 613                 fdt_status_fail(fdt, offset);
 614         }
 615 }
 616
 617 void board_quiesce_devices(void)
 618 {
 619         fsl_mc_ldpaa_exit(gd->bd);
 620 }
 621 #endif
 622
 623 #ifdef CONFIG_OF_BOARD_SETUP
 624
 625 int ft_board_setup(void *blob, bd_t *bd)
 626 {
 627         int i;
 628         u16 mc_memory_bank = 0;
 629
 630         u64 *base;
 631         u64 *size;
 632         u64 mc_memory_base = 0;
 633         u64 mc_memory_size = 0;
 634         u16 total_memory_banks;
 635
 636         ft_cpu_setup(blob, bd);
 637
 638         fdt_fixup_mc_ddr(&mc_memory_base, &mc_memory_size);
 639
 640         if (mc_memory_base != 0)
 641                 mc_memory_bank++;
 642
 643         total_memory_banks = CONFIG_NR_DRAM_BANKS + mc_memory_bank;
 644
 645         base = calloc(total_memory_banks, sizeof(u64));
 646         size = calloc(total_memory_banks, sizeof(u64));
 647
 648         /* fixup DT for the three GPP DDR banks */
 649         for (i = 0; i < CONFIG_NR_DRAM_BANKS; i++) {
 650                 base[i] = gd->bd->bi_dram[i].start;
 651                 size[i] = gd->bd->bi_dram[i].size;
 652         }
 653
 654 #ifdef CONFIG_RESV_RAM
 655         /* reduce size if reserved memory is within this bank */
 656         if (gd->arch.resv_ram >= base[0] &&
 657             gd->arch.resv_ram < base[0] + size[0])
 658                 size[0] = gd->arch.resv_ram - base[0];
 659         else if (gd->arch.resv_ram >= base[1] &&
 660                  gd->arch.resv_ram < base[1] + size[1])
 661                 size[1] = gd->arch.resv_ram - base[1];
 662         else if (gd->arch.resv_ram >= base[2] &&
 663                  gd->arch.resv_ram < base[2] + size[2])
 664                 size[2] = gd->arch.resv_ram - base[2];
 665 #endif
 666
 667         if (mc_memory_base != 0) {
 668                 for (i = 0; i <= total_memory_banks; i++) {
 669                         if (base[i] == 0 && size[i] == 0) {
 670                                 base[i] = mc_memory_base;
 671                                 size[i] = mc_memory_size;
 672                                 break;
 673                         }
 674                 }
 675         }
 676
 677         fdt_fixup_memory_banks(blob, base, size, total_memory_banks);
 678
 679 #ifdef CONFIG_USB
 680         fsl_fdt_fixup_dr_usb(blob, bd);
 681 #endif
 682
 683 #ifdef CONFIG_FSL_MC_ENET
 684         fdt_fsl_mc_fixup_iommu_map_entry(blob);
 685         fdt_fixup_board_enet(blob);
 686 #endif
 687
 688         return 0;
 689 }
 690 #endif
 691
 692 void qixis_dump_switch(void)
 693 {
 694         int i, nr_of_cfgsw;
 695
 696         QIXIS_WRITE(cms[0], 0x00);
 697         nr_of_cfgsw = QIXIS_READ(cms[1]);
 698
 699         puts("DIP switch settings dump:\n");
 700         for (i = 1; i <= nr_of_cfgsw; i++) {
 701                 QIXIS_WRITE(cms[0], i);
 702                 printf("SW%d = (0x%02x)\n", i, QIXIS_READ(cms[1]));
 703         }
 704 }