board/freescale/lx2160a/lx2160a.c

   1 // SPDX-License-Identifier: GPL-2.0+
   2 /*
   3  * Copyright 2018-2019 NXP
   4  */
   5
   6 #include <common.h>
   7 #include <dm.h>
   8 #include <dm/platform_data/serial_pl01x.h>
   9 #include <i2c.h>
  10 #include <malloc.h>
  11 #include <errno.h>
  12 #include <netdev.h>
  13 #include <fsl_ddr.h>
  14 #include <fsl_sec.h>
  15 #include <asm/io.h>
  16 #include <fdt_support.h>
  17 #include <linux/libfdt.h>
  18 #include <fsl-mc/fsl_mc.h>
  19 #include <env_internal.h>
  20 #include <efi_loader.h>
  21 #include <asm/arch/mmu.h>
  22 #include <hwconfig.h>
  23 #include <asm/arch/clock.h>
  24 #include <asm/arch/config.h>
  25 #include <asm/arch/fsl_serdes.h>
  26 #include <asm/arch/soc.h>
  27 #include "../common/qixis.h"
  28 #include "../common/vid.h"
  29 #include <fsl_immap.h>
  30 #include <asm/arch-fsl-layerscape/fsl_icid.h>
  31
  32 #ifdef CONFIG_EMC2305
  33 #include "../common/emc2305.h"
  34 #endif
  35
  36 #ifdef CONFIG_TARGET_LX2160AQDS
  37 #define CFG_MUX_I2C_SDHC(reg, value)            ((reg & 0x3f) | value)
  38 #define SET_CFG_MUX1_SDHC1_SDHC(reg)            (reg & 0x3f)
  39 #define SET_CFG_MUX2_SDHC1_SPI(reg, value)      ((reg & 0xcf) | value)
  40 #define SET_CFG_MUX3_SDHC1_SPI(reg, value)      ((reg & 0xf8) | value)
  41 #define SET_CFG_MUX_SDHC2_DSPI(reg, value)      ((reg & 0xf8) | value)
  42 #define SET_CFG_MUX1_SDHC1_DSPI(reg, value)     ((reg & 0x3f) | value)
  43 #define SDHC1_BASE_PMUX_DSPI                    2
  44 #define SDHC2_BASE_PMUX_DSPI                    2
  45 #define IIC5_PMUX_SPI3                          3
  46 #endif /* CONFIG_TARGET_LX2160AQDS */
  47
  48 DECLARE_GLOBAL_DATA_PTR;
  49
  50 static struct pl01x_serial_platdata serial0 = {
  51 #if CONFIG_CONS_INDEX == 0
  52         .base = CONFIG_SYS_SERIAL0,
  53 #elif CONFIG_CONS_INDEX == 1
  54         .base = CONFIG_SYS_SERIAL1,
  55 #else
  56 #error "Unsupported console index value."
  57 #endif
  58         .type = TYPE_PL011,
  59 };
  60
  61 U_BOOT_DEVICE(nxp_serial0) = {
  62         .name = "serial_pl01x",
  63         .platdata = &serial0,
  64 };
  65
  66 static struct pl01x_serial_platdata serial1 = {
  67         .base = CONFIG_SYS_SERIAL1,
  68         .type = TYPE_PL011,
  69 };
  70
  71 U_BOOT_DEVICE(nxp_serial1) = {
  72         .name = "serial_pl01x",
  73         .platdata = &serial1,
  74 };
  75
  76 int select_i2c_ch_pca9547(u8 ch)
  77 {
  78         int ret;
  79
  80 #ifndef CONFIG_DM_I2C
  81         ret = i2c_write(I2C_MUX_PCA_ADDR_PRI, 0, 1, &ch, 1);
  82 #else
  83         struct udevice *dev;
  84
  85         ret = i2c_get_chip_for_busnum(0, I2C_MUX_PCA_ADDR_PRI, 1, &dev);
  86         if (!ret)
  87                 ret = dm_i2c_write(dev, 0, &ch, 1);
  88 #endif
  89         if (ret) {
  90                 puts("PCA: failed to select proper channel\n");
  91                 return ret;
  92         }
  93
  94         return 0;
  95 }
  96
  97 static void uart_get_clock(void)
  98 {
  99         serial0.clock = get_serial_clock();
 100         serial1.clock = get_serial_clock();
 101 }
 102
 103 int board_early_init_f(void)
 104 {
 105 #ifdef CONFIG_SYS_I2C_EARLY_INIT
 106         i2c_early_init_f();
 107 #endif
 108         /* get required clock for UART IP */
 109         uart_get_clock();
 110
 111 #ifdef CONFIG_EMC2305
 112         select_i2c_ch_pca9547(I2C_MUX_CH_EMC2305);
 113         emc2305_init();
 114         set_fan_speed(I2C_EMC2305_PWM);
 115         select_i2c_ch_pca9547(I2C_MUX_CH_DEFAULT);
 116 #endif
 117
 118         fsl_lsch3_early_init_f();
 119         return 0;
 120 }
 121
 122 #ifdef CONFIG_OF_BOARD_FIXUP
 123 int board_fix_fdt(void *fdt)
 124 {
 125         char *reg_names, *reg_name;
 126         int names_len, old_name_len, new_name_len, remaining_names_len;
 127         struct str_map {
 128                 char *old_str;
 129                 char *new_str;
 130         } reg_names_map[] = {
 131                 { "ccsr", "dbi" },
 132                 { "pf_ctrl", "ctrl" }
 133         };
 134         int off = -1, i;
 135
 136         if (IS_SVR_REV(get_svr(), 1, 0))
 137                 return 0;
 138
 139         off = fdt_node_offset_by_compatible(fdt, -1, "fsl,lx2160a-pcie");
 140         while (off != -FDT_ERR_NOTFOUND) {
 141                 fdt_setprop(fdt, off, "compatible", "fsl,ls-pcie",
 142                             strlen("fsl,ls-pcie") + 1);
 143
 144                 reg_names = (char *)fdt_getprop(fdt, off, "reg-names",
 145                                                 &names_len);
 146                 if (!reg_names)
 147                         continue;
 148
 149                 reg_name = reg_names;
 150                 remaining_names_len = names_len - (reg_name - reg_names);
 151                 for (i = 0; (i < ARRAY_SIZE(reg_names_map)) && names_len; i++) {
 152                         old_name_len = strlen(reg_names_map[i].old_str);
 153                         new_name_len = strlen(reg_names_map[i].new_str);
 154                         if (memcmp(reg_name, reg_names_map[i].old_str,
 155                                    old_name_len) == 0) {
 156                                 /* first only leave required bytes for new_str
 157                                  * and copy rest of the string after it
 158                                  */
 159                                 memcpy(reg_name + new_name_len,
 160                                        reg_name + old_name_len,
 161                                        remaining_names_len - old_name_len);
 162                                 /* Now copy new_str */
 163                                 memcpy(reg_name, reg_names_map[i].new_str,
 164                                        new_name_len);
 165                                 names_len -= old_name_len;
 166                                 names_len += new_name_len;
 167                         }
 168
 169                         reg_name = memchr(reg_name, '\0', remaining_names_len);
 170                         if (!reg_name)
 171                                 break;
 172
 173                         reg_name += 1;
 174
 175                         remaining_names_len = names_len -
 176                                               (reg_name - reg_names);
 177                 }
 178
 179                 fdt_setprop(fdt, off, "reg-names", reg_names, names_len);
 180                 off = fdt_node_offset_by_compatible(fdt, off,
 181                                                     "fsl,lx2160a-pcie");
 182         }
 183
 184         return 0;
 185 }
 186 #endif
 187
 188 #if defined(CONFIG_TARGET_LX2160AQDS)
 189 void esdhc_dspi_status_fixup(void *blob)
 190 {
 191         const char esdhc0_path[] = "/soc/esdhc@2140000";
 192         const char esdhc1_path[] = "/soc/esdhc@2150000";
 193         const char dspi0_path[] = "/soc/dspi@2100000";
 194         const char dspi1_path[] = "/soc/dspi@2110000";
 195         const char dspi2_path[] = "/soc/dspi@2120000";
 196
 197         struct ccsr_gur __iomem *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR);
 198         u32 sdhc1_base_pmux;
 199         u32 sdhc2_base_pmux;
 200         u32 iic5_pmux;
 201
 202         /* Check RCW field sdhc1_base_pmux to enable/disable
 203          * esdhc0/dspi0 DT node
 204          */
 205         sdhc1_base_pmux = gur_in32(&gur->rcwsr[FSL_CHASSIS3_RCWSR12_REGSR - 1])
 206                 & FSL_CHASSIS3_SDHC1_BASE_PMUX_MASK;
 207         sdhc1_base_pmux >>= FSL_CHASSIS3_SDHC1_BASE_PMUX_SHIFT;
 208
 209         if (sdhc1_base_pmux == SDHC1_BASE_PMUX_DSPI) {
 210                 do_fixup_by_path(blob, dspi0_path, "status", "okay",
 211                                  sizeof("okay"), 1);
 212                 do_fixup_by_path(blob, esdhc0_path, "status", "disabled",
 213                                  sizeof("disabled"), 1);
 214         } else {
 215                 do_fixup_by_path(blob, esdhc0_path, "status", "okay",
 216                                  sizeof("okay"), 1);
 217                 do_fixup_by_path(blob, dspi0_path, "status", "disabled",
 218                                  sizeof("disabled"), 1);
 219         }
 220
 221         /* Check RCW field sdhc2_base_pmux to enable/disable
 222          * esdhc1/dspi1 DT node
 223          */
 224         sdhc2_base_pmux = gur_in32(&gur->rcwsr[FSL_CHASSIS3_RCWSR13_REGSR - 1])
 225                 & FSL_CHASSIS3_SDHC2_BASE_PMUX_MASK;
 226         sdhc2_base_pmux >>= FSL_CHASSIS3_SDHC2_BASE_PMUX_SHIFT;
 227
 228         if (sdhc2_base_pmux == SDHC2_BASE_PMUX_DSPI) {
 229                 do_fixup_by_path(blob, dspi1_path, "status", "okay",
 230                                  sizeof("okay"), 1);
 231                 do_fixup_by_path(blob, esdhc1_path, "status", "disabled",
 232                                  sizeof("disabled"), 1);
 233         } else {
 234                 do_fixup_by_path(blob, esdhc1_path, "status", "okay",
 235                                  sizeof("okay"), 1);
 236                 do_fixup_by_path(blob, dspi1_path, "status", "disabled",
 237                                  sizeof("disabled"), 1);
 238         }
 239
 240         /* Check RCW field IIC5 to enable dspi2 DT node */
 241         iic5_pmux = gur_in32(&gur->rcwsr[FSL_CHASSIS3_RCWSR12_REGSR - 1])
 242                 & FSL_CHASSIS3_IIC5_PMUX_MASK;
 243         iic5_pmux >>= FSL_CHASSIS3_IIC5_PMUX_SHIFT;
 244
 245         if (iic5_pmux == IIC5_PMUX_SPI3) {
 246                 do_fixup_by_path(blob, dspi2_path, "status", "okay",
 247                                  sizeof("okay"), 1);
 248         }
 249 }
 250 #endif
 251
 252 int esdhc_status_fixup(void *blob, const char *compat)
 253 {
 254 #if defined(CONFIG_TARGET_LX2160AQDS)
 255         /* Enable esdhc and dspi DT nodes based on RCW fields */
 256         esdhc_dspi_status_fixup(blob);
 257 #else
 258         /* Enable both esdhc DT nodes for LX2160ARDB */
 259         do_fixup_by_compat(blob, compat, "status", "okay",
 260                            sizeof("okay"), 1);
 261 #endif
 262         return 0;
 263 }
 264
 265 #if defined(CONFIG_VID)
 266 int i2c_multiplexer_select_vid_channel(u8 channel)
 267 {
 268         return select_i2c_ch_pca9547(channel);
 269 }
 270
 271 int init_func_vid(void)
 272 {
 273         if (adjust_vdd(0) < 0)
 274                 printf("core voltage not adjusted\n");
 275
 276         return 0;
 277 }
 278 #endif
 279
 280 int checkboard(void)
 281 {
 282         enum boot_src src = get_boot_src();
 283         char buf[64];
 284         u8 sw;
 285 #ifdef CONFIG_TARGET_LX2160AQDS
 286         int clock;
 287         static const char *const freq[] = {"100", "125", "156.25",
 288                                            "161.13", "322.26", "", "", "",
 289                                            "", "", "", "", "", "", "",
 290                                            "100 separate SSCG"};
 291 #endif
 292
 293         cpu_name(buf);
 294 #ifdef CONFIG_TARGET_LX2160AQDS
 295         printf("Board: %s-QDS, ", buf);
 296 #else
 297         printf("Board: %s-RDB, ", buf);
 298 #endif
 299
 300         sw = QIXIS_READ(arch);
 301         printf("Board version: %c, boot from ", (sw & 0xf) - 1 + 'A');
 302
 303         if (src == BOOT_SOURCE_SD_MMC) {
 304                 puts("SD\n");
 305         } else {
 306                 sw = QIXIS_READ(brdcfg[0]);
 307                 sw = (sw >> QIXIS_XMAP_SHIFT) & QIXIS_XMAP_MASK;
 308                 switch (sw) {
 309                 case 0:
 310                 case 4:
 311                         puts("FlexSPI DEV#0\n");
 312                         break;
 313                 case 1:
 314                         puts("FlexSPI DEV#1\n");
 315                         break;
 316                 case 2:
 317                 case 3:
 318                         puts("FlexSPI EMU\n");
 319                         break;
 320                 default:
 321                         printf("invalid setting, xmap: %d\n", sw);
 322                         break;
 323                 }
 324         }
 325 #ifdef CONFIG_TARGET_LX2160AQDS
 326         printf("FPGA: v%d (%s), build %d",
 327                (int)QIXIS_READ(scver), qixis_read_tag(buf),
 328                (int)qixis_read_minor());
 329         /* the timestamp string contains "\n" at the end */
 330         printf(" on %s", qixis_read_time(buf));
 331
 332         puts("SERDES1 Reference : ");
 333         sw = QIXIS_READ(brdcfg[2]);
 334         clock = sw >> 4;
 335         printf("Clock1 = %sMHz ", freq[clock]);
 336         clock = sw & 0x0f;
 337         printf("Clock2 = %sMHz", freq[clock]);
 338
 339         sw = QIXIS_READ(brdcfg[3]);
 340         puts("\nSERDES2 Reference : ");
 341         clock = sw >> 4;
 342         printf("Clock1 = %sMHz ", freq[clock]);
 343         clock = sw & 0x0f;
 344         printf("Clock2 = %sMHz", freq[clock]);
 345
 346         sw = QIXIS_READ(brdcfg[12]);
 347         puts("\nSERDES3 Reference : ");
 348         clock = sw >> 4;
 349         printf("Clock1 = %sMHz Clock2 = %sMHz\n", freq[clock], freq[clock]);
 350 #else
 351         printf("FPGA: v%d.%d\n", QIXIS_READ(scver), QIXIS_READ(tagdata));
 352
 353         puts("SERDES1 Reference: Clock1 = 161.13MHz Clock2 = 161.13MHz\n");
 354         puts("SERDES2 Reference: Clock1 = 100MHz Clock2 = 100MHz\n");
 355         puts("SERDES3 Reference: Clock1 = 100MHz Clock2 = 100MHz\n");
 356 #endif
 357         return 0;
 358 }
 359
 360 #ifdef CONFIG_TARGET_LX2160AQDS
 361 /*
 362  * implementation of CONFIG_ESDHC_DETECT_QUIRK Macro.
 363  */
 364 u8 qixis_esdhc_detect_quirk(void)
 365 {
 366         /* for LX2160AQDS res1[1] @ offset 0x1A is SDHC1 Control/Status (SDHC1)
 367          * SDHC1 Card ID:
 368          * Specifies the type of card installed in the SDHC1 adapter slot.
 369          * 000= (reserved)
 370          * 001= eMMC V4.5 adapter is installed.
 371          * 010= SD/MMC 3.3V adapter is installed.
 372          * 011= eMMC V4.4 adapter is installed.
 373          * 100= eMMC V5.0 adapter is installed.
 374          * 101= MMC card/Legacy (3.3V) adapter is installed.
 375          * 110= SDCard V2/V3 adapter installed.
 376          * 111= no adapter is installed.
 377          */
 378         return ((QIXIS_READ(res1[1]) & QIXIS_SDID_MASK) !=
 379                  QIXIS_ESDHC_NO_ADAPTER);
 380 }
 381
 382 int config_board_mux(void)
 383 {
 384         u8 reg11, reg5, reg13;
 385         struct ccsr_gur __iomem *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR);
 386         u32 sdhc1_base_pmux;
 387         u32 sdhc2_base_pmux;
 388         u32 iic5_pmux;
 389
 390         /* Routes {I2C2_SCL, I2C2_SDA} to SDHC1 as {SDHC1_CD_B, SDHC1_WP}.
 391          * Routes {I2C3_SCL, I2C3_SDA} to CAN transceiver as {CAN1_TX,CAN1_RX}.
 392          * Routes {I2C4_SCL, I2C4_SDA} to CAN transceiver as {CAN2_TX,CAN2_RX}.
 393          * Qixis and remote systems are isolated from the I2C1 bus.
 394          * Processor connections are still available.
 395          * SPI2 CS2_B controls EN25S64 SPI memory device.
 396          * SPI3 CS2_B controls EN25S64 SPI memory device.
 397          * EC2 connects to PHY #2 using RGMII protocol.
 398          * CLK_OUT connects to FPGA for clock measurement.
 399          */
 400
 401         reg5 = QIXIS_READ(brdcfg[5]);
 402         reg5 = CFG_MUX_I2C_SDHC(reg5, 0x40);
 403         QIXIS_WRITE(brdcfg[5], reg5);
 404
 405         /* Check RCW field sdhc1_base_pmux
 406          * esdhc0 : sdhc1_base_pmux = 0
 407          * dspi0  : sdhc1_base_pmux = 2
 408          */
 409         sdhc1_base_pmux = gur_in32(&gur->rcwsr[FSL_CHASSIS3_RCWSR12_REGSR - 1])
 410                 & FSL_CHASSIS3_SDHC1_BASE_PMUX_MASK;
 411         sdhc1_base_pmux >>= FSL_CHASSIS3_SDHC1_BASE_PMUX_SHIFT;
 412
 413         if (sdhc1_base_pmux == SDHC1_BASE_PMUX_DSPI) {
 414                 reg11 = QIXIS_READ(brdcfg[11]);
 415                 reg11 = SET_CFG_MUX1_SDHC1_DSPI(reg11, 0x40);
 416                 QIXIS_WRITE(brdcfg[11], reg11);
 417         } else {
 418                 /* - Routes {SDHC1_CMD, SDHC1_CLK } to SDHC1 adapter slot.
 419                  *          {SDHC1_DAT3, SDHC1_DAT2} to SDHC1 adapter slot.
 420                  *          {SDHC1_DAT1, SDHC1_DAT0} to SDHC1 adapter slot.
 421                  */
 422                 reg11 = QIXIS_READ(brdcfg[11]);
 423                 reg11 = SET_CFG_MUX1_SDHC1_SDHC(reg11);
 424                 QIXIS_WRITE(brdcfg[11], reg11);
 425         }
 426
 427         /* Check RCW field sdhc2_base_pmux
 428          * esdhc1 : sdhc2_base_pmux = 0 (default)
 429          * dspi1  : sdhc2_base_pmux = 2
 430          */
 431         sdhc2_base_pmux = gur_in32(&gur->rcwsr[FSL_CHASSIS3_RCWSR13_REGSR - 1])
 432                 & FSL_CHASSIS3_SDHC2_BASE_PMUX_MASK;
 433         sdhc2_base_pmux >>= FSL_CHASSIS3_SDHC2_BASE_PMUX_SHIFT;
 434
 435         if (sdhc2_base_pmux == SDHC2_BASE_PMUX_DSPI) {
 436                 reg13 = QIXIS_READ(brdcfg[13]);
 437                 reg13 = SET_CFG_MUX_SDHC2_DSPI(reg13, 0x01);
 438                 QIXIS_WRITE(brdcfg[13], reg13);
 439         } else {
 440                 reg13 = QIXIS_READ(brdcfg[13]);
 441                 reg13 = SET_CFG_MUX_SDHC2_DSPI(reg13, 0x00);
 442                 QIXIS_WRITE(brdcfg[13], reg13);
 443         }
 444
 445         /* Check RCW field IIC5 to enable dspi2 DT nodei
 446          * dspi2: IIC5 = 3
 447          */
 448         iic5_pmux = gur_in32(&gur->rcwsr[FSL_CHASSIS3_RCWSR12_REGSR - 1])
 449                 & FSL_CHASSIS3_IIC5_PMUX_MASK;
 450         iic5_pmux >>= FSL_CHASSIS3_IIC5_PMUX_SHIFT;
 451
 452         if (iic5_pmux == IIC5_PMUX_SPI3) {
 453                 /* - Routes {SDHC1_DAT4} to SPI3 devices as {SPI3_M_CS0_B}. */
 454                 reg11 = QIXIS_READ(brdcfg[11]);
 455                 reg11 = SET_CFG_MUX2_SDHC1_SPI(reg11, 0x10);
 456                 QIXIS_WRITE(brdcfg[11], reg11);
 457
 458                 /* - Routes {SDHC1_DAT5, SDHC1_DAT6} nowhere.
 459                  * {SDHC1_DAT7, SDHC1_DS } to {nothing, SPI3_M0_CLK }.
 460                  * {I2C5_SCL, I2C5_SDA } to {SPI3_M0_MOSI, SPI3_M0_MISO}.
 461                  */
 462                 reg11 = QIXIS_READ(brdcfg[11]);
 463                 reg11 = SET_CFG_MUX3_SDHC1_SPI(reg11, 0x01);
 464                 QIXIS_WRITE(brdcfg[11], reg11);
 465         } else {
 466                 /*  Routes {SDHC1_DAT4} to SDHC1 adapter slot */
 467                 reg11 = QIXIS_READ(brdcfg[11]);
 468                 reg11 = SET_CFG_MUX2_SDHC1_SPI(reg11, 0x00);
 469                 QIXIS_WRITE(brdcfg[11], reg11);
 470
 471                 /* - Routes {SDHC1_DAT5, SDHC1_DAT6} to SDHC1 adapter slot.
 472                  * {SDHC1_DAT7, SDHC1_DS } to SDHC1 adapter slot.
 473                  * {I2C5_SCL, I2C5_SDA } to SDHC1 adapter slot.
 474                  */
 475                 reg11 = QIXIS_READ(brdcfg[11]);
 476                 reg11 = SET_CFG_MUX3_SDHC1_SPI(reg11, 0x00);
 477                 QIXIS_WRITE(brdcfg[11], reg11);
 478         }
 479
 480         return 0;
 481 }
 482 #elif defined(CONFIG_TARGET_LX2160ARDB)
 483 int config_board_mux(void)
 484 {
 485         u8 brdcfg;
 486
 487         brdcfg = QIXIS_READ(brdcfg[4]);
 488         /* The BRDCFG4 register controls general board configuration.
 489          *|-------------------------------------------|
 490          *|Field  | Function                          |
 491          *|-------------------------------------------|
 492          *|5      | CAN I/O Enable (net CFG_CAN_EN_B):|
 493          *|CAN_EN | 0= CAN transceivers are disabled. |
 494          *|       | 1= CAN transceivers are enabled.  |
 495          *|-------------------------------------------|
 496          */
 497         brdcfg |= BIT_MASK(5);
 498         QIXIS_WRITE(brdcfg[4], brdcfg);
 499
 500         return 0;
 501 }
 502 #else
 503 int config_board_mux(void)
 504 {
 505         return 0;
 506 }
 507 #endif
 508
 509 unsigned long get_board_sys_clk(void)
 510 {
 511 #ifdef CONFIG_TARGET_LX2160AQDS
 512         u8 sysclk_conf = QIXIS_READ(brdcfg[1]);
 513
 514         switch (sysclk_conf & 0x03) {
 515         case QIXIS_SYSCLK_100:
 516                 return 100000000;
 517         case QIXIS_SYSCLK_125:
 518                 return 125000000;
 519         case QIXIS_SYSCLK_133:
 520                 return 133333333;
 521         }
 522         return 100000000;
 523 #else
 524         return 100000000;
 525 #endif
 526 }
 527
 528 unsigned long get_board_ddr_clk(void)
 529 {
 530 #ifdef CONFIG_TARGET_LX2160AQDS
 531         u8 ddrclk_conf = QIXIS_READ(brdcfg[1]);
 532
 533         switch ((ddrclk_conf & 0x30) >> 4) {
 534         case QIXIS_DDRCLK_100:
 535                 return 100000000;
 536         case QIXIS_DDRCLK_125:
 537                 return 125000000;
 538         case QIXIS_DDRCLK_133:
 539                 return 133333333;
 540         }
 541         return 100000000;
 542 #else
 543         return 100000000;
 544 #endif
 545 }
 546
 547 int board_init(void)
 548 {
 549 #if defined(CONFIG_FSL_MC_ENET) && defined(CONFIG_TARGET_LX2160ARDB)
 550         u32 __iomem *irq_ccsr = (u32 __iomem *)ISC_BASE;
 551 #endif
 552 #ifdef CONFIG_ENV_IS_NOWHERE
 553         gd->env_addr = (ulong)&default_environment[0];
 554 #endif
 555
 556         select_i2c_ch_pca9547(I2C_MUX_CH_DEFAULT);
 557
 558 #if defined(CONFIG_FSL_MC_ENET) && defined(CONFIG_TARGET_LX2160ARDB)
 559         /* invert AQR107 IRQ pins polarity */
 560         out_le32(irq_ccsr + IRQCR_OFFSET / 4, AQR107_IRQ_MASK);
 561 #endif
 562
 563 #ifdef CONFIG_FSL_CAAM
 564         sec_init();
 565 #endif
 566
 567         return 0;
 568 }
 569
 570 void detail_board_ddr_info(void)
 571 {
 572         int i;
 573         u64 ddr_size = 0;
 574
 575         puts("\nDDR    ");
 576         for (i = 0; i < CONFIG_NR_DRAM_BANKS; i++)
 577                 ddr_size += gd->bd->bi_dram[i].size;
 578         print_size(ddr_size, "");
 579         print_ddr_info(0);
 580 }
 581
 582 #if defined(CONFIG_ARCH_MISC_INIT)
 583 int arch_misc_init(void)
 584 {
 585         config_board_mux();
 586
 587         return 0;
 588 }
 589 #endif
 590
 591 #ifdef CONFIG_FSL_MC_ENET
 592 extern int fdt_fixup_board_phy(void *fdt);
 593
 594 void fdt_fixup_board_enet(void *fdt)
 595 {
 596         int offset;
 597
 598         offset = fdt_path_offset(fdt, "/soc/fsl-mc");
 599
 600         if (offset < 0)
 601                 offset = fdt_path_offset(fdt, "/fsl-mc");
 602
 603         if (offset < 0) {
 604                 printf("%s: fsl-mc node not found in device tree (error %d)\n",
 605                        __func__, offset);
 606                 return;
 607         }
 608
 609         if (get_mc_boot_status() == 0 &&
 610             (is_lazy_dpl_addr_valid() || get_dpl_apply_status() == 0)) {
 611                 fdt_status_okay(fdt, offset);
 612                 fdt_fixup_board_phy(fdt);
 613         } else {
 614                 fdt_status_fail(fdt, offset);
 615         }
 616 }
 617
 618 void board_quiesce_devices(void)
 619 {
 620         fsl_mc_ldpaa_exit(gd->bd);
 621 }
 622 #endif
 623
 624 #ifdef CONFIG_OF_BOARD_SETUP
 625
 626 int ft_board_setup(void *blob, bd_t *bd)
 627 {
 628         int i;
 629         u16 mc_memory_bank = 0;
 630
 631         u64 *base;
 632         u64 *size;
 633         u64 mc_memory_base = 0;
 634         u64 mc_memory_size = 0;
 635         u16 total_memory_banks;
 636
 637         ft_cpu_setup(blob, bd);
 638
 639         fdt_fixup_mc_ddr(&mc_memory_base, &mc_memory_size);
 640
 641         if (mc_memory_base != 0)
 642                 mc_memory_bank++;
 643
 644         total_memory_banks = CONFIG_NR_DRAM_BANKS + mc_memory_bank;
 645
 646         base = calloc(total_memory_banks, sizeof(u64));
 647         size = calloc(total_memory_banks, sizeof(u64));
 648
 649         /* fixup DT for the three GPP DDR banks */
 650         for (i = 0; i < CONFIG_NR_DRAM_BANKS; i++) {
 651                 base[i] = gd->bd->bi_dram[i].start;
 652                 size[i] = gd->bd->bi_dram[i].size;
 653         }
 654
 655 #ifdef CONFIG_RESV_RAM
 656         /* reduce size if reserved memory is within this bank */
 657         if (gd->arch.resv_ram >= base[0] &&
 658             gd->arch.resv_ram < base[0] + size[0])
 659                 size[0] = gd->arch.resv_ram - base[0];
 660         else if (gd->arch.resv_ram >= base[1] &&
 661                  gd->arch.resv_ram < base[1] + size[1])
 662                 size[1] = gd->arch.resv_ram - base[1];
 663         else if (gd->arch.resv_ram >= base[2] &&
 664                  gd->arch.resv_ram < base[2] + size[2])
 665                 size[2] = gd->arch.resv_ram - base[2];
 666 #endif
 667
 668         if (mc_memory_base != 0) {
 669                 for (i = 0; i <= total_memory_banks; i++) {
 670                         if (base[i] == 0 && size[i] == 0) {
 671                                 base[i] = mc_memory_base;
 672                                 size[i] = mc_memory_size;
 673                                 break;
 674                         }
 675                 }
 676         }
 677
 678         fdt_fixup_memory_banks(blob, base, size, total_memory_banks);
 679
 680 #ifdef CONFIG_USB
 681         fsl_fdt_fixup_dr_usb(blob, bd);
 682 #endif
 683
 684 #ifdef CONFIG_FSL_MC_ENET
 685         fdt_fsl_mc_fixup_iommu_map_entry(blob);
 686         fdt_fixup_board_enet(blob);
 687 #endif
 688         fdt_fixup_icid(blob);
 689
 690         return 0;
 691 }
 692 #endif
 693
 694 void qixis_dump_switch(void)
 695 {
 696         int i, nr_of_cfgsw;
 697
 698         QIXIS_WRITE(cms[0], 0x00);
 699         nr_of_cfgsw = QIXIS_READ(cms[1]);
 700
 701         puts("DIP switch settings dump:\n");
 702         for (i = 1; i <= nr_of_cfgsw; i++) {
 703                 QIXIS_WRITE(cms[0], i);
 704                 printf("SW%d = (0x%02x)\n", i, QIXIS_READ(cms[1]));
 705         }
 706 }