board/freescale/lx2160a/lx2160a.c

   1 // SPDX-License-Identifier: GPL-2.0+
   2 /*
   3  * Copyright 2018-2021 NXP
   4  */
   5
   6 #include <common.h>
   7 #include <clock_legacy.h>
   8 #include <display_options.h>
   9 #include <dm.h>
  10 #include <init.h>
  11 #include <asm/global_data.h>
  12 #include <dm/platform_data/serial_pl01x.h>
  13 #include <i2c.h>
  14 #include <malloc.h>
  15 #include <errno.h>
  16 #include <netdev.h>
  17 #include <fsl_ddr.h>
  18 #include <asm/io.h>
  19 #include <fdt_support.h>
  20 #include <linux/bitops.h>
  21 #include <linux/libfdt.h>
  22 #include <linux/delay.h>
  23 #include <fsl-mc/fsl_mc.h>
  24 #include <env_internal.h>
  25 #include <efi_loader.h>
  26 #include <asm/arch/mmu.h>
  27 #include <hwconfig.h>
  28 #include <asm/arch/clock.h>
  29 #include <asm/arch/config.h>
  30 #include <asm/arch/fsl_serdes.h>
  31 #include <asm/arch/soc.h>
  32 #include "../common/i2c_mux.h"
  33
  34 #include "../common/qixis.h"
  35 #include "../common/vid.h"
  36 #include <fsl_immap.h>
  37 #include <asm/arch-fsl-layerscape/fsl_icid.h>
  38 #include "lx2160a.h"
  39
  40 #ifdef CONFIG_EMC2305
  41 #include "../common/emc2305.h"
  42 #endif
  43
  44 #if defined(CONFIG_TARGET_LX2160AQDS) || defined(CONFIG_TARGET_LX2162AQDS)
  45 #define CFG_MUX_I2C_SDHC(reg, value)            ((reg & 0x3f) | value)
  46 #define SET_CFG_MUX1_SDHC1_SDHC(reg)            (reg & 0x3f)
  47 #define SET_CFG_MUX2_SDHC1_SPI(reg, value)      ((reg & 0xcf) | value)
  48 #define SET_CFG_MUX3_SDHC1_SPI(reg, value)      ((reg & 0xf8) | value)
  49 #define SET_CFG_MUX_SDHC2_DSPI(reg, value)      ((reg & 0xf8) | value)
  50 #define SET_CFG_MUX1_SDHC1_DSPI(reg, value)     ((reg & 0x3f) | value)
  51 #define SDHC1_BASE_PMUX_DSPI                    2
  52 #define SDHC2_BASE_PMUX_DSPI                    2
  53 #define IIC5_PMUX_SPI3                          3
  54 #endif /* CONFIG_TARGET_LX2160AQDS or CONFIG_TARGET_LX2162AQDS */
  55
  56 DECLARE_GLOBAL_DATA_PTR;
  57
  58 int board_early_init_f(void)
  59 {
  60 #if defined(CONFIG_SYS_I2C_EARLY_INIT) && defined(CONFIG_SPL_BUILD)
  61         i2c_early_init_f();
  62 #endif
  63
  64 #ifdef CONFIG_EMC2305
  65         select_i2c_ch_pca9547(I2C_MUX_CH_EMC2305, 0);
  66         emc2305_init(I2C_EMC2305_ADDR);
  67         set_fan_speed(I2C_EMC2305_PWM, I2C_EMC2305_ADDR);
  68         select_i2c_ch_pca9547(I2C_MUX_CH_DEFAULT, 0);
  69 #endif
  70
  71         fsl_lsch3_early_init_f();
  72         return 0;
  73 }
  74
  75 #ifdef CONFIG_OF_BOARD_FIXUP
  76 int board_fix_fdt(void *fdt)
  77 {
  78         char *reg_names, *reg_name;
  79         int names_len, old_name_len, new_name_len, remaining_names_len;
  80         struct str_map {
  81                 char *old_str;
  82                 char *new_str;
  83         } reg_names_map[] = {
  84                 { "ccsr", "dbi" },
  85                 { "pf_ctrl", "ctrl" }
  86         };
  87         int off = -1, i = 0;
  88
  89         if (IS_SVR_REV(get_svr(), 1, 0))
  90                 return 0;
  91
  92         fdt_for_each_node_by_compatible(off, fdt, -1, "fsl,lx2160a-pcie") {
  93                 fdt_setprop(fdt, off, "compatible", "fsl,ls-pcie",
  94                             strlen("fsl,ls-pcie") + 1);
  95
  96                 reg_names = (char *)fdt_getprop(fdt, off, "reg-names",
  97                                                 &names_len);
  98                 if (!reg_names)
  99                         continue;
 100
 101                 reg_name = reg_names;
 102                 remaining_names_len = names_len - (reg_name - reg_names);
 103                 i = 0;
 104                 while ((i < ARRAY_SIZE(reg_names_map)) && remaining_names_len) {
 105                         old_name_len = strlen(reg_names_map[i].old_str);
 106                         new_name_len = strlen(reg_names_map[i].new_str);
 107                         if (memcmp(reg_name, reg_names_map[i].old_str,
 108                                    old_name_len) == 0) {
 109                                 /* first only leave required bytes for new_str
 110                                  * and copy rest of the string after it
 111                                  */
 112                                 memcpy(reg_name + new_name_len,
 113                                        reg_name + old_name_len,
 114                                        remaining_names_len - old_name_len);
 115                                 /* Now copy new_str */
 116                                 memcpy(reg_name, reg_names_map[i].new_str,
 117                                        new_name_len);
 118                                 names_len -= old_name_len;
 119                                 names_len += new_name_len;
 120                                 i++;
 121                         }
 122
 123                         reg_name = memchr(reg_name, '\0', remaining_names_len);
 124                         if (!reg_name)
 125                                 break;
 126
 127                         reg_name += 1;
 128
 129                         remaining_names_len = names_len -
 130                                               (reg_name - reg_names);
 131                 }
 132
 133                 fdt_setprop(fdt, off, "reg-names", reg_names, names_len);
 134         }
 135
 136         /* Fixup u-boot's DTS in case this is a revC board and
 137          * we're using DM_ETH.
 138          */
 139         if (IS_ENABLED(CONFIG_TARGET_LX2160ARDB) && IS_ENABLED(CONFIG_DM_ETH))
 140                 fdt_fixup_board_phy_revc(fdt);
 141         return 0;
 142 }
 143 #endif
 144
 145 #if defined(CONFIG_TARGET_LX2160AQDS) || defined(CONFIG_TARGET_LX2162AQDS)
 146 void esdhc_dspi_status_fixup(void *blob)
 147 {
 148         const char esdhc0_path[] = "/soc/esdhc@2140000";
 149         const char esdhc1_path[] = "/soc/esdhc@2150000";
 150         const char dspi0_path[] = "/soc/spi@2100000";
 151         const char dspi1_path[] = "/soc/spi@2110000";
 152         const char dspi2_path[] = "/soc/spi@2120000";
 153
 154         struct ccsr_gur __iomem *gur = (void *)(CFG_SYS_FSL_GUTS_ADDR);
 155         u32 sdhc1_base_pmux;
 156         u32 sdhc2_base_pmux;
 157         u32 iic5_pmux;
 158
 159         /* Check RCW field sdhc1_base_pmux to enable/disable
 160          * esdhc0/dspi0 DT node
 161          */
 162         sdhc1_base_pmux = gur_in32(&gur->rcwsr[FSL_CHASSIS3_RCWSR12_REGSR - 1])
 163                 & FSL_CHASSIS3_SDHC1_BASE_PMUX_MASK;
 164         sdhc1_base_pmux >>= FSL_CHASSIS3_SDHC1_BASE_PMUX_SHIFT;
 165
 166         if (sdhc1_base_pmux == SDHC1_BASE_PMUX_DSPI) {
 167                 do_fixup_by_path(blob, dspi0_path, "status", "okay",
 168                                  sizeof("okay"), 1);
 169                 do_fixup_by_path(blob, esdhc0_path, "status", "disabled",
 170                                  sizeof("disabled"), 1);
 171         } else {
 172                 do_fixup_by_path(blob, esdhc0_path, "status", "okay",
 173                                  sizeof("okay"), 1);
 174                 do_fixup_by_path(blob, dspi0_path, "status", "disabled",
 175                                  sizeof("disabled"), 1);
 176         }
 177
 178         /* Check RCW field sdhc2_base_pmux to enable/disable
 179          * esdhc1/dspi1 DT node
 180          */
 181         sdhc2_base_pmux = gur_in32(&gur->rcwsr[FSL_CHASSIS3_RCWSR13_REGSR - 1])
 182                 & FSL_CHASSIS3_SDHC2_BASE_PMUX_MASK;
 183         sdhc2_base_pmux >>= FSL_CHASSIS3_SDHC2_BASE_PMUX_SHIFT;
 184
 185         if (sdhc2_base_pmux == SDHC2_BASE_PMUX_DSPI) {
 186                 do_fixup_by_path(blob, dspi1_path, "status", "okay",
 187                                  sizeof("okay"), 1);
 188                 do_fixup_by_path(blob, esdhc1_path, "status", "disabled",
 189                                  sizeof("disabled"), 1);
 190         } else {
 191                 do_fixup_by_path(blob, esdhc1_path, "status", "okay",
 192                                  sizeof("okay"), 1);
 193                 do_fixup_by_path(blob, dspi1_path, "status", "disabled",
 194                                  sizeof("disabled"), 1);
 195         }
 196
 197         /* Check RCW field IIC5 to enable dspi2 DT node */
 198         iic5_pmux = gur_in32(&gur->rcwsr[FSL_CHASSIS3_RCWSR12_REGSR - 1])
 199                 & FSL_CHASSIS3_IIC5_PMUX_MASK;
 200         iic5_pmux >>= FSL_CHASSIS3_IIC5_PMUX_SHIFT;
 201
 202         if (iic5_pmux == IIC5_PMUX_SPI3)
 203                 do_fixup_by_path(blob, dspi2_path, "status", "okay",
 204                                  sizeof("okay"), 1);
 205         else
 206                 do_fixup_by_path(blob, dspi2_path, "status", "disabled",
 207                                  sizeof("disabled"), 1);
 208 }
 209 #endif
 210
 211 int esdhc_status_fixup(void *blob, const char *compat)
 212 {
 213 #if defined(CONFIG_TARGET_LX2160AQDS) || defined(CONFIG_TARGET_LX2162AQDS)
 214         /* Enable esdhc and dspi DT nodes based on RCW fields */
 215         esdhc_dspi_status_fixup(blob);
 216 #else
 217         /* Enable both esdhc DT nodes for LX2160ARDB */
 218         do_fixup_by_compat(blob, compat, "status", "okay",
 219                            sizeof("okay"), 1);
 220 #endif
 221         return 0;
 222 }
 223
 224 #if defined(CONFIG_VID)
 225 int i2c_multiplexer_select_vid_channel(u8 channel)
 226 {
 227         return select_i2c_ch_pca9547(channel, 0);
 228 }
 229
 230 int init_func_vid(void)
 231 {
 232         int set_vid;
 233
 234         if (IS_SVR_REV(get_svr(), 1, 0))
 235                 set_vid = adjust_vdd(800);
 236         else
 237                 set_vid = adjust_vdd(0);
 238
 239         if (set_vid < 0)
 240                 printf("core voltage not adjusted\n");
 241
 242         return 0;
 243 }
 244 #endif
 245
 246 int checkboard(void)
 247 {
 248         enum boot_src src = get_boot_src();
 249         char buf[64];
 250         u8 sw;
 251 #if defined(CONFIG_TARGET_LX2160AQDS) || defined(CONFIG_TARGET_LX2162AQDS)
 252         int clock;
 253         static const char *const freq[] = {"100", "125", "156.25",
 254                                            "161.13", "322.26", "", "", "",
 255                                            "", "", "", "", "", "", "",
 256                                            "100 separate SSCG"};
 257 #endif
 258
 259         cpu_name(buf);
 260 #if defined(CONFIG_TARGET_LX2160AQDS) || defined(CONFIG_TARGET_LX2162AQDS)
 261         printf("Board: %s-QDS, ", buf);
 262 #else
 263         printf("Board: %s-RDB, ", buf);
 264 #endif
 265
 266         sw = QIXIS_READ(arch);
 267         printf("Board version: %c, boot from ", (sw & 0xf) - 1 + 'A');
 268
 269         if (src == BOOT_SOURCE_SD_MMC) {
 270                 puts("SD\n");
 271         } else if (src == BOOT_SOURCE_SD_MMC2) {
 272                 puts("eMMC\n");
 273         } else {
 274                 sw = QIXIS_READ(brdcfg[0]);
 275                 sw = (sw >> QIXIS_XMAP_SHIFT) & QIXIS_XMAP_MASK;
 276                 switch (sw) {
 277                 case 0:
 278                 case 4:
 279                         puts("FlexSPI DEV#0\n");
 280                         break;
 281                 case 1:
 282                         puts("FlexSPI DEV#1\n");
 283                         break;
 284                 case 2:
 285                 case 3:
 286                         puts("FlexSPI EMU\n");
 287                         break;
 288                 default:
 289                         printf("invalid setting, xmap: %d\n", sw);
 290                         break;
 291                 }
 292         }
 293 #if defined(CONFIG_TARGET_LX2160ARDB)
 294         printf("FPGA: v%d.%d\n", QIXIS_READ(scver), QIXIS_READ(tagdata));
 295
 296         puts("SERDES1 Reference: Clock1 = 161.13MHz Clock2 = 161.13MHz\n");
 297         puts("SERDES2 Reference: Clock1 = 100MHz Clock2 = 100MHz\n");
 298         puts("SERDES3 Reference: Clock1 = 100MHz Clock2 = 100MHz\n");
 299 #else
 300         printf("FPGA: v%d (%s), build %d",
 301                (int)QIXIS_READ(scver), qixis_read_tag(buf),
 302                (int)qixis_read_minor());
 303         /* the timestamp string contains "\n" at the end */
 304         printf(" on %s", qixis_read_time(buf));
 305
 306         puts("SERDES1 Reference : ");
 307         sw = QIXIS_READ(brdcfg[2]);
 308         clock = sw >> 4;
 309         printf("Clock1 = %sMHz ", freq[clock]);
 310 #if defined(CONFIG_TARGET_LX2160AQDS)
 311         clock = sw & 0x0f;
 312         printf("Clock2 = %sMHz", freq[clock]);
 313 #endif
 314         sw = QIXIS_READ(brdcfg[3]);
 315         puts("\nSERDES2 Reference : ");
 316         clock = sw >> 4;
 317         printf("Clock1 = %sMHz ", freq[clock]);
 318         clock = sw & 0x0f;
 319         printf("Clock2 = %sMHz\n", freq[clock]);
 320 #if defined(CONFIG_TARGET_LX2160AQDS)
 321         sw = QIXIS_READ(brdcfg[12]);
 322         puts("SERDES3 Reference : ");
 323         clock = sw >> 4;
 324         printf("Clock1 = %sMHz Clock2 = %sMHz\n", freq[clock], freq[clock]);
 325 #endif
 326 #endif
 327         return 0;
 328 }
 329
 330 #if defined(CONFIG_TARGET_LX2160AQDS) || defined(CONFIG_TARGET_LX2162AQDS)
 331 static void esdhc_adapter_card_ident(void)
 332 {
 333         u8 card_id, val;
 334
 335         val = QIXIS_READ(sdhc1);
 336         card_id = val & QIXIS_SDID_MASK;
 337
 338         switch (card_id) {
 339         case QIXIS_ESDHC_ADAPTER_TYPE_SD:
 340                 /* Power cycle to card */
 341                 val &= ~QIXIS_SDHC1_S1V3;
 342                 QIXIS_WRITE(sdhc1, val);
 343                 mdelay(1);
 344                 val |= QIXIS_SDHC1_S1V3;
 345                 QIXIS_WRITE(sdhc1, val);
 346                 /* Route to SDHC1_VS */
 347                 val = QIXIS_READ(brdcfg[11]);
 348                 val |= QIXIS_SDHC1_VS;
 349                 QIXIS_WRITE(brdcfg[11], val);
 350                 break;
 351         default:
 352                 break;
 353         }
 354 }
 355
 356 int config_board_mux(void)
 357 {
 358         u8 reg11, reg5, reg13;
 359         struct ccsr_gur __iomem *gur = (void *)(CFG_SYS_FSL_GUTS_ADDR);
 360         u32 sdhc1_base_pmux;
 361         u32 sdhc2_base_pmux;
 362         u32 iic5_pmux;
 363
 364         /* Routes {I2C2_SCL, I2C2_SDA} to SDHC1 as {SDHC1_CD_B, SDHC1_WP}.
 365          * Routes {I2C3_SCL, I2C3_SDA} to CAN transceiver as {CAN1_TX,CAN1_RX}.
 366          * Routes {I2C4_SCL, I2C4_SDA} to CAN transceiver as {CAN2_TX,CAN2_RX}.
 367          * Qixis and remote systems are isolated from the I2C1 bus.
 368          * Processor connections are still available.
 369          * SPI2 CS2_B controls EN25S64 SPI memory device.
 370          * SPI3 CS2_B controls EN25S64 SPI memory device.
 371          * EC2 connects to PHY #2 using RGMII protocol.
 372          * CLK_OUT connects to FPGA for clock measurement.
 373          */
 374
 375         reg5 = QIXIS_READ(brdcfg[5]);
 376         reg5 = CFG_MUX_I2C_SDHC(reg5, 0x40);
 377         QIXIS_WRITE(brdcfg[5], reg5);
 378
 379         /* Check RCW field sdhc1_base_pmux
 380          * esdhc0 : sdhc1_base_pmux = 0
 381          * dspi0  : sdhc1_base_pmux = 2
 382          */
 383         sdhc1_base_pmux = gur_in32(&gur->rcwsr[FSL_CHASSIS3_RCWSR12_REGSR - 1])
 384                 & FSL_CHASSIS3_SDHC1_BASE_PMUX_MASK;
 385         sdhc1_base_pmux >>= FSL_CHASSIS3_SDHC1_BASE_PMUX_SHIFT;
 386
 387         if (sdhc1_base_pmux == SDHC1_BASE_PMUX_DSPI) {
 388                 reg11 = QIXIS_READ(brdcfg[11]);
 389                 reg11 = SET_CFG_MUX1_SDHC1_DSPI(reg11, 0x40);
 390                 QIXIS_WRITE(brdcfg[11], reg11);
 391         } else {
 392                 /* - Routes {SDHC1_CMD, SDHC1_CLK } to SDHC1 adapter slot.
 393                  *          {SDHC1_DAT3, SDHC1_DAT2} to SDHC1 adapter slot.
 394                  *          {SDHC1_DAT1, SDHC1_DAT0} to SDHC1 adapter slot.
 395                  */
 396                 reg11 = QIXIS_READ(brdcfg[11]);
 397                 reg11 = SET_CFG_MUX1_SDHC1_SDHC(reg11);
 398                 QIXIS_WRITE(brdcfg[11], reg11);
 399         }
 400
 401         /* Check RCW field sdhc2_base_pmux
 402          * esdhc1 : sdhc2_base_pmux = 0 (default)
 403          * dspi1  : sdhc2_base_pmux = 2
 404          */
 405         sdhc2_base_pmux = gur_in32(&gur->rcwsr[FSL_CHASSIS3_RCWSR13_REGSR - 1])
 406                 & FSL_CHASSIS3_SDHC2_BASE_PMUX_MASK;
 407         sdhc2_base_pmux >>= FSL_CHASSIS3_SDHC2_BASE_PMUX_SHIFT;
 408
 409         if (sdhc2_base_pmux == SDHC2_BASE_PMUX_DSPI) {
 410                 reg13 = QIXIS_READ(brdcfg[13]);
 411                 reg13 = SET_CFG_MUX_SDHC2_DSPI(reg13, 0x01);
 412                 QIXIS_WRITE(brdcfg[13], reg13);
 413         } else {
 414                 reg13 = QIXIS_READ(brdcfg[13]);
 415                 reg13 = SET_CFG_MUX_SDHC2_DSPI(reg13, 0x00);
 416                 QIXIS_WRITE(brdcfg[13], reg13);
 417         }
 418
 419         /* Check RCW field IIC5 to enable dspi2 DT nodei
 420          * dspi2: IIC5 = 3
 421          */
 422         iic5_pmux = gur_in32(&gur->rcwsr[FSL_CHASSIS3_RCWSR12_REGSR - 1])
 423                 & FSL_CHASSIS3_IIC5_PMUX_MASK;
 424         iic5_pmux >>= FSL_CHASSIS3_IIC5_PMUX_SHIFT;
 425
 426         if (iic5_pmux == IIC5_PMUX_SPI3) {
 427                 /* - Routes {SDHC1_DAT4} to SPI3 devices as {SPI3_M_CS0_B}. */
 428                 reg11 = QIXIS_READ(brdcfg[11]);
 429                 reg11 = SET_CFG_MUX2_SDHC1_SPI(reg11, 0x10);
 430                 QIXIS_WRITE(brdcfg[11], reg11);
 431
 432                 /* - Routes {SDHC1_DAT5, SDHC1_DAT6} nowhere.
 433                  * {SDHC1_DAT7, SDHC1_DS } to {nothing, SPI3_M0_CLK }.
 434                  * {I2C5_SCL, I2C5_SDA } to {SPI3_M0_MOSI, SPI3_M0_MISO}.
 435                  */
 436                 reg11 = QIXIS_READ(brdcfg[11]);
 437                 reg11 = SET_CFG_MUX3_SDHC1_SPI(reg11, 0x01);
 438                 QIXIS_WRITE(brdcfg[11], reg11);
 439         } else {
 440                 /*
 441                  * If {SDHC1_DAT4} has been configured to route to SDHC1_VS,
 442                  * do not change it.
 443                  * Otherwise route {SDHC1_DAT4} to SDHC1 adapter slot.
 444                  */
 445                 reg11 = QIXIS_READ(brdcfg[11]);
 446                 if ((reg11 & 0x30) != 0x30) {
 447                         reg11 = SET_CFG_MUX2_SDHC1_SPI(reg11, 0x00);
 448                         QIXIS_WRITE(brdcfg[11], reg11);
 449                 }
 450
 451                 /* - Routes {SDHC1_DAT5, SDHC1_DAT6} to SDHC1 adapter slot.
 452                  * {SDHC1_DAT7, SDHC1_DS } to SDHC1 adapter slot.
 453                  * {I2C5_SCL, I2C5_SDA } to SDHC1 adapter slot.
 454                  */
 455                 reg11 = QIXIS_READ(brdcfg[11]);
 456                 reg11 = SET_CFG_MUX3_SDHC1_SPI(reg11, 0x00);
 457                 QIXIS_WRITE(brdcfg[11], reg11);
 458         }
 459
 460         return 0;
 461 }
 462
 463 int board_early_init_r(void)
 464 {
 465         esdhc_adapter_card_ident();
 466         return 0;
 467 }
 468 #elif defined(CONFIG_TARGET_LX2160ARDB)
 469 int config_board_mux(void)
 470 {
 471         u8 brdcfg;
 472
 473         brdcfg = QIXIS_READ(brdcfg[4]);
 474         /* The BRDCFG4 register controls general board configuration.
 475          *|-------------------------------------------|
 476          *|Field  | Function                          |
 477          *|-------------------------------------------|
 478          *|5      | CAN I/O Enable (net CFG_CAN_EN_B):|
 479          *|CAN_EN | 0= CAN transceivers are disabled. |
 480          *|       | 1= CAN transceivers are enabled.  |
 481          *|-------------------------------------------|
 482          */
 483         brdcfg |= BIT_MASK(5);
 484         QIXIS_WRITE(brdcfg[4], brdcfg);
 485
 486         return 0;
 487 }
 488 #else
 489 int config_board_mux(void)
 490 {
 491         return 0;
 492 }
 493 #endif
 494
 495 #if IS_ENABLED(CONFIG_TARGET_LX2160ARDB)
 496 u8 get_board_rev(void)
 497 {
 498         u8 board_rev = (QIXIS_READ(arch) & 0xf) - 1 + 'A';
 499
 500         return board_rev;
 501 }
 502 #endif
 503
 504 unsigned long get_board_sys_clk(void)
 505 {
 506 #if defined(CONFIG_TARGET_LX2160AQDS) || defined(CONFIG_TARGET_LX2162AQDS)
 507         u8 sysclk_conf = QIXIS_READ(brdcfg[1]);
 508
 509         switch (sysclk_conf & 0x03) {
 510         case QIXIS_SYSCLK_100:
 511                 return 100000000;
 512         case QIXIS_SYSCLK_125:
 513                 return 125000000;
 514         case QIXIS_SYSCLK_133:
 515                 return 133333333;
 516         }
 517         return 100000000;
 518 #else
 519         return 100000000;
 520 #endif
 521 }
 522
 523 unsigned long get_board_ddr_clk(void)
 524 {
 525 #if defined(CONFIG_TARGET_LX2160AQDS) || defined(CONFIG_TARGET_LX2162AQDS)
 526         u8 ddrclk_conf = QIXIS_READ(brdcfg[1]);
 527
 528         switch ((ddrclk_conf & 0x30) >> 4) {
 529         case QIXIS_DDRCLK_100:
 530                 return 100000000;
 531         case QIXIS_DDRCLK_125:
 532                 return 125000000;
 533         case QIXIS_DDRCLK_133:
 534                 return 133333333;
 535         }
 536         return 100000000;
 537 #else
 538         return 100000000;
 539 #endif
 540 }
 541
 542 int board_init(void)
 543 {
 544 #if defined(CONFIG_FSL_MC_ENET) && defined(CONFIG_TARGET_LX2160ARDB)
 545         u32 __iomem *irq_ccsr = (u32 __iomem *)ISC_BASE;
 546 #endif
 547
 548         select_i2c_ch_pca9547(I2C_MUX_CH_DEFAULT, 0);
 549
 550 #if defined(CONFIG_FSL_MC_ENET) && defined(CONFIG_TARGET_LX2160ARDB)
 551         /* invert AQR107 IRQ pins polarity */
 552         out_le32(irq_ccsr + IRQCR_OFFSET / 4, AQR107_IRQ_MASK);
 553 #endif
 554
 555 #if !defined(CONFIG_SYS_EARLY_PCI_INIT)
 556         pci_init();
 557 #endif
 558         return 0;
 559 }
 560
 561 void detail_board_ddr_info(void)
 562 {
 563         int i;
 564         u64 ddr_size = 0;
 565
 566         puts("\nDDR    ");
 567         for (i = 0; i < CONFIG_NR_DRAM_BANKS; i++)
 568                 ddr_size += gd->bd->bi_dram[i].size;
 569         print_size(ddr_size, "");
 570         print_ddr_info(0);
 571 }
 572
 573 #ifdef CONFIG_MISC_INIT_R
 574 int misc_init_r(void)
 575 {
 576         config_board_mux();
 577
 578         return 0;
 579 }
 580 #endif
 581
 582 #ifdef CONFIG_VID
 583 u16 soc_get_fuse_vid(int vid_index)
 584 {
 585         static const u16 vdd[32] = {
 586                 8250,
 587                 7875,
 588                 7750,
 589                 0,      /* reserved */
 590                 0,      /* reserved */
 591                 0,      /* reserved */
 592                 0,      /* reserved */
 593                 0,      /* reserved */
 594                 0,      /* reserved */
 595                 0,      /* reserved */
 596                 0,      /* reserved */
 597                 0,      /* reserved */
 598                 0,      /* reserved */
 599                 0,      /* reserved */
 600                 0,      /* reserved */
 601                 0,      /* reserved */
 602                 8000,
 603                 8125,
 604                 8250,
 605                 0,      /* reserved */
 606                 8500,
 607                 0,      /* reserved */
 608                 0,      /* reserved */
 609                 0,      /* reserved */
 610                 0,      /* reserved */
 611                 0,      /* reserved */
 612                 0,      /* reserved */
 613                 0,      /* reserved */
 614                 0,      /* reserved */
 615                 0,      /* reserved */
 616                 0,      /* reserved */
 617                 0,      /* reserved */
 618         };
 619
 620         return vdd[vid_index];
 621 };
 622 #endif
 623
 624 #ifdef CONFIG_FSL_MC_ENET
 625
 626 void fdt_fixup_board_enet(void *fdt)
 627 {
 628         int offset;
 629
 630         offset = fdt_path_offset(fdt, "/soc/fsl-mc");
 631
 632         if (offset < 0)
 633                 offset = fdt_path_offset(fdt, "/fsl-mc");
 634
 635         if (offset < 0) {
 636                 printf("%s: fsl-mc node not found in device tree (error %d)\n",
 637                        __func__, offset);
 638                 return;
 639         }
 640
 641         if (get_mc_boot_status() == 0 &&
 642             (is_lazy_dpl_addr_valid() || get_dpl_apply_status() == 0)) {
 643                 fdt_status_okay(fdt, offset);
 644                 if (IS_ENABLED(CONFIG_TARGET_LX2160ARDB))
 645                         fdt_fixup_board_phy_revc(fdt);
 646         } else {
 647                 fdt_status_fail(fdt, offset);
 648         }
 649 }
 650
 651 void board_quiesce_devices(void)
 652 {
 653         fsl_mc_ldpaa_exit(gd->bd);
 654 }
 655 #endif
 656
 657 #if IS_ENABLED(CONFIG_TARGET_LX2160ARDB)
 658 int fdt_fixup_add_thermal(void *blob, int mux_node, int channel, int reg)
 659 {
 660         int err;
 661         int noff;
 662         int offset;
 663         char channel_node_name[50];
 664         char thermal_node_name[50];
 665         u32 phandle;
 666
 667         snprintf(channel_node_name, sizeof(channel_node_name),
 668                  "i2c@%x", channel);
 669         debug("channel_node_name = %s\n", channel_node_name);
 670
 671         snprintf(thermal_node_name, sizeof(thermal_node_name),
 672                  "temperature-sensor@%x", reg);
 673         debug("thermal_node_name = %s\n", thermal_node_name);
 674
 675         err = fdt_increase_size(blob, 200);
 676         if (err) {
 677                 printf("fdt_increase_size: err=%s\n", fdt_strerror(err));
 678                 return err;
 679         }
 680
 681         noff = fdt_subnode_offset(blob, mux_node, (const char *)
 682                                   channel_node_name);
 683         if (noff < 0) {
 684                 /* channel node not found - create it */
 685                 noff = fdt_add_subnode(blob, mux_node, channel_node_name);
 686                 if (noff < 0) {
 687                         printf("fdt_add_subnode: err=%s\n", fdt_strerror(err));
 688                         return err;
 689                 }
 690                 fdt_setprop_u32 (blob, noff, "#address-cells", 1);
 691                 fdt_setprop_u32 (blob, noff, "#size-cells", 0);
 692                 fdt_setprop_u32 (blob, noff, "reg", channel);
 693         }
 694
 695         /* Create thermal node*/
 696         offset = fdt_add_subnode(blob, noff, thermal_node_name);
 697         fdt_setprop(blob, offset, "compatible", "nxp,sa56004",
 698                     strlen("nxp,sa56004") + 1);
 699         fdt_setprop_u32 (blob, offset, "reg", reg);
 700
 701         /* fixup phandle*/
 702         noff = fdt_node_offset_by_compatible(blob, -1, "regulator-fixed");
 703         if (noff < 0) {
 704                 printf("%s : failed to get phandle\n", __func__);
 705                 return noff;
 706         }
 707         phandle = fdt_get_phandle(blob, noff);
 708         fdt_setprop_u32 (blob, offset, "vcc-supply", phandle);
 709
 710         return 0;
 711 }
 712
 713 void fdt_fixup_delete_thermal(void *blob, int mux_node, int channel, int reg)
 714 {
 715         int node;
 716         int value;
 717         int err;
 718         int subnode;
 719
 720         fdt_for_each_subnode(subnode, blob, mux_node) {
 721                 value = fdtdec_get_uint(blob, subnode, "reg", -1);
 722                 if (value == channel) {
 723                         /* delete thermal node */
 724                         fdt_for_each_subnode(node, blob, subnode) {
 725                                 value = fdtdec_get_uint(blob, node, "reg", -1);
 726                                 err = fdt_node_check_compatible(blob, node,
 727                                                                 "nxp,sa56004");
 728                                 if (!err && value == reg) {
 729                                         fdt_del_node(blob, node);
 730                                         break;
 731                                 }
 732                         }
 733                 }
 734         }
 735 }
 736
 737 void fdt_fixup_i2c_thermal_node(void *blob)
 738 {
 739         int i2coffset;
 740         int mux_node;
 741         int reg;
 742         int err;
 743
 744         i2coffset = fdt_node_offset_by_compat_reg(blob, "fsl,vf610-i2c",
 745                                                   0x2000000);
 746         if (i2coffset != -FDT_ERR_NOTFOUND) {
 747                 fdt_for_each_subnode(mux_node, blob, i2coffset) {
 748                         reg = fdtdec_get_uint(blob, mux_node, "reg", -1);
 749                         err = fdt_node_check_compatible(blob, mux_node,
 750                                                         "nxp,pca9547");
 751                         if (!err && reg == 0x77) {
 752                                 fdt_fixup_delete_thermal(blob, mux_node,
 753                                                          0x3, 0x4d);
 754                                 err = fdt_fixup_add_thermal(blob, mux_node,
 755                                                             0x3, 0x48);
 756                                 if (err)
 757                                         printf("%s: Add thermal node failed\n",
 758                                                __func__);
 759                         }
 760                 }
 761         } else {
 762                 printf("%s: i2c node not found\n", __func__);
 763         }
 764 }
 765 #endif
 766
 767 #ifdef CONFIG_OF_BOARD_SETUP
 768 int ft_board_setup(void *blob, struct bd_info *bd)
 769 {
 770         int i;
 771         u16 mc_memory_bank = 0;
 772
 773         u64 *base;
 774         u64 *size;
 775         u64 mc_memory_base = 0;
 776         u64 mc_memory_size = 0;
 777         u16 total_memory_banks;
 778         int err;
 779
 780         err = fdt_increase_size(blob, 512);
 781         if (err) {
 782                 printf("%s fdt_increase_size: err=%s\n", __func__,
 783                        fdt_strerror(err));
 784                 return err;
 785         }
 786
 787         ft_cpu_setup(blob, bd);
 788
 789         fdt_fixup_mc_ddr(&mc_memory_base, &mc_memory_size);
 790
 791         if (mc_memory_base != 0)
 792                 mc_memory_bank++;
 793
 794         total_memory_banks = CONFIG_NR_DRAM_BANKS + mc_memory_bank;
 795
 796         base = calloc(total_memory_banks, sizeof(u64));
 797         size = calloc(total_memory_banks, sizeof(u64));
 798
 799         /* fixup DT for the three GPP DDR banks */
 800         for (i = 0; i < CONFIG_NR_DRAM_BANKS; i++) {
 801                 base[i] = gd->bd->bi_dram[i].start;
 802                 size[i] = gd->bd->bi_dram[i].size;
 803         }
 804
 805 #ifdef CONFIG_RESV_RAM
 806         /* reduce size if reserved memory is within this bank */
 807         if (gd->arch.resv_ram >= base[0] &&
 808             gd->arch.resv_ram < base[0] + size[0])
 809                 size[0] = gd->arch.resv_ram - base[0];
 810         else if (gd->arch.resv_ram >= base[1] &&
 811                  gd->arch.resv_ram < base[1] + size[1])
 812                 size[1] = gd->arch.resv_ram - base[1];
 813         else if (gd->arch.resv_ram >= base[2] &&
 814                  gd->arch.resv_ram < base[2] + size[2])
 815                 size[2] = gd->arch.resv_ram - base[2];
 816 #endif
 817
 818         if (mc_memory_base != 0) {
 819                 for (i = 0; i <= total_memory_banks; i++) {
 820                         if (base[i] == 0 && size[i] == 0) {
 821                                 base[i] = mc_memory_base;
 822                                 size[i] = mc_memory_size;
 823                                 break;
 824                         }
 825                 }
 826         }
 827
 828         fdt_fixup_memory_banks(blob, base, size, total_memory_banks);
 829
 830 #ifdef CONFIG_USB_HOST
 831         fsl_fdt_fixup_dr_usb(blob, bd);
 832 #endif
 833
 834 #ifdef CONFIG_FSL_MC_ENET
 835         fdt_fsl_mc_fixup_iommu_map_entry(blob);
 836         fdt_fixup_board_enet(blob);
 837 #endif
 838         fdt_fixup_icid(blob);
 839
 840 #if IS_ENABLED(CONFIG_TARGET_LX2160ARDB)
 841         if (get_board_rev() == 'C')
 842                 fdt_fixup_i2c_thermal_node(blob);
 843 #endif
 844
 845         return 0;
 846 }
 847 #endif
 848
 849 void qixis_dump_switch(void)
 850 {
 851         int i, nr_of_cfgsw;
 852
 853         QIXIS_WRITE(cms[0], 0x00);
 854         nr_of_cfgsw = QIXIS_READ(cms[1]);
 855
 856         puts("DIP switch settings dump:\n");
 857         for (i = 1; i <= nr_of_cfgsw; i++) {
 858                 QIXIS_WRITE(cms[0], i);
 859                 printf("SW%d = (0x%02x)\n", i, QIXIS_READ(cms[1]));
 860         }
 861 }