board/freescale/lx2160a/lx2160a.c

   1 // SPDX-License-Identifier: GPL-2.0+
   2 /*
   3  * Copyright 2018-2020 NXP
   4  */
   5
   6 #include <common.h>
   7 #include <clock_legacy.h>
   8 #include <dm.h>
   9 #include <init.h>
  10 #include <dm/platform_data/serial_pl01x.h>
  11 #include <i2c.h>
  12 #include <malloc.h>
  13 #include <errno.h>
  14 #include <netdev.h>
  15 #include <fsl_ddr.h>
  16 #include <fsl_sec.h>
  17 #include <asm/io.h>
  18 #include <fdt_support.h>
  19 #include <linux/bitops.h>
  20 #include <linux/libfdt.h>
  21 #include <linux/delay.h>
  22 #include <fsl-mc/fsl_mc.h>
  23 #include <env_internal.h>
  24 #include <efi_loader.h>
  25 #include <asm/arch/mmu.h>
  26 #include <hwconfig.h>
  27 #include <asm/arch/clock.h>
  28 #include <asm/arch/config.h>
  29 #include <asm/arch/fsl_serdes.h>
  30 #include <asm/arch/soc.h>
  31 #include "../common/qixis.h"
  32 #include "../common/vid.h"
  33 #include <fsl_immap.h>
  34 #include <asm/arch-fsl-layerscape/fsl_icid.h>
  35 #include "lx2160a.h"
  36
  37 #ifdef CONFIG_EMC2305
  38 #include "../common/emc2305.h"
  39 #endif
  40
  41 #if defined(CONFIG_TARGET_LX2160AQDS) || defined(CONFIG_TARGET_LX2162AQDS)
  42 #define CFG_MUX_I2C_SDHC(reg, value)            ((reg & 0x3f) | value)
  43 #define SET_CFG_MUX1_SDHC1_SDHC(reg)            (reg & 0x3f)
  44 #define SET_CFG_MUX2_SDHC1_SPI(reg, value)      ((reg & 0xcf) | value)
  45 #define SET_CFG_MUX3_SDHC1_SPI(reg, value)      ((reg & 0xf8) | value)
  46 #define SET_CFG_MUX_SDHC2_DSPI(reg, value)      ((reg & 0xf8) | value)
  47 #define SET_CFG_MUX1_SDHC1_DSPI(reg, value)     ((reg & 0x3f) | value)
  48 #define SDHC1_BASE_PMUX_DSPI                    2
  49 #define SDHC2_BASE_PMUX_DSPI                    2
  50 #define IIC5_PMUX_SPI3                          3
  51 #endif /* CONFIG_TARGET_LX2160AQDS or CONFIG_TARGET_LX2162AQDS */
  52
  53 DECLARE_GLOBAL_DATA_PTR;
  54
  55 static struct pl01x_serial_platdata serial0 = {
  56 #if CONFIG_CONS_INDEX == 0
  57         .base = CONFIG_SYS_SERIAL0,
  58 #elif CONFIG_CONS_INDEX == 1
  59         .base = CONFIG_SYS_SERIAL1,
  60 #else
  61 #error "Unsupported console index value."
  62 #endif
  63         .type = TYPE_PL011,
  64 };
  65
  66 U_BOOT_DEVICE(nxp_serial0) = {
  67         .name = "serial_pl01x",
  68         .platdata = &serial0,
  69 };
  70
  71 static struct pl01x_serial_platdata serial1 = {
  72         .base = CONFIG_SYS_SERIAL1,
  73         .type = TYPE_PL011,
  74 };
  75
  76 U_BOOT_DEVICE(nxp_serial1) = {
  77         .name = "serial_pl01x",
  78         .platdata = &serial1,
  79 };
  80
  81 int select_i2c_ch_pca9547(u8 ch)
  82 {
  83         int ret;
  84
  85 #ifndef CONFIG_DM_I2C
  86         ret = i2c_write(I2C_MUX_PCA_ADDR_PRI, 0, 1, &ch, 1);
  87 #else
  88         struct udevice *dev;
  89
  90         ret = i2c_get_chip_for_busnum(0, I2C_MUX_PCA_ADDR_PRI, 1, &dev);
  91         if (!ret)
  92                 ret = dm_i2c_write(dev, 0, &ch, 1);
  93 #endif
  94         if (ret) {
  95                 puts("PCA: failed to select proper channel\n");
  96                 return ret;
  97         }
  98
  99         return 0;
 100 }
 101
 102 static void uart_get_clock(void)
 103 {
 104         serial0.clock = get_serial_clock();
 105         serial1.clock = get_serial_clock();
 106 }
 107
 108 int board_early_init_f(void)
 109 {
 110 #ifdef CONFIG_SYS_I2C_EARLY_INIT
 111         i2c_early_init_f();
 112 #endif
 113         /* get required clock for UART IP */
 114         uart_get_clock();
 115
 116 #ifdef CONFIG_EMC2305
 117         select_i2c_ch_pca9547(I2C_MUX_CH_EMC2305);
 118         emc2305_init(I2C_EMC2305_ADDR);
 119         set_fan_speed(I2C_EMC2305_PWM, I2C_EMC2305_ADDR);
 120         select_i2c_ch_pca9547(I2C_MUX_CH_DEFAULT);
 121 #endif
 122
 123         fsl_lsch3_early_init_f();
 124         return 0;
 125 }
 126
 127 #ifdef CONFIG_OF_BOARD_FIXUP
 128 int board_fix_fdt(void *fdt)
 129 {
 130         char *reg_names, *reg_name;
 131         int names_len, old_name_len, new_name_len, remaining_names_len;
 132         struct str_map {
 133                 char *old_str;
 134                 char *new_str;
 135         } reg_names_map[] = {
 136                 { "ccsr", "dbi" },
 137                 { "pf_ctrl", "ctrl" }
 138         };
 139         int off = -1, i = 0;
 140
 141         if (IS_SVR_REV(get_svr(), 1, 0))
 142                 return 0;
 143
 144         off = fdt_node_offset_by_compatible(fdt, -1, "fsl,lx2160a-pcie");
 145         while (off != -FDT_ERR_NOTFOUND) {
 146                 fdt_setprop(fdt, off, "compatible", "fsl,ls-pcie",
 147                             strlen("fsl,ls-pcie") + 1);
 148
 149                 reg_names = (char *)fdt_getprop(fdt, off, "reg-names",
 150                                                 &names_len);
 151                 if (!reg_names)
 152                         continue;
 153
 154                 reg_name = reg_names;
 155                 remaining_names_len = names_len - (reg_name - reg_names);
 156                 i = 0;
 157                 while ((i < ARRAY_SIZE(reg_names_map)) && remaining_names_len) {
 158                         old_name_len = strlen(reg_names_map[i].old_str);
 159                         new_name_len = strlen(reg_names_map[i].new_str);
 160                         if (memcmp(reg_name, reg_names_map[i].old_str,
 161                                    old_name_len) == 0) {
 162                                 /* first only leave required bytes for new_str
 163                                  * and copy rest of the string after it
 164                                  */
 165                                 memcpy(reg_name + new_name_len,
 166                                        reg_name + old_name_len,
 167                                        remaining_names_len - old_name_len);
 168                                 /* Now copy new_str */
 169                                 memcpy(reg_name, reg_names_map[i].new_str,
 170                                        new_name_len);
 171                                 names_len -= old_name_len;
 172                                 names_len += new_name_len;
 173                                 i++;
 174                         }
 175
 176                         reg_name = memchr(reg_name, '\0', remaining_names_len);
 177                         if (!reg_name)
 178                                 break;
 179
 180                         reg_name += 1;
 181
 182                         remaining_names_len = names_len -
 183                                               (reg_name - reg_names);
 184                 }
 185
 186                 fdt_setprop(fdt, off, "reg-names", reg_names, names_len);
 187                 off = fdt_node_offset_by_compatible(fdt, off,
 188                                                     "fsl,lx2160a-pcie");
 189         }
 190
 191         return 0;
 192 }
 193 #endif
 194
 195 #if defined(CONFIG_TARGET_LX2160AQDS) || defined(CONFIG_TARGET_LX2162AQDS)
 196 void esdhc_dspi_status_fixup(void *blob)
 197 {
 198         const char esdhc0_path[] = "/soc/esdhc@2140000";
 199         const char esdhc1_path[] = "/soc/esdhc@2150000";
 200         const char dspi0_path[] = "/soc/spi@2100000";
 201         const char dspi1_path[] = "/soc/spi@2110000";
 202         const char dspi2_path[] = "/soc/spi@2120000";
 203
 204         struct ccsr_gur __iomem *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR);
 205         u32 sdhc1_base_pmux;
 206         u32 sdhc2_base_pmux;
 207         u32 iic5_pmux;
 208
 209         /* Check RCW field sdhc1_base_pmux to enable/disable
 210          * esdhc0/dspi0 DT node
 211          */
 212         sdhc1_base_pmux = gur_in32(&gur->rcwsr[FSL_CHASSIS3_RCWSR12_REGSR - 1])
 213                 & FSL_CHASSIS3_SDHC1_BASE_PMUX_MASK;
 214         sdhc1_base_pmux >>= FSL_CHASSIS3_SDHC1_BASE_PMUX_SHIFT;
 215
 216         if (sdhc1_base_pmux == SDHC1_BASE_PMUX_DSPI) {
 217                 do_fixup_by_path(blob, dspi0_path, "status", "okay",
 218                                  sizeof("okay"), 1);
 219                 do_fixup_by_path(blob, esdhc0_path, "status", "disabled",
 220                                  sizeof("disabled"), 1);
 221         } else {
 222                 do_fixup_by_path(blob, esdhc0_path, "status", "okay",
 223                                  sizeof("okay"), 1);
 224                 do_fixup_by_path(blob, dspi0_path, "status", "disabled",
 225                                  sizeof("disabled"), 1);
 226         }
 227
 228         /* Check RCW field sdhc2_base_pmux to enable/disable
 229          * esdhc1/dspi1 DT node
 230          */
 231         sdhc2_base_pmux = gur_in32(&gur->rcwsr[FSL_CHASSIS3_RCWSR13_REGSR - 1])
 232                 & FSL_CHASSIS3_SDHC2_BASE_PMUX_MASK;
 233         sdhc2_base_pmux >>= FSL_CHASSIS3_SDHC2_BASE_PMUX_SHIFT;
 234
 235         if (sdhc2_base_pmux == SDHC2_BASE_PMUX_DSPI) {
 236                 do_fixup_by_path(blob, dspi1_path, "status", "okay",
 237                                  sizeof("okay"), 1);
 238                 do_fixup_by_path(blob, esdhc1_path, "status", "disabled",
 239                                  sizeof("disabled"), 1);
 240         } else {
 241                 do_fixup_by_path(blob, esdhc1_path, "status", "okay",
 242                                  sizeof("okay"), 1);
 243                 do_fixup_by_path(blob, dspi1_path, "status", "disabled",
 244                                  sizeof("disabled"), 1);
 245         }
 246
 247         /* Check RCW field IIC5 to enable dspi2 DT node */
 248         iic5_pmux = gur_in32(&gur->rcwsr[FSL_CHASSIS3_RCWSR12_REGSR - 1])
 249                 & FSL_CHASSIS3_IIC5_PMUX_MASK;
 250         iic5_pmux >>= FSL_CHASSIS3_IIC5_PMUX_SHIFT;
 251
 252         if (iic5_pmux == IIC5_PMUX_SPI3)
 253                 do_fixup_by_path(blob, dspi2_path, "status", "okay",
 254                                  sizeof("okay"), 1);
 255         else
 256                 do_fixup_by_path(blob, dspi2_path, "status", "disabled",
 257                                  sizeof("disabled"), 1);
 258 }
 259 #endif
 260
 261 int esdhc_status_fixup(void *blob, const char *compat)
 262 {
 263 #if defined(CONFIG_TARGET_LX2160AQDS) || defined(CONFIG_TARGET_LX2162AQDS)
 264         /* Enable esdhc and dspi DT nodes based on RCW fields */
 265         esdhc_dspi_status_fixup(blob);
 266 #else
 267         /* Enable both esdhc DT nodes for LX2160ARDB */
 268         do_fixup_by_compat(blob, compat, "status", "okay",
 269                            sizeof("okay"), 1);
 270 #endif
 271         return 0;
 272 }
 273
 274 #if defined(CONFIG_VID)
 275 int i2c_multiplexer_select_vid_channel(u8 channel)
 276 {
 277         return select_i2c_ch_pca9547(channel);
 278 }
 279
 280 int init_func_vid(void)
 281 {
 282         int set_vid;
 283
 284         if (IS_SVR_REV(get_svr(), 1, 0))
 285                 set_vid = adjust_vdd(800);
 286         else
 287                 set_vid = adjust_vdd(0);
 288
 289         if (set_vid < 0)
 290                 printf("core voltage not adjusted\n");
 291
 292         return 0;
 293 }
 294 #endif
 295
 296 int checkboard(void)
 297 {
 298         enum boot_src src = get_boot_src();
 299         char buf[64];
 300         u8 sw;
 301 #if defined(CONFIG_TARGET_LX2160AQDS) || defined(CONFIG_TARGET_LX2162AQDS)
 302         int clock;
 303         static const char *const freq[] = {"100", "125", "156.25",
 304                                            "161.13", "322.26", "", "", "",
 305                                            "", "", "", "", "", "", "",
 306                                            "100 separate SSCG"};
 307 #endif
 308
 309         cpu_name(buf);
 310 #if defined(CONFIG_TARGET_LX2160AQDS) || defined(CONFIG_TARGET_LX2162AQDS)
 311         printf("Board: %s-QDS, ", buf);
 312 #else
 313         printf("Board: %s-RDB, ", buf);
 314 #endif
 315
 316         sw = QIXIS_READ(arch);
 317         printf("Board version: %c, boot from ", (sw & 0xf) - 1 + 'A');
 318
 319         if (src == BOOT_SOURCE_SD_MMC) {
 320                 puts("SD\n");
 321         } else if (src == BOOT_SOURCE_SD_MMC2) {
 322                 puts("eMMC\n");
 323         } else {
 324                 sw = QIXIS_READ(brdcfg[0]);
 325                 sw = (sw >> QIXIS_XMAP_SHIFT) & QIXIS_XMAP_MASK;
 326                 switch (sw) {
 327                 case 0:
 328                 case 4:
 329                         puts("FlexSPI DEV#0\n");
 330                         break;
 331                 case 1:
 332                         puts("FlexSPI DEV#1\n");
 333                         break;
 334                 case 2:
 335                 case 3:
 336                         puts("FlexSPI EMU\n");
 337                         break;
 338                 default:
 339                         printf("invalid setting, xmap: %d\n", sw);
 340                         break;
 341                 }
 342         }
 343 #if defined(CONFIG_TARGET_LX2160ARDB)
 344         printf("FPGA: v%d.%d\n", QIXIS_READ(scver), QIXIS_READ(tagdata));
 345
 346         puts("SERDES1 Reference: Clock1 = 161.13MHz Clock2 = 161.13MHz\n");
 347         puts("SERDES2 Reference: Clock1 = 100MHz Clock2 = 100MHz\n");
 348         puts("SERDES3 Reference: Clock1 = 100MHz Clock2 = 100MHz\n");
 349 #else
 350         printf("FPGA: v%d (%s), build %d",
 351                (int)QIXIS_READ(scver), qixis_read_tag(buf),
 352                (int)qixis_read_minor());
 353         /* the timestamp string contains "\n" at the end */
 354         printf(" on %s", qixis_read_time(buf));
 355
 356         puts("SERDES1 Reference : ");
 357         sw = QIXIS_READ(brdcfg[2]);
 358         clock = sw >> 4;
 359         printf("Clock1 = %sMHz ", freq[clock]);
 360 #if defined(CONFIG_TARGET_LX2160AQDS)
 361         clock = sw & 0x0f;
 362         printf("Clock2 = %sMHz", freq[clock]);
 363 #endif
 364         sw = QIXIS_READ(brdcfg[3]);
 365         puts("\nSERDES2 Reference : ");
 366         clock = sw >> 4;
 367         printf("Clock1 = %sMHz ", freq[clock]);
 368         clock = sw & 0x0f;
 369         printf("Clock2 = %sMHz\n", freq[clock]);
 370 #if defined(CONFIG_TARGET_LX2160AQDS)
 371         sw = QIXIS_READ(brdcfg[12]);
 372         puts("SERDES3 Reference : ");
 373         clock = sw >> 4;
 374         printf("Clock1 = %sMHz Clock2 = %sMHz\n", freq[clock], freq[clock]);
 375 #endif
 376 #endif
 377         return 0;
 378 }
 379
 380 #if defined(CONFIG_TARGET_LX2160AQDS) || defined(CONFIG_TARGET_LX2162AQDS)
 381 /*
 382  * implementation of CONFIG_ESDHC_DETECT_QUIRK Macro.
 383  */
 384 u8 qixis_esdhc_detect_quirk(void)
 385 {
 386         /*
 387          * SDHC1 Card ID:
 388          * Specifies the type of card installed in the SDHC1 adapter slot.
 389          * 000= (reserved)
 390          * 001= eMMC V4.5 adapter is installed.
 391          * 010= SD/MMC 3.3V adapter is installed.
 392          * 011= eMMC V4.4 adapter is installed.
 393          * 100= eMMC V5.0 adapter is installed.
 394          * 101= MMC card/Legacy (3.3V) adapter is installed.
 395          * 110= SDCard V2/V3 adapter installed.
 396          * 111= no adapter is installed.
 397          */
 398         return ((QIXIS_READ(sdhc1) & QIXIS_SDID_MASK) !=
 399                  QIXIS_ESDHC_NO_ADAPTER);
 400 }
 401
 402 static void esdhc_adapter_card_ident(void)
 403 {
 404         u8 card_id, val;
 405
 406         val = QIXIS_READ(sdhc1);
 407         card_id = val & QIXIS_SDID_MASK;
 408
 409         switch (card_id) {
 410         case QIXIS_ESDHC_ADAPTER_TYPE_SD:
 411                 /* Power cycle to card */
 412                 val &= ~QIXIS_SDHC1_S1V3;
 413                 QIXIS_WRITE(sdhc1, val);
 414                 mdelay(1);
 415                 val |= QIXIS_SDHC1_S1V3;
 416                 QIXIS_WRITE(sdhc1, val);
 417                 /* Route to SDHC1_VS */
 418                 val = QIXIS_READ(brdcfg[11]);
 419                 val |= QIXIS_SDHC1_VS;
 420                 QIXIS_WRITE(brdcfg[11], val);
 421                 break;
 422         default:
 423                 break;
 424         }
 425 }
 426
 427 int config_board_mux(void)
 428 {
 429         u8 reg11, reg5, reg13;
 430         struct ccsr_gur __iomem *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR);
 431         u32 sdhc1_base_pmux;
 432         u32 sdhc2_base_pmux;
 433         u32 iic5_pmux;
 434
 435         /* Routes {I2C2_SCL, I2C2_SDA} to SDHC1 as {SDHC1_CD_B, SDHC1_WP}.
 436          * Routes {I2C3_SCL, I2C3_SDA} to CAN transceiver as {CAN1_TX,CAN1_RX}.
 437          * Routes {I2C4_SCL, I2C4_SDA} to CAN transceiver as {CAN2_TX,CAN2_RX}.
 438          * Qixis and remote systems are isolated from the I2C1 bus.
 439          * Processor connections are still available.
 440          * SPI2 CS2_B controls EN25S64 SPI memory device.
 441          * SPI3 CS2_B controls EN25S64 SPI memory device.
 442          * EC2 connects to PHY #2 using RGMII protocol.
 443          * CLK_OUT connects to FPGA for clock measurement.
 444          */
 445
 446         reg5 = QIXIS_READ(brdcfg[5]);
 447         reg5 = CFG_MUX_I2C_SDHC(reg5, 0x40);
 448         QIXIS_WRITE(brdcfg[5], reg5);
 449
 450         /* Check RCW field sdhc1_base_pmux
 451          * esdhc0 : sdhc1_base_pmux = 0
 452          * dspi0  : sdhc1_base_pmux = 2
 453          */
 454         sdhc1_base_pmux = gur_in32(&gur->rcwsr[FSL_CHASSIS3_RCWSR12_REGSR - 1])
 455                 & FSL_CHASSIS3_SDHC1_BASE_PMUX_MASK;
 456         sdhc1_base_pmux >>= FSL_CHASSIS3_SDHC1_BASE_PMUX_SHIFT;
 457
 458         if (sdhc1_base_pmux == SDHC1_BASE_PMUX_DSPI) {
 459                 reg11 = QIXIS_READ(brdcfg[11]);
 460                 reg11 = SET_CFG_MUX1_SDHC1_DSPI(reg11, 0x40);
 461                 QIXIS_WRITE(brdcfg[11], reg11);
 462         } else {
 463                 /* - Routes {SDHC1_CMD, SDHC1_CLK } to SDHC1 adapter slot.
 464                  *          {SDHC1_DAT3, SDHC1_DAT2} to SDHC1 adapter slot.
 465                  *          {SDHC1_DAT1, SDHC1_DAT0} to SDHC1 adapter slot.
 466                  */
 467                 reg11 = QIXIS_READ(brdcfg[11]);
 468                 reg11 = SET_CFG_MUX1_SDHC1_SDHC(reg11);
 469                 QIXIS_WRITE(brdcfg[11], reg11);
 470         }
 471
 472         /* Check RCW field sdhc2_base_pmux
 473          * esdhc1 : sdhc2_base_pmux = 0 (default)
 474          * dspi1  : sdhc2_base_pmux = 2
 475          */
 476         sdhc2_base_pmux = gur_in32(&gur->rcwsr[FSL_CHASSIS3_RCWSR13_REGSR - 1])
 477                 & FSL_CHASSIS3_SDHC2_BASE_PMUX_MASK;
 478         sdhc2_base_pmux >>= FSL_CHASSIS3_SDHC2_BASE_PMUX_SHIFT;
 479
 480         if (sdhc2_base_pmux == SDHC2_BASE_PMUX_DSPI) {
 481                 reg13 = QIXIS_READ(brdcfg[13]);
 482                 reg13 = SET_CFG_MUX_SDHC2_DSPI(reg13, 0x01);
 483                 QIXIS_WRITE(brdcfg[13], reg13);
 484         } else {
 485                 reg13 = QIXIS_READ(brdcfg[13]);
 486                 reg13 = SET_CFG_MUX_SDHC2_DSPI(reg13, 0x00);
 487                 QIXIS_WRITE(brdcfg[13], reg13);
 488         }
 489
 490         /* Check RCW field IIC5 to enable dspi2 DT nodei
 491          * dspi2: IIC5 = 3
 492          */
 493         iic5_pmux = gur_in32(&gur->rcwsr[FSL_CHASSIS3_RCWSR12_REGSR - 1])
 494                 & FSL_CHASSIS3_IIC5_PMUX_MASK;
 495         iic5_pmux >>= FSL_CHASSIS3_IIC5_PMUX_SHIFT;
 496
 497         if (iic5_pmux == IIC5_PMUX_SPI3) {
 498                 /* - Routes {SDHC1_DAT4} to SPI3 devices as {SPI3_M_CS0_B}. */
 499                 reg11 = QIXIS_READ(brdcfg[11]);
 500                 reg11 = SET_CFG_MUX2_SDHC1_SPI(reg11, 0x10);
 501                 QIXIS_WRITE(brdcfg[11], reg11);
 502
 503                 /* - Routes {SDHC1_DAT5, SDHC1_DAT6} nowhere.
 504                  * {SDHC1_DAT7, SDHC1_DS } to {nothing, SPI3_M0_CLK }.
 505                  * {I2C5_SCL, I2C5_SDA } to {SPI3_M0_MOSI, SPI3_M0_MISO}.
 506                  */
 507                 reg11 = QIXIS_READ(brdcfg[11]);
 508                 reg11 = SET_CFG_MUX3_SDHC1_SPI(reg11, 0x01);
 509                 QIXIS_WRITE(brdcfg[11], reg11);
 510         } else {
 511                 /*
 512                  * If {SDHC1_DAT4} has been configured to route to SDHC1_VS,
 513                  * do not change it.
 514                  * Otherwise route {SDHC1_DAT4} to SDHC1 adapter slot.
 515                  */
 516                 reg11 = QIXIS_READ(brdcfg[11]);
 517                 if ((reg11 & 0x30) != 0x30) {
 518                         reg11 = SET_CFG_MUX2_SDHC1_SPI(reg11, 0x00);
 519                         QIXIS_WRITE(brdcfg[11], reg11);
 520                 }
 521
 522                 /* - Routes {SDHC1_DAT5, SDHC1_DAT6} to SDHC1 adapter slot.
 523                  * {SDHC1_DAT7, SDHC1_DS } to SDHC1 adapter slot.
 524                  * {I2C5_SCL, I2C5_SDA } to SDHC1 adapter slot.
 525                  */
 526                 reg11 = QIXIS_READ(brdcfg[11]);
 527                 reg11 = SET_CFG_MUX3_SDHC1_SPI(reg11, 0x00);
 528                 QIXIS_WRITE(brdcfg[11], reg11);
 529         }
 530
 531         return 0;
 532 }
 533
 534 int board_early_init_r(void)
 535 {
 536         esdhc_adapter_card_ident();
 537         return 0;
 538 }
 539 #elif defined(CONFIG_TARGET_LX2160ARDB)
 540 int config_board_mux(void)
 541 {
 542         u8 brdcfg;
 543
 544         brdcfg = QIXIS_READ(brdcfg[4]);
 545         /* The BRDCFG4 register controls general board configuration.
 546          *|-------------------------------------------|
 547          *|Field  | Function                          |
 548          *|-------------------------------------------|
 549          *|5      | CAN I/O Enable (net CFG_CAN_EN_B):|
 550          *|CAN_EN | 0= CAN transceivers are disabled. |
 551          *|       | 1= CAN transceivers are enabled.  |
 552          *|-------------------------------------------|
 553          */
 554         brdcfg |= BIT_MASK(5);
 555         QIXIS_WRITE(brdcfg[4], brdcfg);
 556
 557         return 0;
 558 }
 559 #else
 560 int config_board_mux(void)
 561 {
 562         return 0;
 563 }
 564 #endif
 565
 566 unsigned long get_board_sys_clk(void)
 567 {
 568 #if defined(CONFIG_TARGET_LX2160AQDS) || defined(CONFIG_TARGET_LX2162AQDS)
 569         u8 sysclk_conf = QIXIS_READ(brdcfg[1]);
 570
 571         switch (sysclk_conf & 0x03) {
 572         case QIXIS_SYSCLK_100:
 573                 return 100000000;
 574         case QIXIS_SYSCLK_125:
 575                 return 125000000;
 576         case QIXIS_SYSCLK_133:
 577                 return 133333333;
 578         }
 579         return 100000000;
 580 #else
 581         return 100000000;
 582 #endif
 583 }
 584
 585 unsigned long get_board_ddr_clk(void)
 586 {
 587 #if defined(CONFIG_TARGET_LX2160AQDS) || defined(CONFIG_TARGET_LX2162AQDS)
 588         u8 ddrclk_conf = QIXIS_READ(brdcfg[1]);
 589
 590         switch ((ddrclk_conf & 0x30) >> 4) {
 591         case QIXIS_DDRCLK_100:
 592                 return 100000000;
 593         case QIXIS_DDRCLK_125:
 594                 return 125000000;
 595         case QIXIS_DDRCLK_133:
 596                 return 133333333;
 597         }
 598         return 100000000;
 599 #else
 600         return 100000000;
 601 #endif
 602 }
 603
 604 int board_init(void)
 605 {
 606 #if defined(CONFIG_FSL_MC_ENET) && defined(CONFIG_TARGET_LX2160ARDB)
 607         u32 __iomem *irq_ccsr = (u32 __iomem *)ISC_BASE;
 608 #endif
 609 #ifdef CONFIG_ENV_IS_NOWHERE
 610         gd->env_addr = (ulong)&default_environment[0];
 611 #endif
 612
 613         select_i2c_ch_pca9547(I2C_MUX_CH_DEFAULT);
 614
 615 #if defined(CONFIG_FSL_MC_ENET) && defined(CONFIG_TARGET_LX2160ARDB)
 616         /* invert AQR107 IRQ pins polarity */
 617         out_le32(irq_ccsr + IRQCR_OFFSET / 4, AQR107_IRQ_MASK);
 618 #endif
 619
 620 #ifdef CONFIG_FSL_CAAM
 621         sec_init();
 622 #endif
 623
 624 #if !defined(CONFIG_SYS_EARLY_PCI_INIT) && defined(CONFIG_DM_ETH)
 625         pci_init();
 626 #endif
 627         return 0;
 628 }
 629
 630 void detail_board_ddr_info(void)
 631 {
 632         int i;
 633         u64 ddr_size = 0;
 634
 635         puts("\nDDR    ");
 636         for (i = 0; i < CONFIG_NR_DRAM_BANKS; i++)
 637                 ddr_size += gd->bd->bi_dram[i].size;
 638         print_size(ddr_size, "");
 639         print_ddr_info(0);
 640 }
 641
 642 #ifdef CONFIG_MISC_INIT_R
 643 int misc_init_r(void)
 644 {
 645         config_board_mux();
 646
 647         return 0;
 648 }
 649 #endif
 650
 651 #ifdef CONFIG_FSL_MC_ENET
 652 extern int fdt_fixup_board_phy(void *fdt);
 653
 654 void fdt_fixup_board_enet(void *fdt)
 655 {
 656         int offset;
 657
 658         offset = fdt_path_offset(fdt, "/soc/fsl-mc");
 659
 660         if (offset < 0)
 661                 offset = fdt_path_offset(fdt, "/fsl-mc");
 662
 663         if (offset < 0) {
 664                 printf("%s: fsl-mc node not found in device tree (error %d)\n",
 665                        __func__, offset);
 666                 return;
 667         }
 668
 669         if (get_mc_boot_status() == 0 &&
 670             (is_lazy_dpl_addr_valid() || get_dpl_apply_status() == 0)) {
 671                 fdt_status_okay(fdt, offset);
 672 #ifndef CONFIG_DM_ETH
 673                 fdt_fixup_board_phy(fdt);
 674 #endif
 675         } else {
 676                 fdt_status_fail(fdt, offset);
 677         }
 678 }
 679
 680 void board_quiesce_devices(void)
 681 {
 682         fsl_mc_ldpaa_exit(gd->bd);
 683 }
 684 #endif
 685
 686 #ifdef CONFIG_OF_BOARD_SETUP
 687 int ft_board_setup(void *blob, struct bd_info *bd)
 688 {
 689         int i;
 690         u16 mc_memory_bank = 0;
 691
 692         u64 *base;
 693         u64 *size;
 694         u64 mc_memory_base = 0;
 695         u64 mc_memory_size = 0;
 696         u16 total_memory_banks;
 697
 698         ft_cpu_setup(blob, bd);
 699
 700         fdt_fixup_mc_ddr(&mc_memory_base, &mc_memory_size);
 701
 702         if (mc_memory_base != 0)
 703                 mc_memory_bank++;
 704
 705         total_memory_banks = CONFIG_NR_DRAM_BANKS + mc_memory_bank;
 706
 707         base = calloc(total_memory_banks, sizeof(u64));
 708         size = calloc(total_memory_banks, sizeof(u64));
 709
 710         /* fixup DT for the three GPP DDR banks */
 711         for (i = 0; i < CONFIG_NR_DRAM_BANKS; i++) {
 712                 base[i] = gd->bd->bi_dram[i].start;
 713                 size[i] = gd->bd->bi_dram[i].size;
 714         }
 715
 716 #ifdef CONFIG_RESV_RAM
 717         /* reduce size if reserved memory is within this bank */
 718         if (gd->arch.resv_ram >= base[0] &&
 719             gd->arch.resv_ram < base[0] + size[0])
 720                 size[0] = gd->arch.resv_ram - base[0];
 721         else if (gd->arch.resv_ram >= base[1] &&
 722                  gd->arch.resv_ram < base[1] + size[1])
 723                 size[1] = gd->arch.resv_ram - base[1];
 724         else if (gd->arch.resv_ram >= base[2] &&
 725                  gd->arch.resv_ram < base[2] + size[2])
 726                 size[2] = gd->arch.resv_ram - base[2];
 727 #endif
 728
 729         if (mc_memory_base != 0) {
 730                 for (i = 0; i <= total_memory_banks; i++) {
 731                         if (base[i] == 0 && size[i] == 0) {
 732                                 base[i] = mc_memory_base;
 733                                 size[i] = mc_memory_size;
 734                                 break;
 735                         }
 736                 }
 737         }
 738
 739         fdt_fixup_memory_banks(blob, base, size, total_memory_banks);
 740
 741 #ifdef CONFIG_USB
 742         fsl_fdt_fixup_dr_usb(blob, bd);
 743 #endif
 744
 745 #ifdef CONFIG_FSL_MC_ENET
 746         fdt_fsl_mc_fixup_iommu_map_entry(blob);
 747         fdt_fixup_board_enet(blob);
 748 #endif
 749         fdt_fixup_icid(blob);
 750
 751         return 0;
 752 }
 753 #endif
 754
 755 void qixis_dump_switch(void)
 756 {
 757         int i, nr_of_cfgsw;
 758
 759         QIXIS_WRITE(cms[0], 0x00);
 760         nr_of_cfgsw = QIXIS_READ(cms[1]);
 761
 762         puts("DIP switch settings dump:\n");
 763         for (i = 1; i <= nr_of_cfgsw; i++) {
 764                 QIXIS_WRITE(cms[0], i);
 765                 printf("SW%d = (0x%02x)\n", i, QIXIS_READ(cms[1]));
 766         }
 767 }