board/freescale/lx2160a/lx2160a.c

   1 // SPDX-License-Identifier: GPL-2.0+
   2 /*
   3  * Copyright 2018-2020 NXP
   4  */
   5
   6 #include <common.h>
   7 #include <clock_legacy.h>
   8 #include <dm.h>
   9 #include <init.h>
  10 #include <dm/platform_data/serial_pl01x.h>
  11 #include <i2c.h>
  12 #include <malloc.h>
  13 #include <errno.h>
  14 #include <netdev.h>
  15 #include <fsl_ddr.h>
  16 #include <fsl_sec.h>
  17 #include <asm/io.h>
  18 #include <fdt_support.h>
  19 #include <linux/libfdt.h>
  20 #include <fsl-mc/fsl_mc.h>
  21 #include <env_internal.h>
  22 #include <efi_loader.h>
  23 #include <asm/arch/mmu.h>
  24 #include <hwconfig.h>
  25 #include <asm/arch/clock.h>
  26 #include <asm/arch/config.h>
  27 #include <asm/arch/fsl_serdes.h>
  28 #include <asm/arch/soc.h>
  29 #include "../common/qixis.h"
  30 #include "../common/vid.h"
  31 #include <fsl_immap.h>
  32 #include <asm/arch-fsl-layerscape/fsl_icid.h>
  33
  34 #ifdef CONFIG_EMC2305
  35 #include "../common/emc2305.h"
  36 #endif
  37
  38 #ifdef CONFIG_TARGET_LX2160AQDS
  39 #define CFG_MUX_I2C_SDHC(reg, value)            ((reg & 0x3f) | value)
  40 #define SET_CFG_MUX1_SDHC1_SDHC(reg)            (reg & 0x3f)
  41 #define SET_CFG_MUX2_SDHC1_SPI(reg, value)      ((reg & 0xcf) | value)
  42 #define SET_CFG_MUX3_SDHC1_SPI(reg, value)      ((reg & 0xf8) | value)
  43 #define SET_CFG_MUX_SDHC2_DSPI(reg, value)      ((reg & 0xf8) | value)
  44 #define SET_CFG_MUX1_SDHC1_DSPI(reg, value)     ((reg & 0x3f) | value)
  45 #define SDHC1_BASE_PMUX_DSPI                    2
  46 #define SDHC2_BASE_PMUX_DSPI                    2
  47 #define IIC5_PMUX_SPI3                          3
  48 #endif /* CONFIG_TARGET_LX2160AQDS */
  49
  50 DECLARE_GLOBAL_DATA_PTR;
  51
  52 static struct pl01x_serial_platdata serial0 = {
  53 #if CONFIG_CONS_INDEX == 0
  54         .base = CONFIG_SYS_SERIAL0,
  55 #elif CONFIG_CONS_INDEX == 1
  56         .base = CONFIG_SYS_SERIAL1,
  57 #else
  58 #error "Unsupported console index value."
  59 #endif
  60         .type = TYPE_PL011,
  61 };
  62
  63 U_BOOT_DEVICE(nxp_serial0) = {
  64         .name = "serial_pl01x",
  65         .platdata = &serial0,
  66 };
  67
  68 static struct pl01x_serial_platdata serial1 = {
  69         .base = CONFIG_SYS_SERIAL1,
  70         .type = TYPE_PL011,
  71 };
  72
  73 U_BOOT_DEVICE(nxp_serial1) = {
  74         .name = "serial_pl01x",
  75         .platdata = &serial1,
  76 };
  77
  78 int select_i2c_ch_pca9547(u8 ch)
  79 {
  80         int ret;
  81
  82 #ifndef CONFIG_DM_I2C
  83         ret = i2c_write(I2C_MUX_PCA_ADDR_PRI, 0, 1, &ch, 1);
  84 #else
  85         struct udevice *dev;
  86
  87         ret = i2c_get_chip_for_busnum(0, I2C_MUX_PCA_ADDR_PRI, 1, &dev);
  88         if (!ret)
  89                 ret = dm_i2c_write(dev, 0, &ch, 1);
  90 #endif
  91         if (ret) {
  92                 puts("PCA: failed to select proper channel\n");
  93                 return ret;
  94         }
  95
  96         return 0;
  97 }
  98
  99 static void uart_get_clock(void)
 100 {
 101         serial0.clock = get_serial_clock();
 102         serial1.clock = get_serial_clock();
 103 }
 104
 105 int board_early_init_f(void)
 106 {
 107 #ifdef CONFIG_SYS_I2C_EARLY_INIT
 108         i2c_early_init_f();
 109 #endif
 110         /* get required clock for UART IP */
 111         uart_get_clock();
 112
 113 #ifdef CONFIG_EMC2305
 114         select_i2c_ch_pca9547(I2C_MUX_CH_EMC2305);
 115         emc2305_init();
 116         set_fan_speed(I2C_EMC2305_PWM);
 117         select_i2c_ch_pca9547(I2C_MUX_CH_DEFAULT);
 118 #endif
 119
 120         fsl_lsch3_early_init_f();
 121         return 0;
 122 }
 123
 124 #ifdef CONFIG_OF_BOARD_FIXUP
 125 int board_fix_fdt(void *fdt)
 126 {
 127         char *reg_names, *reg_name;
 128         int names_len, old_name_len, new_name_len, remaining_names_len;
 129         struct str_map {
 130                 char *old_str;
 131                 char *new_str;
 132         } reg_names_map[] = {
 133                 { "ccsr", "dbi" },
 134                 { "pf_ctrl", "ctrl" }
 135         };
 136         int off = -1, i = 0;
 137
 138         if (IS_SVR_REV(get_svr(), 1, 0))
 139                 return 0;
 140
 141         off = fdt_node_offset_by_compatible(fdt, -1, "fsl,lx2160a-pcie");
 142         while (off != -FDT_ERR_NOTFOUND) {
 143                 fdt_setprop(fdt, off, "compatible", "fsl,ls-pcie",
 144                             strlen("fsl,ls-pcie") + 1);
 145
 146                 reg_names = (char *)fdt_getprop(fdt, off, "reg-names",
 147                                                 &names_len);
 148                 if (!reg_names)
 149                         continue;
 150
 151                 reg_name = reg_names;
 152                 remaining_names_len = names_len - (reg_name - reg_names);
 153                 i = 0;
 154                 while ((i < ARRAY_SIZE(reg_names_map)) && remaining_names_len) {
 155                         old_name_len = strlen(reg_names_map[i].old_str);
 156                         new_name_len = strlen(reg_names_map[i].new_str);
 157                         if (memcmp(reg_name, reg_names_map[i].old_str,
 158                                    old_name_len) == 0) {
 159                                 /* first only leave required bytes for new_str
 160                                  * and copy rest of the string after it
 161                                  */
 162                                 memcpy(reg_name + new_name_len,
 163                                        reg_name + old_name_len,
 164                                        remaining_names_len - old_name_len);
 165                                 /* Now copy new_str */
 166                                 memcpy(reg_name, reg_names_map[i].new_str,
 167                                        new_name_len);
 168                                 names_len -= old_name_len;
 169                                 names_len += new_name_len;
 170                                 i++;
 171                         }
 172
 173                         reg_name = memchr(reg_name, '\0', remaining_names_len);
 174                         if (!reg_name)
 175                                 break;
 176
 177                         reg_name += 1;
 178
 179                         remaining_names_len = names_len -
 180                                               (reg_name - reg_names);
 181                 }
 182
 183                 fdt_setprop(fdt, off, "reg-names", reg_names, names_len);
 184                 off = fdt_node_offset_by_compatible(fdt, off,
 185                                                     "fsl,lx2160a-pcie");
 186         }
 187
 188         return 0;
 189 }
 190 #endif
 191
 192 #if defined(CONFIG_TARGET_LX2160AQDS)
 193 void esdhc_dspi_status_fixup(void *blob)
 194 {
 195         const char esdhc0_path[] = "/soc/esdhc@2140000";
 196         const char esdhc1_path[] = "/soc/esdhc@2150000";
 197         const char dspi0_path[] = "/soc/spi@2100000";
 198         const char dspi1_path[] = "/soc/spi@2110000";
 199         const char dspi2_path[] = "/soc/spi@2120000";
 200
 201         struct ccsr_gur __iomem *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR);
 202         u32 sdhc1_base_pmux;
 203         u32 sdhc2_base_pmux;
 204         u32 iic5_pmux;
 205
 206         /* Check RCW field sdhc1_base_pmux to enable/disable
 207          * esdhc0/dspi0 DT node
 208          */
 209         sdhc1_base_pmux = gur_in32(&gur->rcwsr[FSL_CHASSIS3_RCWSR12_REGSR - 1])
 210                 & FSL_CHASSIS3_SDHC1_BASE_PMUX_MASK;
 211         sdhc1_base_pmux >>= FSL_CHASSIS3_SDHC1_BASE_PMUX_SHIFT;
 212
 213         if (sdhc1_base_pmux == SDHC1_BASE_PMUX_DSPI) {
 214                 do_fixup_by_path(blob, dspi0_path, "status", "okay",
 215                                  sizeof("okay"), 1);
 216                 do_fixup_by_path(blob, esdhc0_path, "status", "disabled",
 217                                  sizeof("disabled"), 1);
 218         } else {
 219                 do_fixup_by_path(blob, esdhc0_path, "status", "okay",
 220                                  sizeof("okay"), 1);
 221                 do_fixup_by_path(blob, dspi0_path, "status", "disabled",
 222                                  sizeof("disabled"), 1);
 223         }
 224
 225         /* Check RCW field sdhc2_base_pmux to enable/disable
 226          * esdhc1/dspi1 DT node
 227          */
 228         sdhc2_base_pmux = gur_in32(&gur->rcwsr[FSL_CHASSIS3_RCWSR13_REGSR - 1])
 229                 & FSL_CHASSIS3_SDHC2_BASE_PMUX_MASK;
 230         sdhc2_base_pmux >>= FSL_CHASSIS3_SDHC2_BASE_PMUX_SHIFT;
 231
 232         if (sdhc2_base_pmux == SDHC2_BASE_PMUX_DSPI) {
 233                 do_fixup_by_path(blob, dspi1_path, "status", "okay",
 234                                  sizeof("okay"), 1);
 235                 do_fixup_by_path(blob, esdhc1_path, "status", "disabled",
 236                                  sizeof("disabled"), 1);
 237         } else {
 238                 do_fixup_by_path(blob, esdhc1_path, "status", "okay",
 239                                  sizeof("okay"), 1);
 240                 do_fixup_by_path(blob, dspi1_path, "status", "disabled",
 241                                  sizeof("disabled"), 1);
 242         }
 243
 244         /* Check RCW field IIC5 to enable dspi2 DT node */
 245         iic5_pmux = gur_in32(&gur->rcwsr[FSL_CHASSIS3_RCWSR12_REGSR - 1])
 246                 & FSL_CHASSIS3_IIC5_PMUX_MASK;
 247         iic5_pmux >>= FSL_CHASSIS3_IIC5_PMUX_SHIFT;
 248
 249         if (iic5_pmux == IIC5_PMUX_SPI3)
 250                 do_fixup_by_path(blob, dspi2_path, "status", "okay",
 251                                  sizeof("okay"), 1);
 252         else
 253                 do_fixup_by_path(blob, dspi2_path, "status", "disabled",
 254                                  sizeof("disabled"), 1);
 255 }
 256 #endif
 257
 258 int esdhc_status_fixup(void *blob, const char *compat)
 259 {
 260 #if defined(CONFIG_TARGET_LX2160AQDS)
 261         /* Enable esdhc and dspi DT nodes based on RCW fields */
 262         esdhc_dspi_status_fixup(blob);
 263 #else
 264         /* Enable both esdhc DT nodes for LX2160ARDB */
 265         do_fixup_by_compat(blob, compat, "status", "okay",
 266                            sizeof("okay"), 1);
 267 #endif
 268         return 0;
 269 }
 270
 271 #if defined(CONFIG_VID)
 272 int i2c_multiplexer_select_vid_channel(u8 channel)
 273 {
 274         return select_i2c_ch_pca9547(channel);
 275 }
 276
 277 int init_func_vid(void)
 278 {
 279         int set_vid;
 280
 281         if (IS_SVR_REV(get_svr(), 1, 0))
 282                 set_vid = adjust_vdd(800);
 283         else
 284                 set_vid = adjust_vdd(0);
 285
 286         if (set_vid < 0)
 287                 printf("core voltage not adjusted\n");
 288
 289         return 0;
 290 }
 291 #endif
 292
 293 int checkboard(void)
 294 {
 295         enum boot_src src = get_boot_src();
 296         char buf[64];
 297         u8 sw;
 298 #ifdef CONFIG_TARGET_LX2160AQDS
 299         int clock;
 300         static const char *const freq[] = {"100", "125", "156.25",
 301                                            "161.13", "322.26", "", "", "",
 302                                            "", "", "", "", "", "", "",
 303                                            "100 separate SSCG"};
 304 #endif
 305
 306         cpu_name(buf);
 307 #ifdef CONFIG_TARGET_LX2160AQDS
 308         printf("Board: %s-QDS, ", buf);
 309 #else
 310         printf("Board: %s-RDB, ", buf);
 311 #endif
 312
 313         sw = QIXIS_READ(arch);
 314         printf("Board version: %c, boot from ", (sw & 0xf) - 1 + 'A');
 315
 316         if (src == BOOT_SOURCE_SD_MMC) {
 317                 puts("SD\n");
 318         } else if (src == BOOT_SOURCE_SD_MMC2) {
 319                 puts("eMMC\n");
 320         } else {
 321                 sw = QIXIS_READ(brdcfg[0]);
 322                 sw = (sw >> QIXIS_XMAP_SHIFT) & QIXIS_XMAP_MASK;
 323                 switch (sw) {
 324                 case 0:
 325                 case 4:
 326                         puts("FlexSPI DEV#0\n");
 327                         break;
 328                 case 1:
 329                         puts("FlexSPI DEV#1\n");
 330                         break;
 331                 case 2:
 332                 case 3:
 333                         puts("FlexSPI EMU\n");
 334                         break;
 335                 default:
 336                         printf("invalid setting, xmap: %d\n", sw);
 337                         break;
 338                 }
 339         }
 340 #ifdef CONFIG_TARGET_LX2160AQDS
 341         printf("FPGA: v%d (%s), build %d",
 342                (int)QIXIS_READ(scver), qixis_read_tag(buf),
 343                (int)qixis_read_minor());
 344         /* the timestamp string contains "\n" at the end */
 345         printf(" on %s", qixis_read_time(buf));
 346
 347         puts("SERDES1 Reference : ");
 348         sw = QIXIS_READ(brdcfg[2]);
 349         clock = sw >> 4;
 350         printf("Clock1 = %sMHz ", freq[clock]);
 351         clock = sw & 0x0f;
 352         printf("Clock2 = %sMHz", freq[clock]);
 353
 354         sw = QIXIS_READ(brdcfg[3]);
 355         puts("\nSERDES2 Reference : ");
 356         clock = sw >> 4;
 357         printf("Clock1 = %sMHz ", freq[clock]);
 358         clock = sw & 0x0f;
 359         printf("Clock2 = %sMHz", freq[clock]);
 360
 361         sw = QIXIS_READ(brdcfg[12]);
 362         puts("\nSERDES3 Reference : ");
 363         clock = sw >> 4;
 364         printf("Clock1 = %sMHz Clock2 = %sMHz\n", freq[clock], freq[clock]);
 365 #else
 366         printf("FPGA: v%d.%d\n", QIXIS_READ(scver), QIXIS_READ(tagdata));
 367
 368         puts("SERDES1 Reference: Clock1 = 161.13MHz Clock2 = 161.13MHz\n");
 369         puts("SERDES2 Reference: Clock1 = 100MHz Clock2 = 100MHz\n");
 370         puts("SERDES3 Reference: Clock1 = 100MHz Clock2 = 100MHz\n");
 371 #endif
 372         return 0;
 373 }
 374
 375 #ifdef CONFIG_TARGET_LX2160AQDS
 376 /*
 377  * implementation of CONFIG_ESDHC_DETECT_QUIRK Macro.
 378  */
 379 u8 qixis_esdhc_detect_quirk(void)
 380 {
 381         /* for LX2160AQDS res1[1] @ offset 0x1A is SDHC1 Control/Status (SDHC1)
 382          * SDHC1 Card ID:
 383          * Specifies the type of card installed in the SDHC1 adapter slot.
 384          * 000= (reserved)
 385          * 001= eMMC V4.5 adapter is installed.
 386          * 010= SD/MMC 3.3V adapter is installed.
 387          * 011= eMMC V4.4 adapter is installed.
 388          * 100= eMMC V5.0 adapter is installed.
 389          * 101= MMC card/Legacy (3.3V) adapter is installed.
 390          * 110= SDCard V2/V3 adapter installed.
 391          * 111= no adapter is installed.
 392          */
 393         return ((QIXIS_READ(res1[1]) & QIXIS_SDID_MASK) !=
 394                  QIXIS_ESDHC_NO_ADAPTER);
 395 }
 396
 397 int config_board_mux(void)
 398 {
 399         u8 reg11, reg5, reg13;
 400         struct ccsr_gur __iomem *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR);
 401         u32 sdhc1_base_pmux;
 402         u32 sdhc2_base_pmux;
 403         u32 iic5_pmux;
 404
 405         /* Routes {I2C2_SCL, I2C2_SDA} to SDHC1 as {SDHC1_CD_B, SDHC1_WP}.
 406          * Routes {I2C3_SCL, I2C3_SDA} to CAN transceiver as {CAN1_TX,CAN1_RX}.
 407          * Routes {I2C4_SCL, I2C4_SDA} to CAN transceiver as {CAN2_TX,CAN2_RX}.
 408          * Qixis and remote systems are isolated from the I2C1 bus.
 409          * Processor connections are still available.
 410          * SPI2 CS2_B controls EN25S64 SPI memory device.
 411          * SPI3 CS2_B controls EN25S64 SPI memory device.
 412          * EC2 connects to PHY #2 using RGMII protocol.
 413          * CLK_OUT connects to FPGA for clock measurement.
 414          */
 415
 416         reg5 = QIXIS_READ(brdcfg[5]);
 417         reg5 = CFG_MUX_I2C_SDHC(reg5, 0x40);
 418         QIXIS_WRITE(brdcfg[5], reg5);
 419
 420         /* Check RCW field sdhc1_base_pmux
 421          * esdhc0 : sdhc1_base_pmux = 0
 422          * dspi0  : sdhc1_base_pmux = 2
 423          */
 424         sdhc1_base_pmux = gur_in32(&gur->rcwsr[FSL_CHASSIS3_RCWSR12_REGSR - 1])
 425                 & FSL_CHASSIS3_SDHC1_BASE_PMUX_MASK;
 426         sdhc1_base_pmux >>= FSL_CHASSIS3_SDHC1_BASE_PMUX_SHIFT;
 427
 428         if (sdhc1_base_pmux == SDHC1_BASE_PMUX_DSPI) {
 429                 reg11 = QIXIS_READ(brdcfg[11]);
 430                 reg11 = SET_CFG_MUX1_SDHC1_DSPI(reg11, 0x40);
 431                 QIXIS_WRITE(brdcfg[11], reg11);
 432         } else {
 433                 /* - Routes {SDHC1_CMD, SDHC1_CLK } to SDHC1 adapter slot.
 434                  *          {SDHC1_DAT3, SDHC1_DAT2} to SDHC1 adapter slot.
 435                  *          {SDHC1_DAT1, SDHC1_DAT0} to SDHC1 adapter slot.
 436                  */
 437                 reg11 = QIXIS_READ(brdcfg[11]);
 438                 reg11 = SET_CFG_MUX1_SDHC1_SDHC(reg11);
 439                 QIXIS_WRITE(brdcfg[11], reg11);
 440         }
 441
 442         /* Check RCW field sdhc2_base_pmux
 443          * esdhc1 : sdhc2_base_pmux = 0 (default)
 444          * dspi1  : sdhc2_base_pmux = 2
 445          */
 446         sdhc2_base_pmux = gur_in32(&gur->rcwsr[FSL_CHASSIS3_RCWSR13_REGSR - 1])
 447                 & FSL_CHASSIS3_SDHC2_BASE_PMUX_MASK;
 448         sdhc2_base_pmux >>= FSL_CHASSIS3_SDHC2_BASE_PMUX_SHIFT;
 449
 450         if (sdhc2_base_pmux == SDHC2_BASE_PMUX_DSPI) {
 451                 reg13 = QIXIS_READ(brdcfg[13]);
 452                 reg13 = SET_CFG_MUX_SDHC2_DSPI(reg13, 0x01);
 453                 QIXIS_WRITE(brdcfg[13], reg13);
 454         } else {
 455                 reg13 = QIXIS_READ(brdcfg[13]);
 456                 reg13 = SET_CFG_MUX_SDHC2_DSPI(reg13, 0x00);
 457                 QIXIS_WRITE(brdcfg[13], reg13);
 458         }
 459
 460         /* Check RCW field IIC5 to enable dspi2 DT nodei
 461          * dspi2: IIC5 = 3
 462          */
 463         iic5_pmux = gur_in32(&gur->rcwsr[FSL_CHASSIS3_RCWSR12_REGSR - 1])
 464                 & FSL_CHASSIS3_IIC5_PMUX_MASK;
 465         iic5_pmux >>= FSL_CHASSIS3_IIC5_PMUX_SHIFT;
 466
 467         if (iic5_pmux == IIC5_PMUX_SPI3) {
 468                 /* - Routes {SDHC1_DAT4} to SPI3 devices as {SPI3_M_CS0_B}. */
 469                 reg11 = QIXIS_READ(brdcfg[11]);
 470                 reg11 = SET_CFG_MUX2_SDHC1_SPI(reg11, 0x10);
 471                 QIXIS_WRITE(brdcfg[11], reg11);
 472
 473                 /* - Routes {SDHC1_DAT5, SDHC1_DAT6} nowhere.
 474                  * {SDHC1_DAT7, SDHC1_DS } to {nothing, SPI3_M0_CLK }.
 475                  * {I2C5_SCL, I2C5_SDA } to {SPI3_M0_MOSI, SPI3_M0_MISO}.
 476                  */
 477                 reg11 = QIXIS_READ(brdcfg[11]);
 478                 reg11 = SET_CFG_MUX3_SDHC1_SPI(reg11, 0x01);
 479                 QIXIS_WRITE(brdcfg[11], reg11);
 480         } else {
 481                 /*
 482                  * If {SDHC1_DAT4} has been configured to route to SDHC1_VS,
 483                  * do not change it.
 484                  * Otherwise route {SDHC1_DAT4} to SDHC1 adapter slot.
 485                  */
 486                 reg11 = QIXIS_READ(brdcfg[11]);
 487                 if ((reg11 & 0x30) != 0x30) {
 488                         reg11 = SET_CFG_MUX2_SDHC1_SPI(reg11, 0x00);
 489                         QIXIS_WRITE(brdcfg[11], reg11);
 490                 }
 491
 492                 /* - Routes {SDHC1_DAT5, SDHC1_DAT6} to SDHC1 adapter slot.
 493                  * {SDHC1_DAT7, SDHC1_DS } to SDHC1 adapter slot.
 494                  * {I2C5_SCL, I2C5_SDA } to SDHC1 adapter slot.
 495                  */
 496                 reg11 = QIXIS_READ(brdcfg[11]);
 497                 reg11 = SET_CFG_MUX3_SDHC1_SPI(reg11, 0x00);
 498                 QIXIS_WRITE(brdcfg[11], reg11);
 499         }
 500
 501         return 0;
 502 }
 503 #elif defined(CONFIG_TARGET_LX2160ARDB)
 504 int config_board_mux(void)
 505 {
 506         u8 brdcfg;
 507
 508         brdcfg = QIXIS_READ(brdcfg[4]);
 509         /* The BRDCFG4 register controls general board configuration.
 510          *|-------------------------------------------|
 511          *|Field  | Function                          |
 512          *|-------------------------------------------|
 513          *|5      | CAN I/O Enable (net CFG_CAN_EN_B):|
 514          *|CAN_EN | 0= CAN transceivers are disabled. |
 515          *|       | 1= CAN transceivers are enabled.  |
 516          *|-------------------------------------------|
 517          */
 518         brdcfg |= BIT_MASK(5);
 519         QIXIS_WRITE(brdcfg[4], brdcfg);
 520
 521         return 0;
 522 }
 523 #else
 524 int config_board_mux(void)
 525 {
 526         return 0;
 527 }
 528 #endif
 529
 530 unsigned long get_board_sys_clk(void)
 531 {
 532 #ifdef CONFIG_TARGET_LX2160AQDS
 533         u8 sysclk_conf = QIXIS_READ(brdcfg[1]);
 534
 535         switch (sysclk_conf & 0x03) {
 536         case QIXIS_SYSCLK_100:
 537                 return 100000000;
 538         case QIXIS_SYSCLK_125:
 539                 return 125000000;
 540         case QIXIS_SYSCLK_133:
 541                 return 133333333;
 542         }
 543         return 100000000;
 544 #else
 545         return 100000000;
 546 #endif
 547 }
 548
 549 unsigned long get_board_ddr_clk(void)
 550 {
 551 #ifdef CONFIG_TARGET_LX2160AQDS
 552         u8 ddrclk_conf = QIXIS_READ(brdcfg[1]);
 553
 554         switch ((ddrclk_conf & 0x30) >> 4) {
 555         case QIXIS_DDRCLK_100:
 556                 return 100000000;
 557         case QIXIS_DDRCLK_125:
 558                 return 125000000;
 559         case QIXIS_DDRCLK_133:
 560                 return 133333333;
 561         }
 562         return 100000000;
 563 #else
 564         return 100000000;
 565 #endif
 566 }
 567
 568 int board_init(void)
 569 {
 570 #if defined(CONFIG_FSL_MC_ENET) && defined(CONFIG_TARGET_LX2160ARDB)
 571         u32 __iomem *irq_ccsr = (u32 __iomem *)ISC_BASE;
 572 #endif
 573 #ifdef CONFIG_ENV_IS_NOWHERE
 574         gd->env_addr = (ulong)&default_environment[0];
 575 #endif
 576
 577         select_i2c_ch_pca9547(I2C_MUX_CH_DEFAULT);
 578
 579 #if defined(CONFIG_FSL_MC_ENET) && defined(CONFIG_TARGET_LX2160ARDB)
 580         /* invert AQR107 IRQ pins polarity */
 581         out_le32(irq_ccsr + IRQCR_OFFSET / 4, AQR107_IRQ_MASK);
 582 #endif
 583
 584 #ifdef CONFIG_FSL_CAAM
 585         sec_init();
 586 #endif
 587
 588         return 0;
 589 }
 590
 591 void detail_board_ddr_info(void)
 592 {
 593         int i;
 594         u64 ddr_size = 0;
 595
 596         puts("\nDDR    ");
 597         for (i = 0; i < CONFIG_NR_DRAM_BANKS; i++)
 598                 ddr_size += gd->bd->bi_dram[i].size;
 599         print_size(ddr_size, "");
 600         print_ddr_info(0);
 601 }
 602
 603 #ifdef CONFIG_MISC_INIT_R
 604 int misc_init_r(void)
 605 {
 606         config_board_mux();
 607
 608         return 0;
 609 }
 610 #endif
 611
 612 #ifdef CONFIG_FSL_MC_ENET
 613 extern int fdt_fixup_board_phy(void *fdt);
 614
 615 void fdt_fixup_board_enet(void *fdt)
 616 {
 617         int offset;
 618
 619         offset = fdt_path_offset(fdt, "/soc/fsl-mc");
 620
 621         if (offset < 0)
 622                 offset = fdt_path_offset(fdt, "/fsl-mc");
 623
 624         if (offset < 0) {
 625                 printf("%s: fsl-mc node not found in device tree (error %d)\n",
 626                        __func__, offset);
 627                 return;
 628         }
 629
 630         if (get_mc_boot_status() == 0 &&
 631             (is_lazy_dpl_addr_valid() || get_dpl_apply_status() == 0)) {
 632                 fdt_status_okay(fdt, offset);
 633                 fdt_fixup_board_phy(fdt);
 634         } else {
 635                 fdt_status_fail(fdt, offset);
 636         }
 637 }
 638
 639 void board_quiesce_devices(void)
 640 {
 641         fsl_mc_ldpaa_exit(gd->bd);
 642 }
 643 #endif
 644
 645 #ifdef CONFIG_OF_BOARD_SETUP
 646 int ft_board_setup(void *blob, bd_t *bd)
 647 {
 648         int i;
 649         u16 mc_memory_bank = 0;
 650
 651         u64 *base;
 652         u64 *size;
 653         u64 mc_memory_base = 0;
 654         u64 mc_memory_size = 0;
 655         u16 total_memory_banks;
 656
 657         ft_cpu_setup(blob, bd);
 658
 659         fdt_fixup_mc_ddr(&mc_memory_base, &mc_memory_size);
 660
 661         if (mc_memory_base != 0)
 662                 mc_memory_bank++;
 663
 664         total_memory_banks = CONFIG_NR_DRAM_BANKS + mc_memory_bank;
 665
 666         base = calloc(total_memory_banks, sizeof(u64));
 667         size = calloc(total_memory_banks, sizeof(u64));
 668
 669         /* fixup DT for the three GPP DDR banks */
 670         for (i = 0; i < CONFIG_NR_DRAM_BANKS; i++) {
 671                 base[i] = gd->bd->bi_dram[i].start;
 672                 size[i] = gd->bd->bi_dram[i].size;
 673         }
 674
 675 #ifdef CONFIG_RESV_RAM
 676         /* reduce size if reserved memory is within this bank */
 677         if (gd->arch.resv_ram >= base[0] &&
 678             gd->arch.resv_ram < base[0] + size[0])
 679                 size[0] = gd->arch.resv_ram - base[0];
 680         else if (gd->arch.resv_ram >= base[1] &&
 681                  gd->arch.resv_ram < base[1] + size[1])
 682                 size[1] = gd->arch.resv_ram - base[1];
 683         else if (gd->arch.resv_ram >= base[2] &&
 684                  gd->arch.resv_ram < base[2] + size[2])
 685                 size[2] = gd->arch.resv_ram - base[2];
 686 #endif
 687
 688         if (mc_memory_base != 0) {
 689                 for (i = 0; i <= total_memory_banks; i++) {
 690                         if (base[i] == 0 && size[i] == 0) {
 691                                 base[i] = mc_memory_base;
 692                                 size[i] = mc_memory_size;
 693                                 break;
 694                         }
 695                 }
 696         }
 697
 698         fdt_fixup_memory_banks(blob, base, size, total_memory_banks);
 699
 700 #ifdef CONFIG_USB
 701         fsl_fdt_fixup_dr_usb(blob, bd);
 702 #endif
 703
 704 #ifdef CONFIG_FSL_MC_ENET
 705         fdt_fsl_mc_fixup_iommu_map_entry(blob);
 706         fdt_fixup_board_enet(blob);
 707 #endif
 708         fdt_fixup_icid(blob);
 709
 710         return 0;
 711 }
 712 #endif
 713
 714 void qixis_dump_switch(void)
 715 {
 716         int i, nr_of_cfgsw;
 717
 718         QIXIS_WRITE(cms[0], 0x00);
 719         nr_of_cfgsw = QIXIS_READ(cms[1]);
 720
 721         puts("DIP switch settings dump:\n");
 722         for (i = 1; i <= nr_of_cfgsw; i++) {
 723                 QIXIS_WRITE(cms[0], i);
 724                 printf("SW%d = (0x%02x)\n", i, QIXIS_READ(cms[1]));
 725         }
 726 }