board/freescale/lx2160a/lx2160a.c

   1 // SPDX-License-Identifier: GPL-2.0+
   2 /*
   3  * Copyright 2018 NXP
   4  */
   5
   6 #include <common.h>
   7 #include <dm.h>
   8 #include <dm/platform_data/serial_pl01x.h>
   9 #include <i2c.h>
  10 #include <malloc.h>
  11 #include <errno.h>
  12 #include <netdev.h>
  13 #include <fsl_ddr.h>
  14 #include <fsl_sec.h>
  15 #include <asm/io.h>
  16 #include <fdt_support.h>
  17 #include <linux/libfdt.h>
  18 #include <fsl-mc/fsl_mc.h>
  19 #include <environment.h>
  20 #include <efi_loader.h>
  21 #include <asm/arch/mmu.h>
  22 #include <hwconfig.h>
  23 #include <asm/arch/fsl_serdes.h>
  24 #include <asm/arch/soc.h>
  25 #include "../common/qixis.h"
  26 #include "../common/vid.h"
  27 #include <fsl_immap.h>
  28
  29 DECLARE_GLOBAL_DATA_PTR;
  30
  31 static struct pl01x_serial_platdata serial0 = {
  32 #if CONFIG_CONS_INDEX == 0
  33         .base = CONFIG_SYS_SERIAL0,
  34 #elif CONFIG_CONS_INDEX == 1
  35         .base = CONFIG_SYS_SERIAL1,
  36 #else
  37 #error "Unsupported console index value."
  38 #endif
  39         .type = TYPE_PL011,
  40 };
  41
  42 U_BOOT_DEVICE(nxp_serial0) = {
  43         .name = "serial_pl01x",
  44         .platdata = &serial0,
  45 };
  46
  47 static struct pl01x_serial_platdata serial1 = {
  48         .base = CONFIG_SYS_SERIAL1,
  49         .type = TYPE_PL011,
  50 };
  51
  52 U_BOOT_DEVICE(nxp_serial1) = {
  53         .name = "serial_pl01x",
  54         .platdata = &serial1,
  55 };
  56
  57 int select_i2c_ch_pca9547(u8 ch)
  58 {
  59         int ret;
  60
  61         ret = i2c_write(I2C_MUX_PCA_ADDR_PRI, 0, 1, &ch, 1);
  62         if (ret) {
  63                 puts("PCA: failed to select proper channel\n");
  64                 return ret;
  65         }
  66
  67         return 0;
  68 }
  69
  70 static void uart_get_clock(void)
  71 {
  72         serial0.clock = get_serial_clock();
  73         serial1.clock = get_serial_clock();
  74 }
  75
  76 int board_early_init_f(void)
  77 {
  78 #ifdef CONFIG_SYS_I2C_EARLY_INIT
  79         i2c_early_init_f();
  80 #endif
  81         /* get required clock for UART IP */
  82         uart_get_clock();
  83
  84         fsl_lsch3_early_init_f();
  85         return 0;
  86 }
  87
  88 int esdhc_status_fixup(void *blob, const char *compat)
  89 {
  90         /* Enable both esdhc DT nodes for LX2160ARDB */
  91         do_fixup_by_compat(blob, compat, "status", "okay",
  92                            sizeof("okay"), 1);
  93
  94         return 0;
  95 }
  96
  97 #if defined(CONFIG_VID)
  98 int i2c_multiplexer_select_vid_channel(u8 channel)
  99 {
 100         return select_i2c_ch_pca9547(channel);
 101 }
 102
 103 #endif
 104
 105 int checkboard(void)
 106 {
 107         enum boot_src src = get_boot_src();
 108         char buf[64];
 109         u8 sw;
 110
 111         cpu_name(buf);
 112         printf("Board: %s-RDB, ", buf);
 113
 114         sw = QIXIS_READ(arch);
 115         printf("Board version: %c, boot from ", (sw & 0xf) - 1 + 'A');
 116
 117         if (src == BOOT_SOURCE_SD_MMC) {
 118                 puts("SD\n");
 119         } else {
 120                 sw = QIXIS_READ(brdcfg[0]);
 121                 sw = (sw >> QIXIS_XMAP_SHIFT) & QIXIS_XMAP_MASK;
 122                 switch (sw) {
 123                 case 0:
 124                 case 4:
 125                         puts("FlexSPI DEV#0\n");
 126                         break;
 127                 case 1:
 128                         puts("FlexSPI DEV#1\n");
 129                         break;
 130                 case 2:
 131                 case 3:
 132                         puts("FlexSPI EMU\n");
 133                         break;
 134                 default:
 135                         printf("invalid setting, xmap: %d\n", sw);
 136                         break;
 137                 }
 138         }
 139         printf("FPGA: v%d.%d\n", QIXIS_READ(scver), QIXIS_READ(tagdata));
 140
 141         puts("SERDES1 Reference: Clock1 = 161.13MHz Clock2 = 161.13MHz\n");
 142         puts("SERDES2 Reference: Clock1 = 100MHz Clock2 = 100MHz\n");
 143         puts("SERDES3 Reference: Clock1 = 100MHz Clock2 = 100Hz\n");
 144         return 0;
 145 }
 146
 147 unsigned long get_board_sys_clk(void)
 148 {
 149         return 100000000;
 150 }
 151
 152 unsigned long get_board_ddr_clk(void)
 153 {
 154         return 100000000;
 155 }
 156
 157 int board_init(void)
 158 {
 159 #ifdef CONFIG_ENV_IS_NOWHERE
 160         gd->env_addr = (ulong)&default_environment[0];
 161 #endif
 162
 163         select_i2c_ch_pca9547(I2C_MUX_CH_DEFAULT);
 164
 165 #ifdef CONFIG_FSL_CAAM
 166         sec_init();
 167 #endif
 168
 169         return 0;
 170 }
 171
 172 void detail_board_ddr_info(void)
 173 {
 174         int i;
 175         u64 ddr_size = 0;
 176
 177         puts("\nDDR    ");
 178         for (i = 0; i < CONFIG_NR_DRAM_BANKS; i++)
 179                 ddr_size += gd->bd->bi_dram[i].size;
 180         print_size(ddr_size, "");
 181         print_ddr_info(0);
 182 }
 183
 184 #if defined(CONFIG_ARCH_MISC_INIT)
 185 int arch_misc_init(void)
 186 {
 187         return 0;
 188 }
 189 #endif
 190
 191 #ifdef CONFIG_FSL_MC_ENET
 192 extern int fdt_fixup_board_phy(void *fdt);
 193
 194 void fdt_fixup_board_enet(void *fdt)
 195 {
 196         int offset;
 197
 198         offset = fdt_path_offset(fdt, "/soc/fsl-mc");
 199
 200         if (offset < 0)
 201                 offset = fdt_path_offset(fdt, "/fsl-mc");
 202
 203         if (offset < 0) {
 204                 printf("%s: fsl-mc node not found in device tree (error %d)\n",
 205                        __func__, offset);
 206                 return;
 207         }
 208
 209         if ((get_mc_boot_status() == 0) && (get_dpl_apply_status() == 0)) {
 210                 fdt_status_okay(fdt, offset);
 211                 fdt_fixup_board_phy(fdt);
 212         } else {
 213                 fdt_status_fail(fdt, offset);
 214         }
 215 }
 216
 217 void board_quiesce_devices(void)
 218 {
 219         fsl_mc_ldpaa_exit(gd->bd);
 220 }
 221 #endif
 222
 223 #ifdef CONFIG_OF_BOARD_SETUP
 224
 225 int ft_board_setup(void *blob, bd_t *bd)
 226 {
 227         int i;
 228         u64 base[CONFIG_NR_DRAM_BANKS];
 229         u64 size[CONFIG_NR_DRAM_BANKS];
 230
 231         ft_cpu_setup(blob, bd);
 232
 233         /* fixup DT for the three GPP DDR banks */
 234         for (i = 0; i < CONFIG_NR_DRAM_BANKS; i++) {
 235                 base[i] = gd->bd->bi_dram[i].start;
 236                 size[i] = gd->bd->bi_dram[i].size;
 237         }
 238
 239 #ifdef CONFIG_RESV_RAM
 240         /* reduce size if reserved memory is within this bank */
 241         if (gd->arch.resv_ram >= base[0] &&
 242             gd->arch.resv_ram < base[0] + size[0])
 243                 size[0] = gd->arch.resv_ram - base[0];
 244         else if (gd->arch.resv_ram >= base[1] &&
 245                  gd->arch.resv_ram < base[1] + size[1])
 246                 size[1] = gd->arch.resv_ram - base[1];
 247         else if (gd->arch.resv_ram >= base[2] &&
 248                  gd->arch.resv_ram < base[2] + size[2])
 249                 size[2] = gd->arch.resv_ram - base[2];
 250 #endif
 251
 252         fdt_fixup_memory_banks(blob, base, size, CONFIG_NR_DRAM_BANKS);
 253
 254 #ifdef CONFIG_USB
 255         fsl_fdt_fixup_dr_usb(blob, bd);
 256 #endif
 257
 258 #ifdef CONFIG_FSL_MC_ENET
 259         fdt_fsl_mc_fixup_iommu_map_entry(blob);
 260         fdt_fixup_board_enet(blob);
 261 #endif
 262
 263         return 0;
 264 }
 265 #endif
 266
 267 void qixis_dump_switch(void)
 268 {
 269         int i, nr_of_cfgsw;
 270
 271         QIXIS_WRITE(cms[0], 0x00);
 272         nr_of_cfgsw = QIXIS_READ(cms[1]);
 273
 274         puts("DIP switch settings dump:\n");
 275         for (i = 1; i <= nr_of_cfgsw; i++) {
 276                 QIXIS_WRITE(cms[0], i);
 277                 printf("SW%d = (0x%02x)\n", i, QIXIS_READ(cms[1]));
 278         }
 279 }