board/freescale/lx2160a/lx2160a.c

   1 // SPDX-License-Identifier: GPL-2.0+
   2 /*
   3  * Copyright 2018-2020 NXP
   4  */
   5
   6 #include <common.h>
   7 #include <clock_legacy.h>
   8 #include <dm.h>
   9 #include <dm/platform_data/serial_pl01x.h>
  10 #include <i2c.h>
  11 #include <malloc.h>
  12 #include <errno.h>
  13 #include <netdev.h>
  14 #include <fsl_ddr.h>
  15 #include <fsl_sec.h>
  16 #include <asm/io.h>
  17 #include <fdt_support.h>
  18 #include <linux/libfdt.h>
  19 #include <fsl-mc/fsl_mc.h>
  20 #include <env_internal.h>
  21 #include <efi_loader.h>
  22 #include <asm/arch/mmu.h>
  23 #include <hwconfig.h>
  24 #include <asm/arch/clock.h>
  25 #include <asm/arch/config.h>
  26 #include <asm/arch/fsl_serdes.h>
  27 #include <asm/arch/soc.h>
  28 #include "../common/qixis.h"
  29 #include "../common/vid.h"
  30 #include <fsl_immap.h>
  31 #include <asm/arch-fsl-layerscape/fsl_icid.h>
  32
  33 #ifdef CONFIG_EMC2305
  34 #include "../common/emc2305.h"
  35 #endif
  36
  37 #ifdef CONFIG_TARGET_LX2160AQDS
  38 #define CFG_MUX_I2C_SDHC(reg, value)            ((reg & 0x3f) | value)
  39 #define SET_CFG_MUX1_SDHC1_SDHC(reg)            (reg & 0x3f)
  40 #define SET_CFG_MUX2_SDHC1_SPI(reg, value)      ((reg & 0xcf) | value)
  41 #define SET_CFG_MUX3_SDHC1_SPI(reg, value)      ((reg & 0xf8) | value)
  42 #define SET_CFG_MUX_SDHC2_DSPI(reg, value)      ((reg & 0xf8) | value)
  43 #define SET_CFG_MUX1_SDHC1_DSPI(reg, value)     ((reg & 0x3f) | value)
  44 #define SDHC1_BASE_PMUX_DSPI                    2
  45 #define SDHC2_BASE_PMUX_DSPI                    2
  46 #define IIC5_PMUX_SPI3                          3
  47 #endif /* CONFIG_TARGET_LX2160AQDS */
  48
  49 DECLARE_GLOBAL_DATA_PTR;
  50
  51 static struct pl01x_serial_platdata serial0 = {
  52 #if CONFIG_CONS_INDEX == 0
  53         .base = CONFIG_SYS_SERIAL0,
  54 #elif CONFIG_CONS_INDEX == 1
  55         .base = CONFIG_SYS_SERIAL1,
  56 #else
  57 #error "Unsupported console index value."
  58 #endif
  59         .type = TYPE_PL011,
  60 };
  61
  62 U_BOOT_DEVICE(nxp_serial0) = {
  63         .name = "serial_pl01x",
  64         .platdata = &serial0,
  65 };
  66
  67 static struct pl01x_serial_platdata serial1 = {
  68         .base = CONFIG_SYS_SERIAL1,
  69         .type = TYPE_PL011,
  70 };
  71
  72 U_BOOT_DEVICE(nxp_serial1) = {
  73         .name = "serial_pl01x",
  74         .platdata = &serial1,
  75 };
  76
  77 int select_i2c_ch_pca9547(u8 ch)
  78 {
  79         int ret;
  80
  81 #ifndef CONFIG_DM_I2C
  82         ret = i2c_write(I2C_MUX_PCA_ADDR_PRI, 0, 1, &ch, 1);
  83 #else
  84         struct udevice *dev;
  85
  86         ret = i2c_get_chip_for_busnum(0, I2C_MUX_PCA_ADDR_PRI, 1, &dev);
  87         if (!ret)
  88                 ret = dm_i2c_write(dev, 0, &ch, 1);
  89 #endif
  90         if (ret) {
  91                 puts("PCA: failed to select proper channel\n");
  92                 return ret;
  93         }
  94
  95         return 0;
  96 }
  97
  98 static void uart_get_clock(void)
  99 {
 100         serial0.clock = get_serial_clock();
 101         serial1.clock = get_serial_clock();
 102 }
 103
 104 int board_early_init_f(void)
 105 {
 106 #ifdef CONFIG_SYS_I2C_EARLY_INIT
 107         i2c_early_init_f();
 108 #endif
 109         /* get required clock for UART IP */
 110         uart_get_clock();
 111
 112 #ifdef CONFIG_EMC2305
 113         select_i2c_ch_pca9547(I2C_MUX_CH_EMC2305);
 114         emc2305_init();
 115         set_fan_speed(I2C_EMC2305_PWM);
 116         select_i2c_ch_pca9547(I2C_MUX_CH_DEFAULT);
 117 #endif
 118
 119         fsl_lsch3_early_init_f();
 120         return 0;
 121 }
 122
 123 #ifdef CONFIG_OF_BOARD_FIXUP
 124 int board_fix_fdt(void *fdt)
 125 {
 126         char *reg_names, *reg_name;
 127         int names_len, old_name_len, new_name_len, remaining_names_len;
 128         struct str_map {
 129                 char *old_str;
 130                 char *new_str;
 131         } reg_names_map[] = {
 132                 { "ccsr", "dbi" },
 133                 { "pf_ctrl", "ctrl" }
 134         };
 135         int off = -1, i = 0;
 136
 137         if (IS_SVR_REV(get_svr(), 1, 0))
 138                 return 0;
 139
 140         off = fdt_node_offset_by_compatible(fdt, -1, "fsl,lx2160a-pcie");
 141         while (off != -FDT_ERR_NOTFOUND) {
 142                 fdt_setprop(fdt, off, "compatible", "fsl,ls-pcie",
 143                             strlen("fsl,ls-pcie") + 1);
 144
 145                 reg_names = (char *)fdt_getprop(fdt, off, "reg-names",
 146                                                 &names_len);
 147                 if (!reg_names)
 148                         continue;
 149
 150                 reg_name = reg_names;
 151                 remaining_names_len = names_len - (reg_name - reg_names);
 152                 while ((i < ARRAY_SIZE(reg_names_map)) && remaining_names_len) {
 153                         old_name_len = strlen(reg_names_map[i].old_str);
 154                         new_name_len = strlen(reg_names_map[i].new_str);
 155                         if (memcmp(reg_name, reg_names_map[i].old_str,
 156                                    old_name_len) == 0) {
 157                                 /* first only leave required bytes for new_str
 158                                  * and copy rest of the string after it
 159                                  */
 160                                 memcpy(reg_name + new_name_len,
 161                                        reg_name + old_name_len,
 162                                        remaining_names_len - old_name_len);
 163                                 /* Now copy new_str */
 164                                 memcpy(reg_name, reg_names_map[i].new_str,
 165                                        new_name_len);
 166                                 names_len -= old_name_len;
 167                                 names_len += new_name_len;
 168                                 i++;
 169                         }
 170
 171                         reg_name = memchr(reg_name, '\0', remaining_names_len);
 172                         if (!reg_name)
 173                                 break;
 174
 175                         reg_name += 1;
 176
 177                         remaining_names_len = names_len -
 178                                               (reg_name - reg_names);
 179                 }
 180
 181                 fdt_setprop(fdt, off, "reg-names", reg_names, names_len);
 182                 off = fdt_node_offset_by_compatible(fdt, off,
 183                                                     "fsl,lx2160a-pcie");
 184         }
 185
 186         return 0;
 187 }
 188 #endif
 189
 190 #if defined(CONFIG_TARGET_LX2160AQDS)
 191 void esdhc_dspi_status_fixup(void *blob)
 192 {
 193         const char esdhc0_path[] = "/soc/esdhc@2140000";
 194         const char esdhc1_path[] = "/soc/esdhc@2150000";
 195         const char dspi0_path[] = "/soc/spi@2100000";
 196         const char dspi1_path[] = "/soc/spi@2110000";
 197         const char dspi2_path[] = "/soc/spi@2120000";
 198
 199         struct ccsr_gur __iomem *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR);
 200         u32 sdhc1_base_pmux;
 201         u32 sdhc2_base_pmux;
 202         u32 iic5_pmux;
 203
 204         /* Check RCW field sdhc1_base_pmux to enable/disable
 205          * esdhc0/dspi0 DT node
 206          */
 207         sdhc1_base_pmux = gur_in32(&gur->rcwsr[FSL_CHASSIS3_RCWSR12_REGSR - 1])
 208                 & FSL_CHASSIS3_SDHC1_BASE_PMUX_MASK;
 209         sdhc1_base_pmux >>= FSL_CHASSIS3_SDHC1_BASE_PMUX_SHIFT;
 210
 211         if (sdhc1_base_pmux == SDHC1_BASE_PMUX_DSPI) {
 212                 do_fixup_by_path(blob, dspi0_path, "status", "okay",
 213                                  sizeof("okay"), 1);
 214                 do_fixup_by_path(blob, esdhc0_path, "status", "disabled",
 215                                  sizeof("disabled"), 1);
 216         } else {
 217                 do_fixup_by_path(blob, esdhc0_path, "status", "okay",
 218                                  sizeof("okay"), 1);
 219                 do_fixup_by_path(blob, dspi0_path, "status", "disabled",
 220                                  sizeof("disabled"), 1);
 221         }
 222
 223         /* Check RCW field sdhc2_base_pmux to enable/disable
 224          * esdhc1/dspi1 DT node
 225          */
 226         sdhc2_base_pmux = gur_in32(&gur->rcwsr[FSL_CHASSIS3_RCWSR13_REGSR - 1])
 227                 & FSL_CHASSIS3_SDHC2_BASE_PMUX_MASK;
 228         sdhc2_base_pmux >>= FSL_CHASSIS3_SDHC2_BASE_PMUX_SHIFT;
 229
 230         if (sdhc2_base_pmux == SDHC2_BASE_PMUX_DSPI) {
 231                 do_fixup_by_path(blob, dspi1_path, "status", "okay",
 232                                  sizeof("okay"), 1);
 233                 do_fixup_by_path(blob, esdhc1_path, "status", "disabled",
 234                                  sizeof("disabled"), 1);
 235         } else {
 236                 do_fixup_by_path(blob, esdhc1_path, "status", "okay",
 237                                  sizeof("okay"), 1);
 238                 do_fixup_by_path(blob, dspi1_path, "status", "disabled",
 239                                  sizeof("disabled"), 1);
 240         }
 241
 242         /* Check RCW field IIC5 to enable dspi2 DT node */
 243         iic5_pmux = gur_in32(&gur->rcwsr[FSL_CHASSIS3_RCWSR12_REGSR - 1])
 244                 & FSL_CHASSIS3_IIC5_PMUX_MASK;
 245         iic5_pmux >>= FSL_CHASSIS3_IIC5_PMUX_SHIFT;
 246
 247         if (iic5_pmux == IIC5_PMUX_SPI3)
 248                 do_fixup_by_path(blob, dspi2_path, "status", "okay",
 249                                  sizeof("okay"), 1);
 250         else
 251                 do_fixup_by_path(blob, dspi2_path, "status", "disabled",
 252                                  sizeof("disabled"), 1);
 253 }
 254 #endif
 255
 256 int esdhc_status_fixup(void *blob, const char *compat)
 257 {
 258 #if defined(CONFIG_TARGET_LX2160AQDS)
 259         /* Enable esdhc and dspi DT nodes based on RCW fields */
 260         esdhc_dspi_status_fixup(blob);
 261 #else
 262         /* Enable both esdhc DT nodes for LX2160ARDB */
 263         do_fixup_by_compat(blob, compat, "status", "okay",
 264                            sizeof("okay"), 1);
 265 #endif
 266         return 0;
 267 }
 268
 269 #if defined(CONFIG_VID)
 270 int i2c_multiplexer_select_vid_channel(u8 channel)
 271 {
 272         return select_i2c_ch_pca9547(channel);
 273 }
 274
 275 int init_func_vid(void)
 276 {
 277         if (adjust_vdd(0) < 0)
 278                 printf("core voltage not adjusted\n");
 279
 280         return 0;
 281 }
 282 #endif
 283
 284 int checkboard(void)
 285 {
 286         enum boot_src src = get_boot_src();
 287         char buf[64];
 288         u8 sw;
 289 #ifdef CONFIG_TARGET_LX2160AQDS
 290         int clock;
 291         static const char *const freq[] = {"100", "125", "156.25",
 292                                            "161.13", "322.26", "", "", "",
 293                                            "", "", "", "", "", "", "",
 294                                            "100 separate SSCG"};
 295 #endif
 296
 297         cpu_name(buf);
 298 #ifdef CONFIG_TARGET_LX2160AQDS
 299         printf("Board: %s-QDS, ", buf);
 300 #else
 301         printf("Board: %s-RDB, ", buf);
 302 #endif
 303
 304         sw = QIXIS_READ(arch);
 305         printf("Board version: %c, boot from ", (sw & 0xf) - 1 + 'A');
 306
 307         if (src == BOOT_SOURCE_SD_MMC) {
 308                 puts("SD\n");
 309         } else {
 310                 sw = QIXIS_READ(brdcfg[0]);
 311                 sw = (sw >> QIXIS_XMAP_SHIFT) & QIXIS_XMAP_MASK;
 312                 switch (sw) {
 313                 case 0:
 314                 case 4:
 315                         puts("FlexSPI DEV#0\n");
 316                         break;
 317                 case 1:
 318                         puts("FlexSPI DEV#1\n");
 319                         break;
 320                 case 2:
 321                 case 3:
 322                         puts("FlexSPI EMU\n");
 323                         break;
 324                 default:
 325                         printf("invalid setting, xmap: %d\n", sw);
 326                         break;
 327                 }
 328         }
 329 #ifdef CONFIG_TARGET_LX2160AQDS
 330         printf("FPGA: v%d (%s), build %d",
 331                (int)QIXIS_READ(scver), qixis_read_tag(buf),
 332                (int)qixis_read_minor());
 333         /* the timestamp string contains "\n" at the end */
 334         printf(" on %s", qixis_read_time(buf));
 335
 336         puts("SERDES1 Reference : ");
 337         sw = QIXIS_READ(brdcfg[2]);
 338         clock = sw >> 4;
 339         printf("Clock1 = %sMHz ", freq[clock]);
 340         clock = sw & 0x0f;
 341         printf("Clock2 = %sMHz", freq[clock]);
 342
 343         sw = QIXIS_READ(brdcfg[3]);
 344         puts("\nSERDES2 Reference : ");
 345         clock = sw >> 4;
 346         printf("Clock1 = %sMHz ", freq[clock]);
 347         clock = sw & 0x0f;
 348         printf("Clock2 = %sMHz", freq[clock]);
 349
 350         sw = QIXIS_READ(brdcfg[12]);
 351         puts("\nSERDES3 Reference : ");
 352         clock = sw >> 4;
 353         printf("Clock1 = %sMHz Clock2 = %sMHz\n", freq[clock], freq[clock]);
 354 #else
 355         printf("FPGA: v%d.%d\n", QIXIS_READ(scver), QIXIS_READ(tagdata));
 356
 357         puts("SERDES1 Reference: Clock1 = 161.13MHz Clock2 = 161.13MHz\n");
 358         puts("SERDES2 Reference: Clock1 = 100MHz Clock2 = 100MHz\n");
 359         puts("SERDES3 Reference: Clock1 = 100MHz Clock2 = 100MHz\n");
 360 #endif
 361         return 0;
 362 }
 363
 364 #ifdef CONFIG_TARGET_LX2160AQDS
 365 /*
 366  * implementation of CONFIG_ESDHC_DETECT_QUIRK Macro.
 367  */
 368 u8 qixis_esdhc_detect_quirk(void)
 369 {
 370         /* for LX2160AQDS res1[1] @ offset 0x1A is SDHC1 Control/Status (SDHC1)
 371          * SDHC1 Card ID:
 372          * Specifies the type of card installed in the SDHC1 adapter slot.
 373          * 000= (reserved)
 374          * 001= eMMC V4.5 adapter is installed.
 375          * 010= SD/MMC 3.3V adapter is installed.
 376          * 011= eMMC V4.4 adapter is installed.
 377          * 100= eMMC V5.0 adapter is installed.
 378          * 101= MMC card/Legacy (3.3V) adapter is installed.
 379          * 110= SDCard V2/V3 adapter installed.
 380          * 111= no adapter is installed.
 381          */
 382         return ((QIXIS_READ(res1[1]) & QIXIS_SDID_MASK) !=
 383                  QIXIS_ESDHC_NO_ADAPTER);
 384 }
 385
 386 int config_board_mux(void)
 387 {
 388         u8 reg11, reg5, reg13;
 389         struct ccsr_gur __iomem *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR);
 390         u32 sdhc1_base_pmux;
 391         u32 sdhc2_base_pmux;
 392         u32 iic5_pmux;
 393
 394         /* Routes {I2C2_SCL, I2C2_SDA} to SDHC1 as {SDHC1_CD_B, SDHC1_WP}.
 395          * Routes {I2C3_SCL, I2C3_SDA} to CAN transceiver as {CAN1_TX,CAN1_RX}.
 396          * Routes {I2C4_SCL, I2C4_SDA} to CAN transceiver as {CAN2_TX,CAN2_RX}.
 397          * Qixis and remote systems are isolated from the I2C1 bus.
 398          * Processor connections are still available.
 399          * SPI2 CS2_B controls EN25S64 SPI memory device.
 400          * SPI3 CS2_B controls EN25S64 SPI memory device.
 401          * EC2 connects to PHY #2 using RGMII protocol.
 402          * CLK_OUT connects to FPGA for clock measurement.
 403          */
 404
 405         reg5 = QIXIS_READ(brdcfg[5]);
 406         reg5 = CFG_MUX_I2C_SDHC(reg5, 0x40);
 407         QIXIS_WRITE(brdcfg[5], reg5);
 408
 409         /* Check RCW field sdhc1_base_pmux
 410          * esdhc0 : sdhc1_base_pmux = 0
 411          * dspi0  : sdhc1_base_pmux = 2
 412          */
 413         sdhc1_base_pmux = gur_in32(&gur->rcwsr[FSL_CHASSIS3_RCWSR12_REGSR - 1])
 414                 & FSL_CHASSIS3_SDHC1_BASE_PMUX_MASK;
 415         sdhc1_base_pmux >>= FSL_CHASSIS3_SDHC1_BASE_PMUX_SHIFT;
 416
 417         if (sdhc1_base_pmux == SDHC1_BASE_PMUX_DSPI) {
 418                 reg11 = QIXIS_READ(brdcfg[11]);
 419                 reg11 = SET_CFG_MUX1_SDHC1_DSPI(reg11, 0x40);
 420                 QIXIS_WRITE(brdcfg[11], reg11);
 421         } else {
 422                 /* - Routes {SDHC1_CMD, SDHC1_CLK } to SDHC1 adapter slot.
 423                  *          {SDHC1_DAT3, SDHC1_DAT2} to SDHC1 adapter slot.
 424                  *          {SDHC1_DAT1, SDHC1_DAT0} to SDHC1 adapter slot.
 425                  */
 426                 reg11 = QIXIS_READ(brdcfg[11]);
 427                 reg11 = SET_CFG_MUX1_SDHC1_SDHC(reg11);
 428                 QIXIS_WRITE(brdcfg[11], reg11);
 429         }
 430
 431         /* Check RCW field sdhc2_base_pmux
 432          * esdhc1 : sdhc2_base_pmux = 0 (default)
 433          * dspi1  : sdhc2_base_pmux = 2
 434          */
 435         sdhc2_base_pmux = gur_in32(&gur->rcwsr[FSL_CHASSIS3_RCWSR13_REGSR - 1])
 436                 & FSL_CHASSIS3_SDHC2_BASE_PMUX_MASK;
 437         sdhc2_base_pmux >>= FSL_CHASSIS3_SDHC2_BASE_PMUX_SHIFT;
 438
 439         if (sdhc2_base_pmux == SDHC2_BASE_PMUX_DSPI) {
 440                 reg13 = QIXIS_READ(brdcfg[13]);
 441                 reg13 = SET_CFG_MUX_SDHC2_DSPI(reg13, 0x01);
 442                 QIXIS_WRITE(brdcfg[13], reg13);
 443         } else {
 444                 reg13 = QIXIS_READ(brdcfg[13]);
 445                 reg13 = SET_CFG_MUX_SDHC2_DSPI(reg13, 0x00);
 446                 QIXIS_WRITE(brdcfg[13], reg13);
 447         }
 448
 449         /* Check RCW field IIC5 to enable dspi2 DT nodei
 450          * dspi2: IIC5 = 3
 451          */
 452         iic5_pmux = gur_in32(&gur->rcwsr[FSL_CHASSIS3_RCWSR12_REGSR - 1])
 453                 & FSL_CHASSIS3_IIC5_PMUX_MASK;
 454         iic5_pmux >>= FSL_CHASSIS3_IIC5_PMUX_SHIFT;
 455
 456         if (iic5_pmux == IIC5_PMUX_SPI3) {
 457                 /* - Routes {SDHC1_DAT4} to SPI3 devices as {SPI3_M_CS0_B}. */
 458                 reg11 = QIXIS_READ(brdcfg[11]);
 459                 reg11 = SET_CFG_MUX2_SDHC1_SPI(reg11, 0x10);
 460                 QIXIS_WRITE(brdcfg[11], reg11);
 461
 462                 /* - Routes {SDHC1_DAT5, SDHC1_DAT6} nowhere.
 463                  * {SDHC1_DAT7, SDHC1_DS } to {nothing, SPI3_M0_CLK }.
 464                  * {I2C5_SCL, I2C5_SDA } to {SPI3_M0_MOSI, SPI3_M0_MISO}.
 465                  */
 466                 reg11 = QIXIS_READ(brdcfg[11]);
 467                 reg11 = SET_CFG_MUX3_SDHC1_SPI(reg11, 0x01);
 468                 QIXIS_WRITE(brdcfg[11], reg11);
 469         } else {
 470                 /*  Routes {SDHC1_DAT4} to SDHC1 adapter slot */
 471                 reg11 = QIXIS_READ(brdcfg[11]);
 472                 reg11 = SET_CFG_MUX2_SDHC1_SPI(reg11, 0x00);
 473                 QIXIS_WRITE(brdcfg[11], reg11);
 474
 475                 /* - Routes {SDHC1_DAT5, SDHC1_DAT6} to SDHC1 adapter slot.
 476                  * {SDHC1_DAT7, SDHC1_DS } to SDHC1 adapter slot.
 477                  * {I2C5_SCL, I2C5_SDA } to SDHC1 adapter slot.
 478                  */
 479                 reg11 = QIXIS_READ(brdcfg[11]);
 480                 reg11 = SET_CFG_MUX3_SDHC1_SPI(reg11, 0x00);
 481                 QIXIS_WRITE(brdcfg[11], reg11);
 482         }
 483
 484         return 0;
 485 }
 486 #elif defined(CONFIG_TARGET_LX2160ARDB)
 487 int config_board_mux(void)
 488 {
 489         u8 brdcfg;
 490
 491         brdcfg = QIXIS_READ(brdcfg[4]);
 492         /* The BRDCFG4 register controls general board configuration.
 493          *|-------------------------------------------|
 494          *|Field  | Function                          |
 495          *|-------------------------------------------|
 496          *|5      | CAN I/O Enable (net CFG_CAN_EN_B):|
 497          *|CAN_EN | 0= CAN transceivers are disabled. |
 498          *|       | 1= CAN transceivers are enabled.  |
 499          *|-------------------------------------------|
 500          */
 501         brdcfg |= BIT_MASK(5);
 502         QIXIS_WRITE(brdcfg[4], brdcfg);
 503
 504         return 0;
 505 }
 506 #else
 507 int config_board_mux(void)
 508 {
 509         return 0;
 510 }
 511 #endif
 512
 513 unsigned long get_board_sys_clk(void)
 514 {
 515 #ifdef CONFIG_TARGET_LX2160AQDS
 516         u8 sysclk_conf = QIXIS_READ(brdcfg[1]);
 517
 518         switch (sysclk_conf & 0x03) {
 519         case QIXIS_SYSCLK_100:
 520                 return 100000000;
 521         case QIXIS_SYSCLK_125:
 522                 return 125000000;
 523         case QIXIS_SYSCLK_133:
 524                 return 133333333;
 525         }
 526         return 100000000;
 527 #else
 528         return 100000000;
 529 #endif
 530 }
 531
 532 unsigned long get_board_ddr_clk(void)
 533 {
 534 #ifdef CONFIG_TARGET_LX2160AQDS
 535         u8 ddrclk_conf = QIXIS_READ(brdcfg[1]);
 536
 537         switch ((ddrclk_conf & 0x30) >> 4) {
 538         case QIXIS_DDRCLK_100:
 539                 return 100000000;
 540         case QIXIS_DDRCLK_125:
 541                 return 125000000;
 542         case QIXIS_DDRCLK_133:
 543                 return 133333333;
 544         }
 545         return 100000000;
 546 #else
 547         return 100000000;
 548 #endif
 549 }
 550
 551 int board_init(void)
 552 {
 553 #if defined(CONFIG_FSL_MC_ENET) && defined(CONFIG_TARGET_LX2160ARDB)
 554         u32 __iomem *irq_ccsr = (u32 __iomem *)ISC_BASE;
 555 #endif
 556 #ifdef CONFIG_ENV_IS_NOWHERE
 557         gd->env_addr = (ulong)&default_environment[0];
 558 #endif
 559
 560         select_i2c_ch_pca9547(I2C_MUX_CH_DEFAULT);
 561
 562 #if defined(CONFIG_FSL_MC_ENET) && defined(CONFIG_TARGET_LX2160ARDB)
 563         /* invert AQR107 IRQ pins polarity */
 564         out_le32(irq_ccsr + IRQCR_OFFSET / 4, AQR107_IRQ_MASK);
 565 #endif
 566
 567 #ifdef CONFIG_FSL_CAAM
 568         sec_init();
 569 #endif
 570
 571         return 0;
 572 }
 573
 574 void detail_board_ddr_info(void)
 575 {
 576         int i;
 577         u64 ddr_size = 0;
 578
 579         puts("\nDDR    ");
 580         for (i = 0; i < CONFIG_NR_DRAM_BANKS; i++)
 581                 ddr_size += gd->bd->bi_dram[i].size;
 582         print_size(ddr_size, "");
 583         print_ddr_info(0);
 584 }
 585
 586 #ifdef CONFIG_MISC_INIT_R
 587 int misc_init_r(void)
 588 {
 589         config_board_mux();
 590
 591         return 0;
 592 }
 593 #endif
 594
 595 #ifdef CONFIG_FSL_MC_ENET
 596 extern int fdt_fixup_board_phy(void *fdt);
 597
 598 void fdt_fixup_board_enet(void *fdt)
 599 {
 600         int offset;
 601
 602         offset = fdt_path_offset(fdt, "/soc/fsl-mc");
 603
 604         if (offset < 0)
 605                 offset = fdt_path_offset(fdt, "/fsl-mc");
 606
 607         if (offset < 0) {
 608                 printf("%s: fsl-mc node not found in device tree (error %d)\n",
 609                        __func__, offset);
 610                 return;
 611         }
 612
 613         if (get_mc_boot_status() == 0 &&
 614             (is_lazy_dpl_addr_valid() || get_dpl_apply_status() == 0)) {
 615                 fdt_status_okay(fdt, offset);
 616                 fdt_fixup_board_phy(fdt);
 617         } else {
 618                 fdt_status_fail(fdt, offset);
 619         }
 620 }
 621
 622 void board_quiesce_devices(void)
 623 {
 624         fsl_mc_ldpaa_exit(gd->bd);
 625 }
 626 #endif
 627
 628 #ifdef CONFIG_OF_BOARD_SETUP
 629
 630 int ft_board_setup(void *blob, bd_t *bd)
 631 {
 632         int i;
 633         u16 mc_memory_bank = 0;
 634
 635         u64 *base;
 636         u64 *size;
 637         u64 mc_memory_base = 0;
 638         u64 mc_memory_size = 0;
 639         u16 total_memory_banks;
 640
 641         ft_cpu_setup(blob, bd);
 642
 643         fdt_fixup_mc_ddr(&mc_memory_base, &mc_memory_size);
 644
 645         if (mc_memory_base != 0)
 646                 mc_memory_bank++;
 647
 648         total_memory_banks = CONFIG_NR_DRAM_BANKS + mc_memory_bank;
 649
 650         base = calloc(total_memory_banks, sizeof(u64));
 651         size = calloc(total_memory_banks, sizeof(u64));
 652
 653         /* fixup DT for the three GPP DDR banks */
 654         for (i = 0; i < CONFIG_NR_DRAM_BANKS; i++) {
 655                 base[i] = gd->bd->bi_dram[i].start;
 656                 size[i] = gd->bd->bi_dram[i].size;
 657         }
 658
 659 #ifdef CONFIG_RESV_RAM
 660         /* reduce size if reserved memory is within this bank */
 661         if (gd->arch.resv_ram >= base[0] &&
 662             gd->arch.resv_ram < base[0] + size[0])
 663                 size[0] = gd->arch.resv_ram - base[0];
 664         else if (gd->arch.resv_ram >= base[1] &&
 665                  gd->arch.resv_ram < base[1] + size[1])
 666                 size[1] = gd->arch.resv_ram - base[1];
 667         else if (gd->arch.resv_ram >= base[2] &&
 668                  gd->arch.resv_ram < base[2] + size[2])
 669                 size[2] = gd->arch.resv_ram - base[2];
 670 #endif
 671
 672         if (mc_memory_base != 0) {
 673                 for (i = 0; i <= total_memory_banks; i++) {
 674                         if (base[i] == 0 && size[i] == 0) {
 675                                 base[i] = mc_memory_base;
 676                                 size[i] = mc_memory_size;
 677                                 break;
 678                         }
 679                 }
 680         }
 681
 682         fdt_fixup_memory_banks(blob, base, size, total_memory_banks);
 683
 684 #ifdef CONFIG_USB
 685         fsl_fdt_fixup_dr_usb(blob, bd);
 686 #endif
 687
 688 #ifdef CONFIG_FSL_MC_ENET
 689         fdt_fsl_mc_fixup_iommu_map_entry(blob);
 690         fdt_fixup_board_enet(blob);
 691 #endif
 692         fdt_fixup_icid(blob);
 693
 694         return 0;
 695 }
 696 #endif
 697
 698 void qixis_dump_switch(void)
 699 {
 700         int i, nr_of_cfgsw;
 701
 702         QIXIS_WRITE(cms[0], 0x00);
 703         nr_of_cfgsw = QIXIS_READ(cms[1]);
 704
 705         puts("DIP switch settings dump:\n");
 706         for (i = 1; i <= nr_of_cfgsw; i++) {
 707                 QIXIS_WRITE(cms[0], i);
 708                 printf("SW%d = (0x%02x)\n", i, QIXIS_READ(cms[1]));
 709         }
 710 }