board/freescale/lx2160a/lx2160a.c

   1 // SPDX-License-Identifier: GPL-2.0+
   2 /*
   3  * Copyright 2018-2020 NXP
   4  */
   5
   6 #include <common.h>
   7 #include <clock_legacy.h>
   8 #include <dm.h>
   9 #include <init.h>
  10 #include <dm/platform_data/serial_pl01x.h>
  11 #include <i2c.h>
  12 #include <malloc.h>
  13 #include <errno.h>
  14 #include <netdev.h>
  15 #include <fsl_ddr.h>
  16 #include <fsl_sec.h>
  17 #include <asm/io.h>
  18 #include <fdt_support.h>
  19 #include <linux/bitops.h>
  20 #include <linux/libfdt.h>
  21 #include <fsl-mc/fsl_mc.h>
  22 #include <env_internal.h>
  23 #include <efi_loader.h>
  24 #include <asm/arch/mmu.h>
  25 #include <hwconfig.h>
  26 #include <asm/arch/clock.h>
  27 #include <asm/arch/config.h>
  28 #include <asm/arch/fsl_serdes.h>
  29 #include <asm/arch/soc.h>
  30 #include "../common/qixis.h"
  31 #include "../common/vid.h"
  32 #include <fsl_immap.h>
  33 #include <asm/arch-fsl-layerscape/fsl_icid.h>
  34
  35 #ifdef CONFIG_EMC2305
  36 #include "../common/emc2305.h"
  37 #endif
  38
  39 #ifdef CONFIG_TARGET_LX2160AQDS
  40 #define CFG_MUX_I2C_SDHC(reg, value)            ((reg & 0x3f) | value)
  41 #define SET_CFG_MUX1_SDHC1_SDHC(reg)            (reg & 0x3f)
  42 #define SET_CFG_MUX2_SDHC1_SPI(reg, value)      ((reg & 0xcf) | value)
  43 #define SET_CFG_MUX3_SDHC1_SPI(reg, value)      ((reg & 0xf8) | value)
  44 #define SET_CFG_MUX_SDHC2_DSPI(reg, value)      ((reg & 0xf8) | value)
  45 #define SET_CFG_MUX1_SDHC1_DSPI(reg, value)     ((reg & 0x3f) | value)
  46 #define SDHC1_BASE_PMUX_DSPI                    2
  47 #define SDHC2_BASE_PMUX_DSPI                    2
  48 #define IIC5_PMUX_SPI3                          3
  49 #endif /* CONFIG_TARGET_LX2160AQDS */
  50
  51 DECLARE_GLOBAL_DATA_PTR;
  52
  53 static struct pl01x_serial_platdata serial0 = {
  54 #if CONFIG_CONS_INDEX == 0
  55         .base = CONFIG_SYS_SERIAL0,
  56 #elif CONFIG_CONS_INDEX == 1
  57         .base = CONFIG_SYS_SERIAL1,
  58 #else
  59 #error "Unsupported console index value."
  60 #endif
  61         .type = TYPE_PL011,
  62 };
  63
  64 U_BOOT_DEVICE(nxp_serial0) = {
  65         .name = "serial_pl01x",
  66         .platdata = &serial0,
  67 };
  68
  69 static struct pl01x_serial_platdata serial1 = {
  70         .base = CONFIG_SYS_SERIAL1,
  71         .type = TYPE_PL011,
  72 };
  73
  74 U_BOOT_DEVICE(nxp_serial1) = {
  75         .name = "serial_pl01x",
  76         .platdata = &serial1,
  77 };
  78
  79 int select_i2c_ch_pca9547(u8 ch)
  80 {
  81         int ret;
  82
  83 #ifndef CONFIG_DM_I2C
  84         ret = i2c_write(I2C_MUX_PCA_ADDR_PRI, 0, 1, &ch, 1);
  85 #else
  86         struct udevice *dev;
  87
  88         ret = i2c_get_chip_for_busnum(0, I2C_MUX_PCA_ADDR_PRI, 1, &dev);
  89         if (!ret)
  90                 ret = dm_i2c_write(dev, 0, &ch, 1);
  91 #endif
  92         if (ret) {
  93                 puts("PCA: failed to select proper channel\n");
  94                 return ret;
  95         }
  96
  97         return 0;
  98 }
  99
 100 static void uart_get_clock(void)
 101 {
 102         serial0.clock = get_serial_clock();
 103         serial1.clock = get_serial_clock();
 104 }
 105
 106 int board_early_init_f(void)
 107 {
 108 #ifdef CONFIG_SYS_I2C_EARLY_INIT
 109         i2c_early_init_f();
 110 #endif
 111         /* get required clock for UART IP */
 112         uart_get_clock();
 113
 114 #ifdef CONFIG_EMC2305
 115         select_i2c_ch_pca9547(I2C_MUX_CH_EMC2305);
 116         emc2305_init();
 117         set_fan_speed(I2C_EMC2305_PWM);
 118         select_i2c_ch_pca9547(I2C_MUX_CH_DEFAULT);
 119 #endif
 120
 121         fsl_lsch3_early_init_f();
 122         return 0;
 123 }
 124
 125 #ifdef CONFIG_OF_BOARD_FIXUP
 126 int board_fix_fdt(void *fdt)
 127 {
 128         char *reg_names, *reg_name;
 129         int names_len, old_name_len, new_name_len, remaining_names_len;
 130         struct str_map {
 131                 char *old_str;
 132                 char *new_str;
 133         } reg_names_map[] = {
 134                 { "ccsr", "dbi" },
 135                 { "pf_ctrl", "ctrl" }
 136         };
 137         int off = -1, i = 0;
 138
 139         if (IS_SVR_REV(get_svr(), 1, 0))
 140                 return 0;
 141
 142         off = fdt_node_offset_by_compatible(fdt, -1, "fsl,lx2160a-pcie");
 143         while (off != -FDT_ERR_NOTFOUND) {
 144                 fdt_setprop(fdt, off, "compatible", "fsl,ls-pcie",
 145                             strlen("fsl,ls-pcie") + 1);
 146
 147                 reg_names = (char *)fdt_getprop(fdt, off, "reg-names",
 148                                                 &names_len);
 149                 if (!reg_names)
 150                         continue;
 151
 152                 reg_name = reg_names;
 153                 remaining_names_len = names_len - (reg_name - reg_names);
 154                 i = 0;
 155                 while ((i < ARRAY_SIZE(reg_names_map)) && remaining_names_len) {
 156                         old_name_len = strlen(reg_names_map[i].old_str);
 157                         new_name_len = strlen(reg_names_map[i].new_str);
 158                         if (memcmp(reg_name, reg_names_map[i].old_str,
 159                                    old_name_len) == 0) {
 160                                 /* first only leave required bytes for new_str
 161                                  * and copy rest of the string after it
 162                                  */
 163                                 memcpy(reg_name + new_name_len,
 164                                        reg_name + old_name_len,
 165                                        remaining_names_len - old_name_len);
 166                                 /* Now copy new_str */
 167                                 memcpy(reg_name, reg_names_map[i].new_str,
 168                                        new_name_len);
 169                                 names_len -= old_name_len;
 170                                 names_len += new_name_len;
 171                                 i++;
 172                         }
 173
 174                         reg_name = memchr(reg_name, '\0', remaining_names_len);
 175                         if (!reg_name)
 176                                 break;
 177
 178                         reg_name += 1;
 179
 180                         remaining_names_len = names_len -
 181                                               (reg_name - reg_names);
 182                 }
 183
 184                 fdt_setprop(fdt, off, "reg-names", reg_names, names_len);
 185                 off = fdt_node_offset_by_compatible(fdt, off,
 186                                                     "fsl,lx2160a-pcie");
 187         }
 188
 189         return 0;
 190 }
 191 #endif
 192
 193 #if defined(CONFIG_TARGET_LX2160AQDS)
 194 void esdhc_dspi_status_fixup(void *blob)
 195 {
 196         const char esdhc0_path[] = "/soc/esdhc@2140000";
 197         const char esdhc1_path[] = "/soc/esdhc@2150000";
 198         const char dspi0_path[] = "/soc/spi@2100000";
 199         const char dspi1_path[] = "/soc/spi@2110000";
 200         const char dspi2_path[] = "/soc/spi@2120000";
 201
 202         struct ccsr_gur __iomem *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR);
 203         u32 sdhc1_base_pmux;
 204         u32 sdhc2_base_pmux;
 205         u32 iic5_pmux;
 206
 207         /* Check RCW field sdhc1_base_pmux to enable/disable
 208          * esdhc0/dspi0 DT node
 209          */
 210         sdhc1_base_pmux = gur_in32(&gur->rcwsr[FSL_CHASSIS3_RCWSR12_REGSR - 1])
 211                 & FSL_CHASSIS3_SDHC1_BASE_PMUX_MASK;
 212         sdhc1_base_pmux >>= FSL_CHASSIS3_SDHC1_BASE_PMUX_SHIFT;
 213
 214         if (sdhc1_base_pmux == SDHC1_BASE_PMUX_DSPI) {
 215                 do_fixup_by_path(blob, dspi0_path, "status", "okay",
 216                                  sizeof("okay"), 1);
 217                 do_fixup_by_path(blob, esdhc0_path, "status", "disabled",
 218                                  sizeof("disabled"), 1);
 219         } else {
 220                 do_fixup_by_path(blob, esdhc0_path, "status", "okay",
 221                                  sizeof("okay"), 1);
 222                 do_fixup_by_path(blob, dspi0_path, "status", "disabled",
 223                                  sizeof("disabled"), 1);
 224         }
 225
 226         /* Check RCW field sdhc2_base_pmux to enable/disable
 227          * esdhc1/dspi1 DT node
 228          */
 229         sdhc2_base_pmux = gur_in32(&gur->rcwsr[FSL_CHASSIS3_RCWSR13_REGSR - 1])
 230                 & FSL_CHASSIS3_SDHC2_BASE_PMUX_MASK;
 231         sdhc2_base_pmux >>= FSL_CHASSIS3_SDHC2_BASE_PMUX_SHIFT;
 232
 233         if (sdhc2_base_pmux == SDHC2_BASE_PMUX_DSPI) {
 234                 do_fixup_by_path(blob, dspi1_path, "status", "okay",
 235                                  sizeof("okay"), 1);
 236                 do_fixup_by_path(blob, esdhc1_path, "status", "disabled",
 237                                  sizeof("disabled"), 1);
 238         } else {
 239                 do_fixup_by_path(blob, esdhc1_path, "status", "okay",
 240                                  sizeof("okay"), 1);
 241                 do_fixup_by_path(blob, dspi1_path, "status", "disabled",
 242                                  sizeof("disabled"), 1);
 243         }
 244
 245         /* Check RCW field IIC5 to enable dspi2 DT node */
 246         iic5_pmux = gur_in32(&gur->rcwsr[FSL_CHASSIS3_RCWSR12_REGSR - 1])
 247                 & FSL_CHASSIS3_IIC5_PMUX_MASK;
 248         iic5_pmux >>= FSL_CHASSIS3_IIC5_PMUX_SHIFT;
 249
 250         if (iic5_pmux == IIC5_PMUX_SPI3)
 251                 do_fixup_by_path(blob, dspi2_path, "status", "okay",
 252                                  sizeof("okay"), 1);
 253         else
 254                 do_fixup_by_path(blob, dspi2_path, "status", "disabled",
 255                                  sizeof("disabled"), 1);
 256 }
 257 #endif
 258
 259 int esdhc_status_fixup(void *blob, const char *compat)
 260 {
 261 #if defined(CONFIG_TARGET_LX2160AQDS)
 262         /* Enable esdhc and dspi DT nodes based on RCW fields */
 263         esdhc_dspi_status_fixup(blob);
 264 #else
 265         /* Enable both esdhc DT nodes for LX2160ARDB */
 266         do_fixup_by_compat(blob, compat, "status", "okay",
 267                            sizeof("okay"), 1);
 268 #endif
 269         return 0;
 270 }
 271
 272 #if defined(CONFIG_VID)
 273 int i2c_multiplexer_select_vid_channel(u8 channel)
 274 {
 275         return select_i2c_ch_pca9547(channel);
 276 }
 277
 278 int init_func_vid(void)
 279 {
 280         int set_vid;
 281
 282         if (IS_SVR_REV(get_svr(), 1, 0))
 283                 set_vid = adjust_vdd(800);
 284         else
 285                 set_vid = adjust_vdd(0);
 286
 287         if (set_vid < 0)
 288                 printf("core voltage not adjusted\n");
 289
 290         return 0;
 291 }
 292 #endif
 293
 294 int checkboard(void)
 295 {
 296         enum boot_src src = get_boot_src();
 297         char buf[64];
 298         u8 sw;
 299 #ifdef CONFIG_TARGET_LX2160AQDS
 300         int clock;
 301         static const char *const freq[] = {"100", "125", "156.25",
 302                                            "161.13", "322.26", "", "", "",
 303                                            "", "", "", "", "", "", "",
 304                                            "100 separate SSCG"};
 305 #endif
 306
 307         cpu_name(buf);
 308 #ifdef CONFIG_TARGET_LX2160AQDS
 309         printf("Board: %s-QDS, ", buf);
 310 #else
 311         printf("Board: %s-RDB, ", buf);
 312 #endif
 313
 314         sw = QIXIS_READ(arch);
 315         printf("Board version: %c, boot from ", (sw & 0xf) - 1 + 'A');
 316
 317         if (src == BOOT_SOURCE_SD_MMC) {
 318                 puts("SD\n");
 319         } else if (src == BOOT_SOURCE_SD_MMC2) {
 320                 puts("eMMC\n");
 321         } else {
 322                 sw = QIXIS_READ(brdcfg[0]);
 323                 sw = (sw >> QIXIS_XMAP_SHIFT) & QIXIS_XMAP_MASK;
 324                 switch (sw) {
 325                 case 0:
 326                 case 4:
 327                         puts("FlexSPI DEV#0\n");
 328                         break;
 329                 case 1:
 330                         puts("FlexSPI DEV#1\n");
 331                         break;
 332                 case 2:
 333                 case 3:
 334                         puts("FlexSPI EMU\n");
 335                         break;
 336                 default:
 337                         printf("invalid setting, xmap: %d\n", sw);
 338                         break;
 339                 }
 340         }
 341 #ifdef CONFIG_TARGET_LX2160AQDS
 342         printf("FPGA: v%d (%s), build %d",
 343                (int)QIXIS_READ(scver), qixis_read_tag(buf),
 344                (int)qixis_read_minor());
 345         /* the timestamp string contains "\n" at the end */
 346         printf(" on %s", qixis_read_time(buf));
 347
 348         puts("SERDES1 Reference : ");
 349         sw = QIXIS_READ(brdcfg[2]);
 350         clock = sw >> 4;
 351         printf("Clock1 = %sMHz ", freq[clock]);
 352         clock = sw & 0x0f;
 353         printf("Clock2 = %sMHz", freq[clock]);
 354
 355         sw = QIXIS_READ(brdcfg[3]);
 356         puts("\nSERDES2 Reference : ");
 357         clock = sw >> 4;
 358         printf("Clock1 = %sMHz ", freq[clock]);
 359         clock = sw & 0x0f;
 360         printf("Clock2 = %sMHz", freq[clock]);
 361
 362         sw = QIXIS_READ(brdcfg[12]);
 363         puts("\nSERDES3 Reference : ");
 364         clock = sw >> 4;
 365         printf("Clock1 = %sMHz Clock2 = %sMHz\n", freq[clock], freq[clock]);
 366 #else
 367         printf("FPGA: v%d.%d\n", QIXIS_READ(scver), QIXIS_READ(tagdata));
 368
 369         puts("SERDES1 Reference: Clock1 = 161.13MHz Clock2 = 161.13MHz\n");
 370         puts("SERDES2 Reference: Clock1 = 100MHz Clock2 = 100MHz\n");
 371         puts("SERDES3 Reference: Clock1 = 100MHz Clock2 = 100MHz\n");
 372 #endif
 373         return 0;
 374 }
 375
 376 #ifdef CONFIG_TARGET_LX2160AQDS
 377 /*
 378  * implementation of CONFIG_ESDHC_DETECT_QUIRK Macro.
 379  */
 380 u8 qixis_esdhc_detect_quirk(void)
 381 {
 382         /* for LX2160AQDS res1[1] @ offset 0x1A is SDHC1 Control/Status (SDHC1)
 383          * SDHC1 Card ID:
 384          * Specifies the type of card installed in the SDHC1 adapter slot.
 385          * 000= (reserved)
 386          * 001= eMMC V4.5 adapter is installed.
 387          * 010= SD/MMC 3.3V adapter is installed.
 388          * 011= eMMC V4.4 adapter is installed.
 389          * 100= eMMC V5.0 adapter is installed.
 390          * 101= MMC card/Legacy (3.3V) adapter is installed.
 391          * 110= SDCard V2/V3 adapter installed.
 392          * 111= no adapter is installed.
 393          */
 394         return ((QIXIS_READ(res1[1]) & QIXIS_SDID_MASK) !=
 395                  QIXIS_ESDHC_NO_ADAPTER);
 396 }
 397
 398 int config_board_mux(void)
 399 {
 400         u8 reg11, reg5, reg13;
 401         struct ccsr_gur __iomem *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR);
 402         u32 sdhc1_base_pmux;
 403         u32 sdhc2_base_pmux;
 404         u32 iic5_pmux;
 405
 406         /* Routes {I2C2_SCL, I2C2_SDA} to SDHC1 as {SDHC1_CD_B, SDHC1_WP}.
 407          * Routes {I2C3_SCL, I2C3_SDA} to CAN transceiver as {CAN1_TX,CAN1_RX}.
 408          * Routes {I2C4_SCL, I2C4_SDA} to CAN transceiver as {CAN2_TX,CAN2_RX}.
 409          * Qixis and remote systems are isolated from the I2C1 bus.
 410          * Processor connections are still available.
 411          * SPI2 CS2_B controls EN25S64 SPI memory device.
 412          * SPI3 CS2_B controls EN25S64 SPI memory device.
 413          * EC2 connects to PHY #2 using RGMII protocol.
 414          * CLK_OUT connects to FPGA for clock measurement.
 415          */
 416
 417         reg5 = QIXIS_READ(brdcfg[5]);
 418         reg5 = CFG_MUX_I2C_SDHC(reg5, 0x40);
 419         QIXIS_WRITE(brdcfg[5], reg5);
 420
 421         /* Check RCW field sdhc1_base_pmux
 422          * esdhc0 : sdhc1_base_pmux = 0
 423          * dspi0  : sdhc1_base_pmux = 2
 424          */
 425         sdhc1_base_pmux = gur_in32(&gur->rcwsr[FSL_CHASSIS3_RCWSR12_REGSR - 1])
 426                 & FSL_CHASSIS3_SDHC1_BASE_PMUX_MASK;
 427         sdhc1_base_pmux >>= FSL_CHASSIS3_SDHC1_BASE_PMUX_SHIFT;
 428
 429         if (sdhc1_base_pmux == SDHC1_BASE_PMUX_DSPI) {
 430                 reg11 = QIXIS_READ(brdcfg[11]);
 431                 reg11 = SET_CFG_MUX1_SDHC1_DSPI(reg11, 0x40);
 432                 QIXIS_WRITE(brdcfg[11], reg11);
 433         } else {
 434                 /* - Routes {SDHC1_CMD, SDHC1_CLK } to SDHC1 adapter slot.
 435                  *          {SDHC1_DAT3, SDHC1_DAT2} to SDHC1 adapter slot.
 436                  *          {SDHC1_DAT1, SDHC1_DAT0} to SDHC1 adapter slot.
 437                  */
 438                 reg11 = QIXIS_READ(brdcfg[11]);
 439                 reg11 = SET_CFG_MUX1_SDHC1_SDHC(reg11);
 440                 QIXIS_WRITE(brdcfg[11], reg11);
 441         }
 442
 443         /* Check RCW field sdhc2_base_pmux
 444          * esdhc1 : sdhc2_base_pmux = 0 (default)
 445          * dspi1  : sdhc2_base_pmux = 2
 446          */
 447         sdhc2_base_pmux = gur_in32(&gur->rcwsr[FSL_CHASSIS3_RCWSR13_REGSR - 1])
 448                 & FSL_CHASSIS3_SDHC2_BASE_PMUX_MASK;
 449         sdhc2_base_pmux >>= FSL_CHASSIS3_SDHC2_BASE_PMUX_SHIFT;
 450
 451         if (sdhc2_base_pmux == SDHC2_BASE_PMUX_DSPI) {
 452                 reg13 = QIXIS_READ(brdcfg[13]);
 453                 reg13 = SET_CFG_MUX_SDHC2_DSPI(reg13, 0x01);
 454                 QIXIS_WRITE(brdcfg[13], reg13);
 455         } else {
 456                 reg13 = QIXIS_READ(brdcfg[13]);
 457                 reg13 = SET_CFG_MUX_SDHC2_DSPI(reg13, 0x00);
 458                 QIXIS_WRITE(brdcfg[13], reg13);
 459         }
 460
 461         /* Check RCW field IIC5 to enable dspi2 DT nodei
 462          * dspi2: IIC5 = 3
 463          */
 464         iic5_pmux = gur_in32(&gur->rcwsr[FSL_CHASSIS3_RCWSR12_REGSR - 1])
 465                 & FSL_CHASSIS3_IIC5_PMUX_MASK;
 466         iic5_pmux >>= FSL_CHASSIS3_IIC5_PMUX_SHIFT;
 467
 468         if (iic5_pmux == IIC5_PMUX_SPI3) {
 469                 /* - Routes {SDHC1_DAT4} to SPI3 devices as {SPI3_M_CS0_B}. */
 470                 reg11 = QIXIS_READ(brdcfg[11]);
 471                 reg11 = SET_CFG_MUX2_SDHC1_SPI(reg11, 0x10);
 472                 QIXIS_WRITE(brdcfg[11], reg11);
 473
 474                 /* - Routes {SDHC1_DAT5, SDHC1_DAT6} nowhere.
 475                  * {SDHC1_DAT7, SDHC1_DS } to {nothing, SPI3_M0_CLK }.
 476                  * {I2C5_SCL, I2C5_SDA } to {SPI3_M0_MOSI, SPI3_M0_MISO}.
 477                  */
 478                 reg11 = QIXIS_READ(brdcfg[11]);
 479                 reg11 = SET_CFG_MUX3_SDHC1_SPI(reg11, 0x01);
 480                 QIXIS_WRITE(brdcfg[11], reg11);
 481         } else {
 482                 /*
 483                  * If {SDHC1_DAT4} has been configured to route to SDHC1_VS,
 484                  * do not change it.
 485                  * Otherwise route {SDHC1_DAT4} to SDHC1 adapter slot.
 486                  */
 487                 reg11 = QIXIS_READ(brdcfg[11]);
 488                 if ((reg11 & 0x30) != 0x30) {
 489                         reg11 = SET_CFG_MUX2_SDHC1_SPI(reg11, 0x00);
 490                         QIXIS_WRITE(brdcfg[11], reg11);
 491                 }
 492
 493                 /* - Routes {SDHC1_DAT5, SDHC1_DAT6} to SDHC1 adapter slot.
 494                  * {SDHC1_DAT7, SDHC1_DS } to SDHC1 adapter slot.
 495                  * {I2C5_SCL, I2C5_SDA } to SDHC1 adapter slot.
 496                  */
 497                 reg11 = QIXIS_READ(brdcfg[11]);
 498                 reg11 = SET_CFG_MUX3_SDHC1_SPI(reg11, 0x00);
 499                 QIXIS_WRITE(brdcfg[11], reg11);
 500         }
 501
 502         return 0;
 503 }
 504 #elif defined(CONFIG_TARGET_LX2160ARDB)
 505 int config_board_mux(void)
 506 {
 507         u8 brdcfg;
 508
 509         brdcfg = QIXIS_READ(brdcfg[4]);
 510         /* The BRDCFG4 register controls general board configuration.
 511          *|-------------------------------------------|
 512          *|Field  | Function                          |
 513          *|-------------------------------------------|
 514          *|5      | CAN I/O Enable (net CFG_CAN_EN_B):|
 515          *|CAN_EN | 0= CAN transceivers are disabled. |
 516          *|       | 1= CAN transceivers are enabled.  |
 517          *|-------------------------------------------|
 518          */
 519         brdcfg |= BIT_MASK(5);
 520         QIXIS_WRITE(brdcfg[4], brdcfg);
 521
 522         return 0;
 523 }
 524 #else
 525 int config_board_mux(void)
 526 {
 527         return 0;
 528 }
 529 #endif
 530
 531 unsigned long get_board_sys_clk(void)
 532 {
 533 #ifdef CONFIG_TARGET_LX2160AQDS
 534         u8 sysclk_conf = QIXIS_READ(brdcfg[1]);
 535
 536         switch (sysclk_conf & 0x03) {
 537         case QIXIS_SYSCLK_100:
 538                 return 100000000;
 539         case QIXIS_SYSCLK_125:
 540                 return 125000000;
 541         case QIXIS_SYSCLK_133:
 542                 return 133333333;
 543         }
 544         return 100000000;
 545 #else
 546         return 100000000;
 547 #endif
 548 }
 549
 550 unsigned long get_board_ddr_clk(void)
 551 {
 552 #ifdef CONFIG_TARGET_LX2160AQDS
 553         u8 ddrclk_conf = QIXIS_READ(brdcfg[1]);
 554
 555         switch ((ddrclk_conf & 0x30) >> 4) {
 556         case QIXIS_DDRCLK_100:
 557                 return 100000000;
 558         case QIXIS_DDRCLK_125:
 559                 return 125000000;
 560         case QIXIS_DDRCLK_133:
 561                 return 133333333;
 562         }
 563         return 100000000;
 564 #else
 565         return 100000000;
 566 #endif
 567 }
 568
 569 int board_init(void)
 570 {
 571 #if defined(CONFIG_FSL_MC_ENET) && defined(CONFIG_TARGET_LX2160ARDB)
 572         u32 __iomem *irq_ccsr = (u32 __iomem *)ISC_BASE;
 573 #endif
 574 #ifdef CONFIG_ENV_IS_NOWHERE
 575         gd->env_addr = (ulong)&default_environment[0];
 576 #endif
 577
 578         select_i2c_ch_pca9547(I2C_MUX_CH_DEFAULT);
 579
 580 #if defined(CONFIG_FSL_MC_ENET) && defined(CONFIG_TARGET_LX2160ARDB)
 581         /* invert AQR107 IRQ pins polarity */
 582         out_le32(irq_ccsr + IRQCR_OFFSET / 4, AQR107_IRQ_MASK);
 583 #endif
 584
 585 #ifdef CONFIG_FSL_CAAM
 586         sec_init();
 587 #endif
 588
 589 #if !defined(CONFIG_SYS_EARLY_PCI_INIT) && defined(CONFIG_DM_ETH)
 590         pci_init();
 591 #endif
 592         return 0;
 593 }
 594
 595 void detail_board_ddr_info(void)
 596 {
 597         int i;
 598         u64 ddr_size = 0;
 599
 600         puts("\nDDR    ");
 601         for (i = 0; i < CONFIG_NR_DRAM_BANKS; i++)
 602                 ddr_size += gd->bd->bi_dram[i].size;
 603         print_size(ddr_size, "");
 604         print_ddr_info(0);
 605 }
 606
 607 #ifdef CONFIG_MISC_INIT_R
 608 int misc_init_r(void)
 609 {
 610         config_board_mux();
 611
 612         return 0;
 613 }
 614 #endif
 615
 616 #ifdef CONFIG_FSL_MC_ENET
 617 extern int fdt_fixup_board_phy(void *fdt);
 618
 619 void fdt_fixup_board_enet(void *fdt)
 620 {
 621         int offset;
 622
 623         offset = fdt_path_offset(fdt, "/soc/fsl-mc");
 624
 625         if (offset < 0)
 626                 offset = fdt_path_offset(fdt, "/fsl-mc");
 627
 628         if (offset < 0) {
 629                 printf("%s: fsl-mc node not found in device tree (error %d)\n",
 630                        __func__, offset);
 631                 return;
 632         }
 633
 634         if (get_mc_boot_status() == 0 &&
 635             (is_lazy_dpl_addr_valid() || get_dpl_apply_status() == 0)) {
 636                 fdt_status_okay(fdt, offset);
 637 #ifndef CONFIG_DM_ETH
 638                 fdt_fixup_board_phy(fdt);
 639 #endif
 640         } else {
 641                 fdt_status_fail(fdt, offset);
 642         }
 643 }
 644
 645 void board_quiesce_devices(void)
 646 {
 647         fsl_mc_ldpaa_exit(gd->bd);
 648 }
 649 #endif
 650
 651 #ifdef CONFIG_OF_BOARD_SETUP
 652 int ft_board_setup(void *blob, struct bd_info *bd)
 653 {
 654         int i;
 655         u16 mc_memory_bank = 0;
 656
 657         u64 *base;
 658         u64 *size;
 659         u64 mc_memory_base = 0;
 660         u64 mc_memory_size = 0;
 661         u16 total_memory_banks;
 662
 663         ft_cpu_setup(blob, bd);
 664
 665         fdt_fixup_mc_ddr(&mc_memory_base, &mc_memory_size);
 666
 667         if (mc_memory_base != 0)
 668                 mc_memory_bank++;
 669
 670         total_memory_banks = CONFIG_NR_DRAM_BANKS + mc_memory_bank;
 671
 672         base = calloc(total_memory_banks, sizeof(u64));
 673         size = calloc(total_memory_banks, sizeof(u64));
 674
 675         /* fixup DT for the three GPP DDR banks */
 676         for (i = 0; i < CONFIG_NR_DRAM_BANKS; i++) {
 677                 base[i] = gd->bd->bi_dram[i].start;
 678                 size[i] = gd->bd->bi_dram[i].size;
 679         }
 680
 681 #ifdef CONFIG_RESV_RAM
 682         /* reduce size if reserved memory is within this bank */
 683         if (gd->arch.resv_ram >= base[0] &&
 684             gd->arch.resv_ram < base[0] + size[0])
 685                 size[0] = gd->arch.resv_ram - base[0];
 686         else if (gd->arch.resv_ram >= base[1] &&
 687                  gd->arch.resv_ram < base[1] + size[1])
 688                 size[1] = gd->arch.resv_ram - base[1];
 689         else if (gd->arch.resv_ram >= base[2] &&
 690                  gd->arch.resv_ram < base[2] + size[2])
 691                 size[2] = gd->arch.resv_ram - base[2];
 692 #endif
 693
 694         if (mc_memory_base != 0) {
 695                 for (i = 0; i <= total_memory_banks; i++) {
 696                         if (base[i] == 0 && size[i] == 0) {
 697                                 base[i] = mc_memory_base;
 698                                 size[i] = mc_memory_size;
 699                                 break;
 700                         }
 701                 }
 702         }
 703
 704         fdt_fixup_memory_banks(blob, base, size, total_memory_banks);
 705
 706 #ifdef CONFIG_USB
 707         fsl_fdt_fixup_dr_usb(blob, bd);
 708 #endif
 709
 710 #ifdef CONFIG_FSL_MC_ENET
 711         fdt_fsl_mc_fixup_iommu_map_entry(blob);
 712         fdt_fixup_board_enet(blob);
 713 #endif
 714         fdt_fixup_icid(blob);
 715
 716         return 0;
 717 }
 718 #endif
 719
 720 void qixis_dump_switch(void)
 721 {
 722         int i, nr_of_cfgsw;
 723
 724         QIXIS_WRITE(cms[0], 0x00);
 725         nr_of_cfgsw = QIXIS_READ(cms[1]);
 726
 727         puts("DIP switch settings dump:\n");
 728         for (i = 1; i <= nr_of_cfgsw; i++) {
 729                 QIXIS_WRITE(cms[0], i);
 730                 printf("SW%d = (0x%02x)\n", i, QIXIS_READ(cms[1]));
 731         }
 732 }