board/freescale/lx2160a/lx2160a.c

   1 // SPDX-License-Identifier: GPL-2.0+
   2 /*
   3  * Copyright 2018-2019 NXP
   4  */
   5
   6 #include <common.h>
   7 #include <dm.h>
   8 #include <dm/platform_data/serial_pl01x.h>
   9 #include <i2c.h>
  10 #include <malloc.h>
  11 #include <errno.h>
  12 #include <netdev.h>
  13 #include <fsl_ddr.h>
  14 #include <fsl_sec.h>
  15 #include <asm/io.h>
  16 #include <fdt_support.h>
  17 #include <linux/libfdt.h>
  18 #include <fsl-mc/fsl_mc.h>
  19 #include <env_internal.h>
  20 #include <efi_loader.h>
  21 #include <asm/arch/mmu.h>
  22 #include <hwconfig.h>
  23 #include <asm/arch/fsl_serdes.h>
  24 #include <asm/arch/soc.h>
  25 #include "../common/qixis.h"
  26 #include "../common/vid.h"
  27 #include <fsl_immap.h>
  28
  29 #ifdef CONFIG_EMC2305
  30 #include "../common/emc2305.h"
  31 #endif
  32
  33 #ifdef CONFIG_TARGET_LX2160AQDS
  34 #define CFG_MUX_I2C_SDHC(reg, value)            ((reg & 0x3f) | value)
  35 #define SET_CFG_MUX1_SDHC1_SDHC(reg)            (reg & 0x3f)
  36 #define SET_CFG_MUX2_SDHC1_SPI(reg, value)      ((reg & 0xcf) | value)
  37 #define SET_CFG_MUX3_SDHC1_SPI(reg, value)      ((reg & 0xf8) | value)
  38 #define SET_CFG_MUX_SDHC2_DSPI(reg, value)      ((reg & 0xf8) | value)
  39 #define SET_CFG_MUX1_SDHC1_DSPI(reg, value)     ((reg & 0x3f) | value)
  40 #define SDHC1_BASE_PMUX_DSPI                    2
  41 #define SDHC2_BASE_PMUX_DSPI                    2
  42 #define IIC5_PMUX_SPI3                          3
  43 #endif /* CONFIG_TARGET_LX2160AQDS */
  44
  45 DECLARE_GLOBAL_DATA_PTR;
  46
  47 static struct pl01x_serial_platdata serial0 = {
  48 #if CONFIG_CONS_INDEX == 0
  49         .base = CONFIG_SYS_SERIAL0,
  50 #elif CONFIG_CONS_INDEX == 1
  51         .base = CONFIG_SYS_SERIAL1,
  52 #else
  53 #error "Unsupported console index value."
  54 #endif
  55         .type = TYPE_PL011,
  56 };
  57
  58 U_BOOT_DEVICE(nxp_serial0) = {
  59         .name = "serial_pl01x",
  60         .platdata = &serial0,
  61 };
  62
  63 static struct pl01x_serial_platdata serial1 = {
  64         .base = CONFIG_SYS_SERIAL1,
  65         .type = TYPE_PL011,
  66 };
  67
  68 U_BOOT_DEVICE(nxp_serial1) = {
  69         .name = "serial_pl01x",
  70         .platdata = &serial1,
  71 };
  72
  73 int select_i2c_ch_pca9547(u8 ch)
  74 {
  75         int ret;
  76
  77 #ifndef CONFIG_DM_I2C
  78         ret = i2c_write(I2C_MUX_PCA_ADDR_PRI, 0, 1, &ch, 1);
  79 #else
  80         struct udevice *dev;
  81
  82         ret = i2c_get_chip_for_busnum(0, I2C_MUX_PCA_ADDR_PRI, 1, &dev);
  83         if (!ret)
  84                 ret = dm_i2c_write(dev, 0, &ch, 1);
  85 #endif
  86         if (ret) {
  87                 puts("PCA: failed to select proper channel\n");
  88                 return ret;
  89         }
  90
  91         return 0;
  92 }
  93
  94 static void uart_get_clock(void)
  95 {
  96         serial0.clock = get_serial_clock();
  97         serial1.clock = get_serial_clock();
  98 }
  99
 100 int board_early_init_f(void)
 101 {
 102 #ifdef CONFIG_SYS_I2C_EARLY_INIT
 103         i2c_early_init_f();
 104 #endif
 105         /* get required clock for UART IP */
 106         uart_get_clock();
 107
 108 #ifdef CONFIG_EMC2305
 109         select_i2c_ch_pca9547(I2C_MUX_CH_EMC2305);
 110         emc2305_init();
 111         set_fan_speed(I2C_EMC2305_PWM);
 112         select_i2c_ch_pca9547(I2C_MUX_CH_DEFAULT);
 113 #endif
 114
 115         fsl_lsch3_early_init_f();
 116         return 0;
 117 }
 118
 119 #if defined(CONFIG_TARGET_LX2160AQDS)
 120 void esdhc_dspi_status_fixup(void *blob)
 121 {
 122         const char esdhc0_path[] = "/soc/esdhc@2140000";
 123         const char esdhc1_path[] = "/soc/esdhc@2150000";
 124         const char dspi0_path[] = "/soc/dspi@2100000";
 125         const char dspi1_path[] = "/soc/dspi@2110000";
 126         const char dspi2_path[] = "/soc/dspi@2120000";
 127
 128         struct ccsr_gur __iomem *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR);
 129         u32 sdhc1_base_pmux;
 130         u32 sdhc2_base_pmux;
 131         u32 iic5_pmux;
 132
 133         /* Check RCW field sdhc1_base_pmux to enable/disable
 134          * esdhc0/dspi0 DT node
 135          */
 136         sdhc1_base_pmux = gur_in32(&gur->rcwsr[FSL_CHASSIS3_RCWSR12_REGSR - 1])
 137                 & FSL_CHASSIS3_SDHC1_BASE_PMUX_MASK;
 138         sdhc1_base_pmux >>= FSL_CHASSIS3_SDHC1_BASE_PMUX_SHIFT;
 139
 140         if (sdhc1_base_pmux == SDHC1_BASE_PMUX_DSPI) {
 141                 do_fixup_by_path(blob, dspi0_path, "status", "okay",
 142                                  sizeof("okay"), 1);
 143                 do_fixup_by_path(blob, esdhc0_path, "status", "disabled",
 144                                  sizeof("disabled"), 1);
 145         } else {
 146                 do_fixup_by_path(blob, esdhc0_path, "status", "okay",
 147                                  sizeof("okay"), 1);
 148                 do_fixup_by_path(blob, dspi0_path, "status", "disabled",
 149                                  sizeof("disabled"), 1);
 150         }
 151
 152         /* Check RCW field sdhc2_base_pmux to enable/disable
 153          * esdhc1/dspi1 DT node
 154          */
 155         sdhc2_base_pmux = gur_in32(&gur->rcwsr[FSL_CHASSIS3_RCWSR13_REGSR - 1])
 156                 & FSL_CHASSIS3_SDHC2_BASE_PMUX_MASK;
 157         sdhc2_base_pmux >>= FSL_CHASSIS3_SDHC2_BASE_PMUX_SHIFT;
 158
 159         if (sdhc2_base_pmux == SDHC2_BASE_PMUX_DSPI) {
 160                 do_fixup_by_path(blob, dspi1_path, "status", "okay",
 161                                  sizeof("okay"), 1);
 162                 do_fixup_by_path(blob, esdhc1_path, "status", "disabled",
 163                                  sizeof("disabled"), 1);
 164         } else {
 165                 do_fixup_by_path(blob, esdhc1_path, "status", "okay",
 166                                  sizeof("okay"), 1);
 167                 do_fixup_by_path(blob, dspi1_path, "status", "disabled",
 168                                  sizeof("disabled"), 1);
 169         }
 170
 171         /* Check RCW field IIC5 to enable dspi2 DT node */
 172         iic5_pmux = gur_in32(&gur->rcwsr[FSL_CHASSIS3_RCWSR12_REGSR - 1])
 173                 & FSL_CHASSIS3_IIC5_PMUX_MASK;
 174         iic5_pmux >>= FSL_CHASSIS3_IIC5_PMUX_SHIFT;
 175
 176         if (iic5_pmux == IIC5_PMUX_SPI3) {
 177                 do_fixup_by_path(blob, dspi2_path, "status", "okay",
 178                                  sizeof("okay"), 1);
 179         }
 180 }
 181 #endif
 182
 183 int esdhc_status_fixup(void *blob, const char *compat)
 184 {
 185 #if defined(CONFIG_TARGET_LX2160AQDS)
 186         /* Enable esdhc and dspi DT nodes based on RCW fields */
 187         esdhc_dspi_status_fixup(blob);
 188 #else
 189         /* Enable both esdhc DT nodes for LX2160ARDB */
 190         do_fixup_by_compat(blob, compat, "status", "okay",
 191                            sizeof("okay"), 1);
 192 #endif
 193         return 0;
 194 }
 195
 196 #if defined(CONFIG_VID)
 197 int i2c_multiplexer_select_vid_channel(u8 channel)
 198 {
 199         return select_i2c_ch_pca9547(channel);
 200 }
 201
 202 int init_func_vid(void)
 203 {
 204         if (adjust_vdd(0) < 0)
 205                 printf("core voltage not adjusted\n");
 206
 207         return 0;
 208 }
 209 #endif
 210
 211 int checkboard(void)
 212 {
 213         enum boot_src src = get_boot_src();
 214         char buf[64];
 215         u8 sw;
 216 #ifdef CONFIG_TARGET_LX2160AQDS
 217         int clock;
 218         static const char *const freq[] = {"100", "125", "156.25",
 219                                            "161.13", "322.26", "", "", "",
 220                                            "", "", "", "", "", "", "",
 221                                            "100 separate SSCG"};
 222 #endif
 223
 224         cpu_name(buf);
 225 #ifdef CONFIG_TARGET_LX2160AQDS
 226         printf("Board: %s-QDS, ", buf);
 227 #else
 228         printf("Board: %s-RDB, ", buf);
 229 #endif
 230
 231         sw = QIXIS_READ(arch);
 232         printf("Board version: %c, boot from ", (sw & 0xf) - 1 + 'A');
 233
 234         if (src == BOOT_SOURCE_SD_MMC) {
 235                 puts("SD\n");
 236         } else {
 237                 sw = QIXIS_READ(brdcfg[0]);
 238                 sw = (sw >> QIXIS_XMAP_SHIFT) & QIXIS_XMAP_MASK;
 239                 switch (sw) {
 240                 case 0:
 241                 case 4:
 242                         puts("FlexSPI DEV#0\n");
 243                         break;
 244                 case 1:
 245                         puts("FlexSPI DEV#1\n");
 246                         break;
 247                 case 2:
 248                 case 3:
 249                         puts("FlexSPI EMU\n");
 250                         break;
 251                 default:
 252                         printf("invalid setting, xmap: %d\n", sw);
 253                         break;
 254                 }
 255         }
 256 #ifdef CONFIG_TARGET_LX2160AQDS
 257         printf("FPGA: v%d (%s), build %d",
 258                (int)QIXIS_READ(scver), qixis_read_tag(buf),
 259                (int)qixis_read_minor());
 260         /* the timestamp string contains "\n" at the end */
 261         printf(" on %s", qixis_read_time(buf));
 262
 263         puts("SERDES1 Reference : ");
 264         sw = QIXIS_READ(brdcfg[2]);
 265         clock = sw >> 4;
 266         printf("Clock1 = %sMHz ", freq[clock]);
 267         clock = sw & 0x0f;
 268         printf("Clock2 = %sMHz", freq[clock]);
 269
 270         sw = QIXIS_READ(brdcfg[3]);
 271         puts("\nSERDES2 Reference : ");
 272         clock = sw >> 4;
 273         printf("Clock1 = %sMHz ", freq[clock]);
 274         clock = sw & 0x0f;
 275         printf("Clock2 = %sMHz", freq[clock]);
 276
 277         sw = QIXIS_READ(brdcfg[12]);
 278         puts("\nSERDES3 Reference : ");
 279         clock = sw >> 4;
 280         printf("Clock1 = %sMHz Clock2 = %sMHz\n", freq[clock], freq[clock]);
 281 #else
 282         printf("FPGA: v%d.%d\n", QIXIS_READ(scver), QIXIS_READ(tagdata));
 283
 284         puts("SERDES1 Reference: Clock1 = 161.13MHz Clock2 = 161.13MHz\n");
 285         puts("SERDES2 Reference: Clock1 = 100MHz Clock2 = 100MHz\n");
 286         puts("SERDES3 Reference: Clock1 = 100MHz Clock2 = 100Hz\n");
 287 #endif
 288         return 0;
 289 }
 290
 291 #ifdef CONFIG_TARGET_LX2160AQDS
 292 /*
 293  * implementation of CONFIG_ESDHC_DETECT_QUIRK Macro.
 294  */
 295 u8 qixis_esdhc_detect_quirk(void)
 296 {
 297         /* for LX2160AQDS res1[1] @ offset 0x1A is SDHC1 Control/Status (SDHC1)
 298          * SDHC1 Card ID:
 299          * Specifies the type of card installed in the SDHC1 adapter slot.
 300          * 000= (reserved)
 301          * 001= eMMC V4.5 adapter is installed.
 302          * 010= SD/MMC 3.3V adapter is installed.
 303          * 011= eMMC V4.4 adapter is installed.
 304          * 100= eMMC V5.0 adapter is installed.
 305          * 101= MMC card/Legacy (3.3V) adapter is installed.
 306          * 110= SDCard V2/V3 adapter installed.
 307          * 111= no adapter is installed.
 308          */
 309         return ((QIXIS_READ(res1[1]) & QIXIS_SDID_MASK) !=
 310                  QIXIS_ESDHC_NO_ADAPTER);
 311 }
 312
 313 int config_board_mux(void)
 314 {
 315         u8 reg11, reg5, reg13;
 316         struct ccsr_gur __iomem *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR);
 317         u32 sdhc1_base_pmux;
 318         u32 sdhc2_base_pmux;
 319         u32 iic5_pmux;
 320
 321         /* Routes {I2C2_SCL, I2C2_SDA} to SDHC1 as {SDHC1_CD_B, SDHC1_WP}.
 322          * Routes {I2C3_SCL, I2C3_SDA} to CAN transceiver as {CAN1_TX,CAN1_RX}.
 323          * Routes {I2C4_SCL, I2C4_SDA} to CAN transceiver as {CAN2_TX,CAN2_RX}.
 324          * Qixis and remote systems are isolated from the I2C1 bus.
 325          * Processor connections are still available.
 326          * SPI2 CS2_B controls EN25S64 SPI memory device.
 327          * SPI3 CS2_B controls EN25S64 SPI memory device.
 328          * EC2 connects to PHY #2 using RGMII protocol.
 329          * CLK_OUT connects to FPGA for clock measurement.
 330          */
 331
 332         reg5 = QIXIS_READ(brdcfg[5]);
 333         reg5 = CFG_MUX_I2C_SDHC(reg5, 0x40);
 334         QIXIS_WRITE(brdcfg[5], reg5);
 335
 336         /* Check RCW field sdhc1_base_pmux
 337          * esdhc0 : sdhc1_base_pmux = 0
 338          * dspi0  : sdhc1_base_pmux = 2
 339          */
 340         sdhc1_base_pmux = gur_in32(&gur->rcwsr[FSL_CHASSIS3_RCWSR12_REGSR - 1])
 341                 & FSL_CHASSIS3_SDHC1_BASE_PMUX_MASK;
 342         sdhc1_base_pmux >>= FSL_CHASSIS3_SDHC1_BASE_PMUX_SHIFT;
 343
 344         if (sdhc1_base_pmux == SDHC1_BASE_PMUX_DSPI) {
 345                 reg11 = QIXIS_READ(brdcfg[11]);
 346                 reg11 = SET_CFG_MUX1_SDHC1_DSPI(reg11, 0x40);
 347                 QIXIS_WRITE(brdcfg[11], reg11);
 348         } else {
 349                 /* - Routes {SDHC1_CMD, SDHC1_CLK } to SDHC1 adapter slot.
 350                  *          {SDHC1_DAT3, SDHC1_DAT2} to SDHC1 adapter slot.
 351                  *          {SDHC1_DAT1, SDHC1_DAT0} to SDHC1 adapter slot.
 352                  */
 353                 reg11 = QIXIS_READ(brdcfg[11]);
 354                 reg11 = SET_CFG_MUX1_SDHC1_SDHC(reg11);
 355                 QIXIS_WRITE(brdcfg[11], reg11);
 356         }
 357
 358         /* Check RCW field sdhc2_base_pmux
 359          * esdhc1 : sdhc2_base_pmux = 0 (default)
 360          * dspi1  : sdhc2_base_pmux = 2
 361          */
 362         sdhc2_base_pmux = gur_in32(&gur->rcwsr[FSL_CHASSIS3_RCWSR13_REGSR - 1])
 363                 & FSL_CHASSIS3_SDHC2_BASE_PMUX_MASK;
 364         sdhc2_base_pmux >>= FSL_CHASSIS3_SDHC2_BASE_PMUX_SHIFT;
 365
 366         if (sdhc2_base_pmux == SDHC2_BASE_PMUX_DSPI) {
 367                 reg13 = QIXIS_READ(brdcfg[13]);
 368                 reg13 = SET_CFG_MUX_SDHC2_DSPI(reg13, 0x01);
 369                 QIXIS_WRITE(brdcfg[13], reg13);
 370         } else {
 371                 reg13 = QIXIS_READ(brdcfg[13]);
 372                 reg13 = SET_CFG_MUX_SDHC2_DSPI(reg13, 0x00);
 373                 QIXIS_WRITE(brdcfg[13], reg13);
 374         }
 375
 376         /* Check RCW field IIC5 to enable dspi2 DT nodei
 377          * dspi2: IIC5 = 3
 378          */
 379         iic5_pmux = gur_in32(&gur->rcwsr[FSL_CHASSIS3_RCWSR12_REGSR - 1])
 380                 & FSL_CHASSIS3_IIC5_PMUX_MASK;
 381         iic5_pmux >>= FSL_CHASSIS3_IIC5_PMUX_SHIFT;
 382
 383         if (iic5_pmux == IIC5_PMUX_SPI3) {
 384                 /* - Routes {SDHC1_DAT4} to SPI3 devices as {SPI3_M_CS0_B}. */
 385                 reg11 = QIXIS_READ(brdcfg[11]);
 386                 reg11 = SET_CFG_MUX2_SDHC1_SPI(reg11, 0x10);
 387                 QIXIS_WRITE(brdcfg[11], reg11);
 388
 389                 /* - Routes {SDHC1_DAT5, SDHC1_DAT6} nowhere.
 390                  * {SDHC1_DAT7, SDHC1_DS } to {nothing, SPI3_M0_CLK }.
 391                  * {I2C5_SCL, I2C5_SDA } to {SPI3_M0_MOSI, SPI3_M0_MISO}.
 392                  */
 393                 reg11 = QIXIS_READ(brdcfg[11]);
 394                 reg11 = SET_CFG_MUX3_SDHC1_SPI(reg11, 0x01);
 395                 QIXIS_WRITE(brdcfg[11], reg11);
 396         } else {
 397                 /*  Routes {SDHC1_DAT4} to SDHC1 adapter slot */
 398                 reg11 = QIXIS_READ(brdcfg[11]);
 399                 reg11 = SET_CFG_MUX2_SDHC1_SPI(reg11, 0x00);
 400                 QIXIS_WRITE(brdcfg[11], reg11);
 401
 402                 /* - Routes {SDHC1_DAT5, SDHC1_DAT6} to SDHC1 adapter slot.
 403                  * {SDHC1_DAT7, SDHC1_DS } to SDHC1 adapter slot.
 404                  * {I2C5_SCL, I2C5_SDA } to SDHC1 adapter slot.
 405                  */
 406                 reg11 = QIXIS_READ(brdcfg[11]);
 407                 reg11 = SET_CFG_MUX3_SDHC1_SPI(reg11, 0x00);
 408                 QIXIS_WRITE(brdcfg[11], reg11);
 409         }
 410
 411         return 0;
 412 }
 413 #else
 414 int config_board_mux(void)
 415 {
 416         return 0;
 417 }
 418 #endif
 419
 420 unsigned long get_board_sys_clk(void)
 421 {
 422 #ifdef CONFIG_TARGET_LX2160AQDS
 423         u8 sysclk_conf = QIXIS_READ(brdcfg[1]);
 424
 425         switch (sysclk_conf & 0x03) {
 426         case QIXIS_SYSCLK_100:
 427                 return 100000000;
 428         case QIXIS_SYSCLK_125:
 429                 return 125000000;
 430         case QIXIS_SYSCLK_133:
 431                 return 133333333;
 432         }
 433         return 100000000;
 434 #else
 435         return 100000000;
 436 #endif
 437 }
 438
 439 unsigned long get_board_ddr_clk(void)
 440 {
 441 #ifdef CONFIG_TARGET_LX2160AQDS
 442         u8 ddrclk_conf = QIXIS_READ(brdcfg[1]);
 443
 444         switch ((ddrclk_conf & 0x30) >> 4) {
 445         case QIXIS_DDRCLK_100:
 446                 return 100000000;
 447         case QIXIS_DDRCLK_125:
 448                 return 125000000;
 449         case QIXIS_DDRCLK_133:
 450                 return 133333333;
 451         }
 452         return 100000000;
 453 #else
 454         return 100000000;
 455 #endif
 456 }
 457
 458 int board_init(void)
 459 {
 460 #if defined(CONFIG_FSL_MC_ENET) && defined(CONFIG_TARGET_LX2160ARDB)
 461         u32 __iomem *irq_ccsr = (u32 __iomem *)ISC_BASE;
 462 #endif
 463 #ifdef CONFIG_ENV_IS_NOWHERE
 464         gd->env_addr = (ulong)&default_environment[0];
 465 #endif
 466
 467         select_i2c_ch_pca9547(I2C_MUX_CH_DEFAULT);
 468
 469 #if defined(CONFIG_FSL_MC_ENET) && defined(CONFIG_TARGET_LX2160ARDB)
 470         /* invert AQR107 IRQ pins polarity */
 471         out_le32(irq_ccsr + IRQCR_OFFSET / 4, AQR107_IRQ_MASK);
 472 #endif
 473
 474 #ifdef CONFIG_FSL_CAAM
 475         sec_init();
 476 #endif
 477
 478         return 0;
 479 }
 480
 481 void detail_board_ddr_info(void)
 482 {
 483         int i;
 484         u64 ddr_size = 0;
 485
 486         puts("\nDDR    ");
 487         for (i = 0; i < CONFIG_NR_DRAM_BANKS; i++)
 488                 ddr_size += gd->bd->bi_dram[i].size;
 489         print_size(ddr_size, "");
 490         print_ddr_info(0);
 491 }
 492
 493 #if defined(CONFIG_ARCH_MISC_INIT)
 494 int arch_misc_init(void)
 495 {
 496         config_board_mux();
 497
 498         return 0;
 499 }
 500 #endif
 501
 502 #ifdef CONFIG_FSL_MC_ENET
 503 extern int fdt_fixup_board_phy(void *fdt);
 504
 505 void fdt_fixup_board_enet(void *fdt)
 506 {
 507         int offset;
 508
 509         offset = fdt_path_offset(fdt, "/soc/fsl-mc");
 510
 511         if (offset < 0)
 512                 offset = fdt_path_offset(fdt, "/fsl-mc");
 513
 514         if (offset < 0) {
 515                 printf("%s: fsl-mc node not found in device tree (error %d)\n",
 516                        __func__, offset);
 517                 return;
 518         }
 519
 520         if (get_mc_boot_status() == 0 &&
 521             (is_lazy_dpl_addr_valid() || get_dpl_apply_status() == 0)) {
 522                 fdt_status_okay(fdt, offset);
 523                 fdt_fixup_board_phy(fdt);
 524         } else {
 525                 fdt_status_fail(fdt, offset);
 526         }
 527 }
 528
 529 void board_quiesce_devices(void)
 530 {
 531         fsl_mc_ldpaa_exit(gd->bd);
 532 }
 533 #endif
 534
 535 #ifdef CONFIG_OF_BOARD_SETUP
 536
 537 int ft_board_setup(void *blob, bd_t *bd)
 538 {
 539         int i;
 540         u16 mc_memory_bank = 0;
 541
 542         u64 *base;
 543         u64 *size;
 544         u64 mc_memory_base = 0;
 545         u64 mc_memory_size = 0;
 546         u16 total_memory_banks;
 547
 548         ft_cpu_setup(blob, bd);
 549
 550         fdt_fixup_mc_ddr(&mc_memory_base, &mc_memory_size);
 551
 552         if (mc_memory_base != 0)
 553                 mc_memory_bank++;
 554
 555         total_memory_banks = CONFIG_NR_DRAM_BANKS + mc_memory_bank;
 556
 557         base = calloc(total_memory_banks, sizeof(u64));
 558         size = calloc(total_memory_banks, sizeof(u64));
 559
 560         /* fixup DT for the three GPP DDR banks */
 561         for (i = 0; i < CONFIG_NR_DRAM_BANKS; i++) {
 562                 base[i] = gd->bd->bi_dram[i].start;
 563                 size[i] = gd->bd->bi_dram[i].size;
 564         }
 565
 566 #ifdef CONFIG_RESV_RAM
 567         /* reduce size if reserved memory is within this bank */
 568         if (gd->arch.resv_ram >= base[0] &&
 569             gd->arch.resv_ram < base[0] + size[0])
 570                 size[0] = gd->arch.resv_ram - base[0];
 571         else if (gd->arch.resv_ram >= base[1] &&
 572                  gd->arch.resv_ram < base[1] + size[1])
 573                 size[1] = gd->arch.resv_ram - base[1];
 574         else if (gd->arch.resv_ram >= base[2] &&
 575                  gd->arch.resv_ram < base[2] + size[2])
 576                 size[2] = gd->arch.resv_ram - base[2];
 577 #endif
 578
 579         if (mc_memory_base != 0) {
 580                 for (i = 0; i <= total_memory_banks; i++) {
 581                         if (base[i] == 0 && size[i] == 0) {
 582                                 base[i] = mc_memory_base;
 583                                 size[i] = mc_memory_size;
 584                                 break;
 585                         }
 586                 }
 587         }
 588
 589         fdt_fixup_memory_banks(blob, base, size, total_memory_banks);
 590
 591 #ifdef CONFIG_USB
 592         fsl_fdt_fixup_dr_usb(blob, bd);
 593 #endif
 594
 595 #ifdef CONFIG_FSL_MC_ENET
 596         fdt_fsl_mc_fixup_iommu_map_entry(blob);
 597         fdt_fixup_board_enet(blob);
 598 #endif
 599
 600         return 0;
 601 }
 602 #endif
 603
 604 void qixis_dump_switch(void)
 605 {
 606         int i, nr_of_cfgsw;
 607
 608         QIXIS_WRITE(cms[0], 0x00);
 609         nr_of_cfgsw = QIXIS_READ(cms[1]);
 610
 611         puts("DIP switch settings dump:\n");
 612         for (i = 1; i <= nr_of_cfgsw; i++) {
 613                 QIXIS_WRITE(cms[0], i);
 614                 printf("SW%d = (0x%02x)\n", i, QIXIS_READ(cms[1]));
 615         }
 616 }