board/freescale/lx2160a/lx2160a.c

   1 // SPDX-License-Identifier: GPL-2.0+
   2 /*
   3  * Copyright 2018-2021 NXP
   4  */
   5
   6 #include <common.h>
   7 #include <clock_legacy.h>
   8 #include <dm.h>
   9 #include <init.h>
  10 #include <asm/global_data.h>
  11 #include <dm/platform_data/serial_pl01x.h>
  12 #include <i2c.h>
  13 #include <malloc.h>
  14 #include <errno.h>
  15 #include <netdev.h>
  16 #include <fsl_ddr.h>
  17 #include <asm/io.h>
  18 #include <fdt_support.h>
  19 #include <linux/bitops.h>
  20 #include <linux/libfdt.h>
  21 #include <linux/delay.h>
  22 #include <fsl-mc/fsl_mc.h>
  23 #include <env_internal.h>
  24 #include <efi_loader.h>
  25 #include <asm/arch/mmu.h>
  26 #include <hwconfig.h>
  27 #include <asm/arch/clock.h>
  28 #include <asm/arch/config.h>
  29 #include <asm/arch/fsl_serdes.h>
  30 #include <asm/arch/soc.h>
  31 #include "../common/i2c_mux.h"
  32
  33 #include "../common/qixis.h"
  34 #include "../common/vid.h"
  35 #include <fsl_immap.h>
  36 #include <asm/arch-fsl-layerscape/fsl_icid.h>
  37 #include "lx2160a.h"
  38
  39 #ifdef CONFIG_EMC2305
  40 #include "../common/emc2305.h"
  41 #endif
  42
  43 #if defined(CONFIG_TARGET_LX2160AQDS) || defined(CONFIG_TARGET_LX2162AQDS)
  44 #define CFG_MUX_I2C_SDHC(reg, value)            ((reg & 0x3f) | value)
  45 #define SET_CFG_MUX1_SDHC1_SDHC(reg)            (reg & 0x3f)
  46 #define SET_CFG_MUX2_SDHC1_SPI(reg, value)      ((reg & 0xcf) | value)
  47 #define SET_CFG_MUX3_SDHC1_SPI(reg, value)      ((reg & 0xf8) | value)
  48 #define SET_CFG_MUX_SDHC2_DSPI(reg, value)      ((reg & 0xf8) | value)
  49 #define SET_CFG_MUX1_SDHC1_DSPI(reg, value)     ((reg & 0x3f) | value)
  50 #define SDHC1_BASE_PMUX_DSPI                    2
  51 #define SDHC2_BASE_PMUX_DSPI                    2
  52 #define IIC5_PMUX_SPI3                          3
  53 #endif /* CONFIG_TARGET_LX2160AQDS or CONFIG_TARGET_LX2162AQDS */
  54
  55 DECLARE_GLOBAL_DATA_PTR;
  56
  57 static struct pl01x_serial_plat serial0 = {
  58 #if CONFIG_CONS_INDEX == 0
  59         .base = CONFIG_SYS_SERIAL0,
  60 #elif CONFIG_CONS_INDEX == 1
  61         .base = CONFIG_SYS_SERIAL1,
  62 #else
  63 #error "Unsupported console index value."
  64 #endif
  65         .type = TYPE_PL011,
  66 };
  67
  68 U_BOOT_DRVINFO(nxp_serial0) = {
  69         .name = "serial_pl01x",
  70         .plat = &serial0,
  71 };
  72
  73 static struct pl01x_serial_plat serial1 = {
  74         .base = CONFIG_SYS_SERIAL1,
  75         .type = TYPE_PL011,
  76 };
  77
  78 U_BOOT_DRVINFO(nxp_serial1) = {
  79         .name = "serial_pl01x",
  80         .plat = &serial1,
  81 };
  82
  83 static void uart_get_clock(void)
  84 {
  85         serial0.clock = get_serial_clock();
  86         serial1.clock = get_serial_clock();
  87 }
  88
  89 int board_early_init_f(void)
  90 {
  91 #if defined(CONFIG_SYS_I2C_EARLY_INIT) && defined(CONFIG_SPL_BUILD)
  92         i2c_early_init_f();
  93 #endif
  94         /* get required clock for UART IP */
  95         uart_get_clock();
  96
  97 #ifdef CONFIG_EMC2305
  98         select_i2c_ch_pca9547(I2C_MUX_CH_EMC2305, 0);
  99         emc2305_init(I2C_EMC2305_ADDR);
 100         set_fan_speed(I2C_EMC2305_PWM, I2C_EMC2305_ADDR);
 101         select_i2c_ch_pca9547(I2C_MUX_CH_DEFAULT, 0);
 102 #endif
 103
 104         fsl_lsch3_early_init_f();
 105         return 0;
 106 }
 107
 108 #ifdef CONFIG_OF_BOARD_FIXUP
 109 int board_fix_fdt(void *fdt)
 110 {
 111         char *reg_names, *reg_name;
 112         int names_len, old_name_len, new_name_len, remaining_names_len;
 113         struct str_map {
 114                 char *old_str;
 115                 char *new_str;
 116         } reg_names_map[] = {
 117                 { "ccsr", "dbi" },
 118                 { "pf_ctrl", "ctrl" }
 119         };
 120         int off = -1, i = 0;
 121
 122         if (IS_SVR_REV(get_svr(), 1, 0))
 123                 return 0;
 124
 125         fdt_for_each_node_by_compatible(off, fdt, -1, "fsl,lx2160a-pcie") {
 126                 fdt_setprop(fdt, off, "compatible", "fsl,ls-pcie",
 127                             strlen("fsl,ls-pcie") + 1);
 128
 129                 reg_names = (char *)fdt_getprop(fdt, off, "reg-names",
 130                                                 &names_len);
 131                 if (!reg_names)
 132                         continue;
 133
 134                 reg_name = reg_names;
 135                 remaining_names_len = names_len - (reg_name - reg_names);
 136                 i = 0;
 137                 while ((i < ARRAY_SIZE(reg_names_map)) && remaining_names_len) {
 138                         old_name_len = strlen(reg_names_map[i].old_str);
 139                         new_name_len = strlen(reg_names_map[i].new_str);
 140                         if (memcmp(reg_name, reg_names_map[i].old_str,
 141                                    old_name_len) == 0) {
 142                                 /* first only leave required bytes for new_str
 143                                  * and copy rest of the string after it
 144                                  */
 145                                 memcpy(reg_name + new_name_len,
 146                                        reg_name + old_name_len,
 147                                        remaining_names_len - old_name_len);
 148                                 /* Now copy new_str */
 149                                 memcpy(reg_name, reg_names_map[i].new_str,
 150                                        new_name_len);
 151                                 names_len -= old_name_len;
 152                                 names_len += new_name_len;
 153                                 i++;
 154                         }
 155
 156                         reg_name = memchr(reg_name, '\0', remaining_names_len);
 157                         if (!reg_name)
 158                                 break;
 159
 160                         reg_name += 1;
 161
 162                         remaining_names_len = names_len -
 163                                               (reg_name - reg_names);
 164                 }
 165
 166                 fdt_setprop(fdt, off, "reg-names", reg_names, names_len);
 167         }
 168
 169         return 0;
 170 }
 171 #endif
 172
 173 #if defined(CONFIG_TARGET_LX2160AQDS) || defined(CONFIG_TARGET_LX2162AQDS)
 174 void esdhc_dspi_status_fixup(void *blob)
 175 {
 176         const char esdhc0_path[] = "/soc/esdhc@2140000";
 177         const char esdhc1_path[] = "/soc/esdhc@2150000";
 178         const char dspi0_path[] = "/soc/spi@2100000";
 179         const char dspi1_path[] = "/soc/spi@2110000";
 180         const char dspi2_path[] = "/soc/spi@2120000";
 181
 182         struct ccsr_gur __iomem *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR);
 183         u32 sdhc1_base_pmux;
 184         u32 sdhc2_base_pmux;
 185         u32 iic5_pmux;
 186
 187         /* Check RCW field sdhc1_base_pmux to enable/disable
 188          * esdhc0/dspi0 DT node
 189          */
 190         sdhc1_base_pmux = gur_in32(&gur->rcwsr[FSL_CHASSIS3_RCWSR12_REGSR - 1])
 191                 & FSL_CHASSIS3_SDHC1_BASE_PMUX_MASK;
 192         sdhc1_base_pmux >>= FSL_CHASSIS3_SDHC1_BASE_PMUX_SHIFT;
 193
 194         if (sdhc1_base_pmux == SDHC1_BASE_PMUX_DSPI) {
 195                 do_fixup_by_path(blob, dspi0_path, "status", "okay",
 196                                  sizeof("okay"), 1);
 197                 do_fixup_by_path(blob, esdhc0_path, "status", "disabled",
 198                                  sizeof("disabled"), 1);
 199         } else {
 200                 do_fixup_by_path(blob, esdhc0_path, "status", "okay",
 201                                  sizeof("okay"), 1);
 202                 do_fixup_by_path(blob, dspi0_path, "status", "disabled",
 203                                  sizeof("disabled"), 1);
 204         }
 205
 206         /* Check RCW field sdhc2_base_pmux to enable/disable
 207          * esdhc1/dspi1 DT node
 208          */
 209         sdhc2_base_pmux = gur_in32(&gur->rcwsr[FSL_CHASSIS3_RCWSR13_REGSR - 1])
 210                 & FSL_CHASSIS3_SDHC2_BASE_PMUX_MASK;
 211         sdhc2_base_pmux >>= FSL_CHASSIS3_SDHC2_BASE_PMUX_SHIFT;
 212
 213         if (sdhc2_base_pmux == SDHC2_BASE_PMUX_DSPI) {
 214                 do_fixup_by_path(blob, dspi1_path, "status", "okay",
 215                                  sizeof("okay"), 1);
 216                 do_fixup_by_path(blob, esdhc1_path, "status", "disabled",
 217                                  sizeof("disabled"), 1);
 218         } else {
 219                 do_fixup_by_path(blob, esdhc1_path, "status", "okay",
 220                                  sizeof("okay"), 1);
 221                 do_fixup_by_path(blob, dspi1_path, "status", "disabled",
 222                                  sizeof("disabled"), 1);
 223         }
 224
 225         /* Check RCW field IIC5 to enable dspi2 DT node */
 226         iic5_pmux = gur_in32(&gur->rcwsr[FSL_CHASSIS3_RCWSR12_REGSR - 1])
 227                 & FSL_CHASSIS3_IIC5_PMUX_MASK;
 228         iic5_pmux >>= FSL_CHASSIS3_IIC5_PMUX_SHIFT;
 229
 230         if (iic5_pmux == IIC5_PMUX_SPI3)
 231                 do_fixup_by_path(blob, dspi2_path, "status", "okay",
 232                                  sizeof("okay"), 1);
 233         else
 234                 do_fixup_by_path(blob, dspi2_path, "status", "disabled",
 235                                  sizeof("disabled"), 1);
 236 }
 237 #endif
 238
 239 int esdhc_status_fixup(void *blob, const char *compat)
 240 {
 241 #if defined(CONFIG_TARGET_LX2160AQDS) || defined(CONFIG_TARGET_LX2162AQDS)
 242         /* Enable esdhc and dspi DT nodes based on RCW fields */
 243         esdhc_dspi_status_fixup(blob);
 244 #else
 245         /* Enable both esdhc DT nodes for LX2160ARDB */
 246         do_fixup_by_compat(blob, compat, "status", "okay",
 247                            sizeof("okay"), 1);
 248 #endif
 249         return 0;
 250 }
 251
 252 #if defined(CONFIG_VID)
 253 int i2c_multiplexer_select_vid_channel(u8 channel)
 254 {
 255         return select_i2c_ch_pca9547(channel, 0);
 256 }
 257
 258 int init_func_vid(void)
 259 {
 260         int set_vid;
 261
 262         if (IS_SVR_REV(get_svr(), 1, 0))
 263                 set_vid = adjust_vdd(800);
 264         else
 265                 set_vid = adjust_vdd(0);
 266
 267         if (set_vid < 0)
 268                 printf("core voltage not adjusted\n");
 269
 270         return 0;
 271 }
 272 #endif
 273
 274 int checkboard(void)
 275 {
 276         enum boot_src src = get_boot_src();
 277         char buf[64];
 278         u8 sw;
 279 #if defined(CONFIG_TARGET_LX2160AQDS) || defined(CONFIG_TARGET_LX2162AQDS)
 280         int clock;
 281         static const char *const freq[] = {"100", "125", "156.25",
 282                                            "161.13", "322.26", "", "", "",
 283                                            "", "", "", "", "", "", "",
 284                                            "100 separate SSCG"};
 285 #endif
 286
 287         cpu_name(buf);
 288 #if defined(CONFIG_TARGET_LX2160AQDS) || defined(CONFIG_TARGET_LX2162AQDS)
 289         printf("Board: %s-QDS, ", buf);
 290 #else
 291         printf("Board: %s-RDB, ", buf);
 292 #endif
 293
 294         sw = QIXIS_READ(arch);
 295         printf("Board version: %c, boot from ", (sw & 0xf) - 1 + 'A');
 296
 297         if (src == BOOT_SOURCE_SD_MMC) {
 298                 puts("SD\n");
 299         } else if (src == BOOT_SOURCE_SD_MMC2) {
 300                 puts("eMMC\n");
 301         } else {
 302                 sw = QIXIS_READ(brdcfg[0]);
 303                 sw = (sw >> QIXIS_XMAP_SHIFT) & QIXIS_XMAP_MASK;
 304                 switch (sw) {
 305                 case 0:
 306                 case 4:
 307                         puts("FlexSPI DEV#0\n");
 308                         break;
 309                 case 1:
 310                         puts("FlexSPI DEV#1\n");
 311                         break;
 312                 case 2:
 313                 case 3:
 314                         puts("FlexSPI EMU\n");
 315                         break;
 316                 default:
 317                         printf("invalid setting, xmap: %d\n", sw);
 318                         break;
 319                 }
 320         }
 321 #if defined(CONFIG_TARGET_LX2160ARDB)
 322         printf("FPGA: v%d.%d\n", QIXIS_READ(scver), QIXIS_READ(tagdata));
 323
 324         puts("SERDES1 Reference: Clock1 = 161.13MHz Clock2 = 161.13MHz\n");
 325         puts("SERDES2 Reference: Clock1 = 100MHz Clock2 = 100MHz\n");
 326         puts("SERDES3 Reference: Clock1 = 100MHz Clock2 = 100MHz\n");
 327 #else
 328         printf("FPGA: v%d (%s), build %d",
 329                (int)QIXIS_READ(scver), qixis_read_tag(buf),
 330                (int)qixis_read_minor());
 331         /* the timestamp string contains "\n" at the end */
 332         printf(" on %s", qixis_read_time(buf));
 333
 334         puts("SERDES1 Reference : ");
 335         sw = QIXIS_READ(brdcfg[2]);
 336         clock = sw >> 4;
 337         printf("Clock1 = %sMHz ", freq[clock]);
 338 #if defined(CONFIG_TARGET_LX2160AQDS)
 339         clock = sw & 0x0f;
 340         printf("Clock2 = %sMHz", freq[clock]);
 341 #endif
 342         sw = QIXIS_READ(brdcfg[3]);
 343         puts("\nSERDES2 Reference : ");
 344         clock = sw >> 4;
 345         printf("Clock1 = %sMHz ", freq[clock]);
 346         clock = sw & 0x0f;
 347         printf("Clock2 = %sMHz\n", freq[clock]);
 348 #if defined(CONFIG_TARGET_LX2160AQDS)
 349         sw = QIXIS_READ(brdcfg[12]);
 350         puts("SERDES3 Reference : ");
 351         clock = sw >> 4;
 352         printf("Clock1 = %sMHz Clock2 = %sMHz\n", freq[clock], freq[clock]);
 353 #endif
 354 #endif
 355         return 0;
 356 }
 357
 358 #if defined(CONFIG_TARGET_LX2160AQDS) || defined(CONFIG_TARGET_LX2162AQDS)
 359 /*
 360  * implementation of CONFIG_ESDHC_DETECT_QUIRK Macro.
 361  */
 362 u8 qixis_esdhc_detect_quirk(void)
 363 {
 364         /*
 365          * SDHC1 Card ID:
 366          * Specifies the type of card installed in the SDHC1 adapter slot.
 367          * 000= (reserved)
 368          * 001= eMMC V4.5 adapter is installed.
 369          * 010= SD/MMC 3.3V adapter is installed.
 370          * 011= eMMC V4.4 adapter is installed.
 371          * 100= eMMC V5.0 adapter is installed.
 372          * 101= MMC card/Legacy (3.3V) adapter is installed.
 373          * 110= SDCard V2/V3 adapter installed.
 374          * 111= no adapter is installed.
 375          */
 376         return ((QIXIS_READ(sdhc1) & QIXIS_SDID_MASK) !=
 377                  QIXIS_ESDHC_NO_ADAPTER);
 378 }
 379
 380 static void esdhc_adapter_card_ident(void)
 381 {
 382         u8 card_id, val;
 383
 384         val = QIXIS_READ(sdhc1);
 385         card_id = val & QIXIS_SDID_MASK;
 386
 387         switch (card_id) {
 388         case QIXIS_ESDHC_ADAPTER_TYPE_SD:
 389                 /* Power cycle to card */
 390                 val &= ~QIXIS_SDHC1_S1V3;
 391                 QIXIS_WRITE(sdhc1, val);
 392                 mdelay(1);
 393                 val |= QIXIS_SDHC1_S1V3;
 394                 QIXIS_WRITE(sdhc1, val);
 395                 /* Route to SDHC1_VS */
 396                 val = QIXIS_READ(brdcfg[11]);
 397                 val |= QIXIS_SDHC1_VS;
 398                 QIXIS_WRITE(brdcfg[11], val);
 399                 break;
 400         default:
 401                 break;
 402         }
 403 }
 404
 405 int config_board_mux(void)
 406 {
 407         u8 reg11, reg5, reg13;
 408         struct ccsr_gur __iomem *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR);
 409         u32 sdhc1_base_pmux;
 410         u32 sdhc2_base_pmux;
 411         u32 iic5_pmux;
 412
 413         /* Routes {I2C2_SCL, I2C2_SDA} to SDHC1 as {SDHC1_CD_B, SDHC1_WP}.
 414          * Routes {I2C3_SCL, I2C3_SDA} to CAN transceiver as {CAN1_TX,CAN1_RX}.
 415          * Routes {I2C4_SCL, I2C4_SDA} to CAN transceiver as {CAN2_TX,CAN2_RX}.
 416          * Qixis and remote systems are isolated from the I2C1 bus.
 417          * Processor connections are still available.
 418          * SPI2 CS2_B controls EN25S64 SPI memory device.
 419          * SPI3 CS2_B controls EN25S64 SPI memory device.
 420          * EC2 connects to PHY #2 using RGMII protocol.
 421          * CLK_OUT connects to FPGA for clock measurement.
 422          */
 423
 424         reg5 = QIXIS_READ(brdcfg[5]);
 425         reg5 = CFG_MUX_I2C_SDHC(reg5, 0x40);
 426         QIXIS_WRITE(brdcfg[5], reg5);
 427
 428         /* Check RCW field sdhc1_base_pmux
 429          * esdhc0 : sdhc1_base_pmux = 0
 430          * dspi0  : sdhc1_base_pmux = 2
 431          */
 432         sdhc1_base_pmux = gur_in32(&gur->rcwsr[FSL_CHASSIS3_RCWSR12_REGSR - 1])
 433                 & FSL_CHASSIS3_SDHC1_BASE_PMUX_MASK;
 434         sdhc1_base_pmux >>= FSL_CHASSIS3_SDHC1_BASE_PMUX_SHIFT;
 435
 436         if (sdhc1_base_pmux == SDHC1_BASE_PMUX_DSPI) {
 437                 reg11 = QIXIS_READ(brdcfg[11]);
 438                 reg11 = SET_CFG_MUX1_SDHC1_DSPI(reg11, 0x40);
 439                 QIXIS_WRITE(brdcfg[11], reg11);
 440         } else {
 441                 /* - Routes {SDHC1_CMD, SDHC1_CLK } to SDHC1 adapter slot.
 442                  *          {SDHC1_DAT3, SDHC1_DAT2} to SDHC1 adapter slot.
 443                  *          {SDHC1_DAT1, SDHC1_DAT0} to SDHC1 adapter slot.
 444                  */
 445                 reg11 = QIXIS_READ(brdcfg[11]);
 446                 reg11 = SET_CFG_MUX1_SDHC1_SDHC(reg11);
 447                 QIXIS_WRITE(brdcfg[11], reg11);
 448         }
 449
 450         /* Check RCW field sdhc2_base_pmux
 451          * esdhc1 : sdhc2_base_pmux = 0 (default)
 452          * dspi1  : sdhc2_base_pmux = 2
 453          */
 454         sdhc2_base_pmux = gur_in32(&gur->rcwsr[FSL_CHASSIS3_RCWSR13_REGSR - 1])
 455                 & FSL_CHASSIS3_SDHC2_BASE_PMUX_MASK;
 456         sdhc2_base_pmux >>= FSL_CHASSIS3_SDHC2_BASE_PMUX_SHIFT;
 457
 458         if (sdhc2_base_pmux == SDHC2_BASE_PMUX_DSPI) {
 459                 reg13 = QIXIS_READ(brdcfg[13]);
 460                 reg13 = SET_CFG_MUX_SDHC2_DSPI(reg13, 0x01);
 461                 QIXIS_WRITE(brdcfg[13], reg13);
 462         } else {
 463                 reg13 = QIXIS_READ(brdcfg[13]);
 464                 reg13 = SET_CFG_MUX_SDHC2_DSPI(reg13, 0x00);
 465                 QIXIS_WRITE(brdcfg[13], reg13);
 466         }
 467
 468         /* Check RCW field IIC5 to enable dspi2 DT nodei
 469          * dspi2: IIC5 = 3
 470          */
 471         iic5_pmux = gur_in32(&gur->rcwsr[FSL_CHASSIS3_RCWSR12_REGSR - 1])
 472                 & FSL_CHASSIS3_IIC5_PMUX_MASK;
 473         iic5_pmux >>= FSL_CHASSIS3_IIC5_PMUX_SHIFT;
 474
 475         if (iic5_pmux == IIC5_PMUX_SPI3) {
 476                 /* - Routes {SDHC1_DAT4} to SPI3 devices as {SPI3_M_CS0_B}. */
 477                 reg11 = QIXIS_READ(brdcfg[11]);
 478                 reg11 = SET_CFG_MUX2_SDHC1_SPI(reg11, 0x10);
 479                 QIXIS_WRITE(brdcfg[11], reg11);
 480
 481                 /* - Routes {SDHC1_DAT5, SDHC1_DAT6} nowhere.
 482                  * {SDHC1_DAT7, SDHC1_DS } to {nothing, SPI3_M0_CLK }.
 483                  * {I2C5_SCL, I2C5_SDA } to {SPI3_M0_MOSI, SPI3_M0_MISO}.
 484                  */
 485                 reg11 = QIXIS_READ(brdcfg[11]);
 486                 reg11 = SET_CFG_MUX3_SDHC1_SPI(reg11, 0x01);
 487                 QIXIS_WRITE(brdcfg[11], reg11);
 488         } else {
 489                 /*
 490                  * If {SDHC1_DAT4} has been configured to route to SDHC1_VS,
 491                  * do not change it.
 492                  * Otherwise route {SDHC1_DAT4} to SDHC1 adapter slot.
 493                  */
 494                 reg11 = QIXIS_READ(brdcfg[11]);
 495                 if ((reg11 & 0x30) != 0x30) {
 496                         reg11 = SET_CFG_MUX2_SDHC1_SPI(reg11, 0x00);
 497                         QIXIS_WRITE(brdcfg[11], reg11);
 498                 }
 499
 500                 /* - Routes {SDHC1_DAT5, SDHC1_DAT6} to SDHC1 adapter slot.
 501                  * {SDHC1_DAT7, SDHC1_DS } to SDHC1 adapter slot.
 502                  * {I2C5_SCL, I2C5_SDA } to SDHC1 adapter slot.
 503                  */
 504                 reg11 = QIXIS_READ(brdcfg[11]);
 505                 reg11 = SET_CFG_MUX3_SDHC1_SPI(reg11, 0x00);
 506                 QIXIS_WRITE(brdcfg[11], reg11);
 507         }
 508
 509         return 0;
 510 }
 511
 512 int board_early_init_r(void)
 513 {
 514         esdhc_adapter_card_ident();
 515         return 0;
 516 }
 517 #elif defined(CONFIG_TARGET_LX2160ARDB)
 518 int config_board_mux(void)
 519 {
 520         u8 brdcfg;
 521
 522         brdcfg = QIXIS_READ(brdcfg[4]);
 523         /* The BRDCFG4 register controls general board configuration.
 524          *|-------------------------------------------|
 525          *|Field  | Function                          |
 526          *|-------------------------------------------|
 527          *|5      | CAN I/O Enable (net CFG_CAN_EN_B):|
 528          *|CAN_EN | 0= CAN transceivers are disabled. |
 529          *|       | 1= CAN transceivers are enabled.  |
 530          *|-------------------------------------------|
 531          */
 532         brdcfg |= BIT_MASK(5);
 533         QIXIS_WRITE(brdcfg[4], brdcfg);
 534
 535         return 0;
 536 }
 537 #else
 538 int config_board_mux(void)
 539 {
 540         return 0;
 541 }
 542 #endif
 543
 544 unsigned long get_board_sys_clk(void)
 545 {
 546 #if defined(CONFIG_TARGET_LX2160AQDS) || defined(CONFIG_TARGET_LX2162AQDS)
 547         u8 sysclk_conf = QIXIS_READ(brdcfg[1]);
 548
 549         switch (sysclk_conf & 0x03) {
 550         case QIXIS_SYSCLK_100:
 551                 return 100000000;
 552         case QIXIS_SYSCLK_125:
 553                 return 125000000;
 554         case QIXIS_SYSCLK_133:
 555                 return 133333333;
 556         }
 557         return 100000000;
 558 #else
 559         return 100000000;
 560 #endif
 561 }
 562
 563 unsigned long get_board_ddr_clk(void)
 564 {
 565 #if defined(CONFIG_TARGET_LX2160AQDS) || defined(CONFIG_TARGET_LX2162AQDS)
 566         u8 ddrclk_conf = QIXIS_READ(brdcfg[1]);
 567
 568         switch ((ddrclk_conf & 0x30) >> 4) {
 569         case QIXIS_DDRCLK_100:
 570                 return 100000000;
 571         case QIXIS_DDRCLK_125:
 572                 return 125000000;
 573         case QIXIS_DDRCLK_133:
 574                 return 133333333;
 575         }
 576         return 100000000;
 577 #else
 578         return 100000000;
 579 #endif
 580 }
 581
 582 int board_init(void)
 583 {
 584 #if defined(CONFIG_FSL_MC_ENET) && defined(CONFIG_TARGET_LX2160ARDB)
 585         u32 __iomem *irq_ccsr = (u32 __iomem *)ISC_BASE;
 586 #endif
 587
 588         select_i2c_ch_pca9547(I2C_MUX_CH_DEFAULT, 0);
 589
 590 #if defined(CONFIG_FSL_MC_ENET) && defined(CONFIG_TARGET_LX2160ARDB)
 591         /* invert AQR107 IRQ pins polarity */
 592         out_le32(irq_ccsr + IRQCR_OFFSET / 4, AQR107_IRQ_MASK);
 593 #endif
 594
 595 #if !defined(CONFIG_SYS_EARLY_PCI_INIT) && defined(CONFIG_DM_ETH)
 596         pci_init();
 597 #endif
 598         return 0;
 599 }
 600
 601 void detail_board_ddr_info(void)
 602 {
 603         int i;
 604         u64 ddr_size = 0;
 605
 606         puts("\nDDR    ");
 607         for (i = 0; i < CONFIG_NR_DRAM_BANKS; i++)
 608                 ddr_size += gd->bd->bi_dram[i].size;
 609         print_size(ddr_size, "");
 610         print_ddr_info(0);
 611 }
 612
 613 #ifdef CONFIG_MISC_INIT_R
 614 int misc_init_r(void)
 615 {
 616         config_board_mux();
 617
 618         return 0;
 619 }
 620 #endif
 621
 622 #ifdef CONFIG_VID
 623 u16 soc_get_fuse_vid(int vid_index)
 624 {
 625         static const u16 vdd[32] = {
 626                 8250,
 627                 7875,
 628                 7750,
 629                 0,      /* reserved */
 630                 0,      /* reserved */
 631                 0,      /* reserved */
 632                 0,      /* reserved */
 633                 0,      /* reserved */
 634                 0,      /* reserved */
 635                 0,      /* reserved */
 636                 0,      /* reserved */
 637                 0,      /* reserved */
 638                 0,      /* reserved */
 639                 0,      /* reserved */
 640                 0,      /* reserved */
 641                 0,      /* reserved */
 642                 8000,
 643                 8125,
 644                 8250,
 645                 0,      /* reserved */
 646                 8500,
 647                 0,      /* reserved */
 648                 0,      /* reserved */
 649                 0,      /* reserved */
 650                 0,      /* reserved */
 651                 0,      /* reserved */
 652                 0,      /* reserved */
 653                 0,      /* reserved */
 654                 0,      /* reserved */
 655                 0,      /* reserved */
 656                 0,      /* reserved */
 657                 0,      /* reserved */
 658         };
 659
 660         return vdd[vid_index];
 661 };
 662 #endif
 663
 664 #ifdef CONFIG_FSL_MC_ENET
 665 extern int fdt_fixup_board_phy(void *fdt);
 666
 667 void fdt_fixup_board_enet(void *fdt)
 668 {
 669         int offset;
 670
 671         offset = fdt_path_offset(fdt, "/soc/fsl-mc");
 672
 673         if (offset < 0)
 674                 offset = fdt_path_offset(fdt, "/fsl-mc");
 675
 676         if (offset < 0) {
 677                 printf("%s: fsl-mc node not found in device tree (error %d)\n",
 678                        __func__, offset);
 679                 return;
 680         }
 681
 682         if (get_mc_boot_status() == 0 &&
 683             (is_lazy_dpl_addr_valid() || get_dpl_apply_status() == 0)) {
 684                 fdt_status_okay(fdt, offset);
 685 #ifndef CONFIG_DM_ETH
 686                 fdt_fixup_board_phy(fdt);
 687 #endif
 688         } else {
 689                 fdt_status_fail(fdt, offset);
 690         }
 691 }
 692
 693 void board_quiesce_devices(void)
 694 {
 695         fsl_mc_ldpaa_exit(gd->bd);
 696 }
 697 #endif
 698
 699 #if CONFIG_IS_ENABLED(TARGET_LX2160ARDB)
 700 int fdt_fixup_add_thermal(void *blob, int mux_node, int channel, int reg)
 701 {
 702         int err;
 703         int noff;
 704         int offset;
 705         char channel_node_name[50];
 706         char thermal_node_name[50];
 707         u32 phandle;
 708
 709         snprintf(channel_node_name, sizeof(channel_node_name),
 710                  "i2c@%x", channel);
 711         debug("channel_node_name = %s\n", channel_node_name);
 712
 713         snprintf(thermal_node_name, sizeof(thermal_node_name),
 714                  "temperature-sensor@%x", reg);
 715         debug("thermal_node_name = %s\n", thermal_node_name);
 716
 717         err = fdt_increase_size(blob, 200);
 718         if (err) {
 719                 printf("fdt_increase_size: err=%s\n", fdt_strerror(err));
 720                 return err;
 721         }
 722
 723         noff = fdt_subnode_offset(blob, mux_node, (const char *)
 724                                   channel_node_name);
 725         if (noff < 0) {
 726                 /* channel node not found - create it */
 727                 noff = fdt_add_subnode(blob, mux_node, channel_node_name);
 728                 if (noff < 0) {
 729                         printf("fdt_add_subnode: err=%s\n", fdt_strerror(err));
 730                         return err;
 731                 }
 732                 fdt_setprop_u32 (blob, noff, "#address-cells", 1);
 733                 fdt_setprop_u32 (blob, noff, "#size-cells", 0);
 734                 fdt_setprop_u32 (blob, noff, "reg", channel);
 735         }
 736
 737         /* Create thermal node*/
 738         offset = fdt_add_subnode(blob, noff, thermal_node_name);
 739         fdt_setprop(blob, offset, "compatible", "nxp,sa56004",
 740                     strlen("nxp,sa56004") + 1);
 741         fdt_setprop_u32 (blob, offset, "reg", reg);
 742
 743         /* fixup phandle*/
 744         noff = fdt_node_offset_by_compatible(blob, -1, "regulator-fixed");
 745         if (noff < 0) {
 746                 printf("%s : failed to get phandle\n", __func__);
 747                 return noff;
 748         }
 749         phandle = fdt_get_phandle(blob, noff);
 750         fdt_setprop_u32 (blob, offset, "vcc-supply", phandle);
 751
 752         return 0;
 753 }
 754
 755 void fdt_fixup_delete_thermal(void *blob, int mux_node, int channel, int reg)
 756 {
 757         int node;
 758         int value;
 759         int err;
 760         int subnode;
 761
 762         fdt_for_each_subnode(subnode, blob, mux_node) {
 763                 value = fdtdec_get_uint(blob, subnode, "reg", -1);
 764                 if (value == channel) {
 765                         /* delete thermal node */
 766                         fdt_for_each_subnode(node, blob, subnode) {
 767                                 value = fdtdec_get_uint(blob, node, "reg", -1);
 768                                 err = fdt_node_check_compatible(blob, node,
 769                                                                 "nxp,sa56004");
 770                                 if (!err && value == reg) {
 771                                         fdt_del_node(blob, node);
 772                                         break;
 773                                 }
 774                         }
 775                 }
 776         }
 777 }
 778
 779 void fdt_fixup_i2c_thermal_node(void *blob)
 780 {
 781         int i2coffset;
 782         int mux_node;
 783         int reg;
 784         int err;
 785
 786         i2coffset = fdt_node_offset_by_compat_reg(blob, "fsl,vf610-i2c",
 787                                                   0x2000000);
 788         if (i2coffset != -FDT_ERR_NOTFOUND) {
 789                 fdt_for_each_subnode(mux_node, blob, i2coffset) {
 790                         reg = fdtdec_get_uint(blob, mux_node, "reg", -1);
 791                         err = fdt_node_check_compatible(blob, mux_node,
 792                                                         "nxp,pca9547");
 793                         if (!err && reg == 0x77) {
 794                                 fdt_fixup_delete_thermal(blob, mux_node,
 795                                                          0x3, 0x4d);
 796                                 err = fdt_fixup_add_thermal(blob, mux_node,
 797                                                             0x3, 0x48);
 798                                 if (err)
 799                                         printf("%s: Add thermal node failed\n",
 800                                                __func__);
 801                         }
 802                 }
 803         } else {
 804                 printf("%s: i2c node not found\n", __func__);
 805         }
 806 }
 807 #endif
 808
 809 #ifdef CONFIG_OF_BOARD_SETUP
 810 int ft_board_setup(void *blob, struct bd_info *bd)
 811 {
 812         int i;
 813         u16 mc_memory_bank = 0;
 814
 815         u64 *base;
 816         u64 *size;
 817         u64 mc_memory_base = 0;
 818         u64 mc_memory_size = 0;
 819         u16 total_memory_banks;
 820         int err;
 821 #if CONFIG_IS_ENABLED(TARGET_LX2160ARDB)
 822         u8 board_rev;
 823 #endif
 824
 825         err = fdt_increase_size(blob, 512);
 826         if (err) {
 827                 printf("%s fdt_increase_size: err=%s\n", __func__,
 828                        fdt_strerror(err));
 829                 return err;
 830         }
 831
 832         ft_cpu_setup(blob, bd);
 833
 834         fdt_fixup_mc_ddr(&mc_memory_base, &mc_memory_size);
 835
 836         if (mc_memory_base != 0)
 837                 mc_memory_bank++;
 838
 839         total_memory_banks = CONFIG_NR_DRAM_BANKS + mc_memory_bank;
 840
 841         base = calloc(total_memory_banks, sizeof(u64));
 842         size = calloc(total_memory_banks, sizeof(u64));
 843
 844         /* fixup DT for the three GPP DDR banks */
 845         for (i = 0; i < CONFIG_NR_DRAM_BANKS; i++) {
 846                 base[i] = gd->bd->bi_dram[i].start;
 847                 size[i] = gd->bd->bi_dram[i].size;
 848         }
 849
 850 #ifdef CONFIG_RESV_RAM
 851         /* reduce size if reserved memory is within this bank */
 852         if (gd->arch.resv_ram >= base[0] &&
 853             gd->arch.resv_ram < base[0] + size[0])
 854                 size[0] = gd->arch.resv_ram - base[0];
 855         else if (gd->arch.resv_ram >= base[1] &&
 856                  gd->arch.resv_ram < base[1] + size[1])
 857                 size[1] = gd->arch.resv_ram - base[1];
 858         else if (gd->arch.resv_ram >= base[2] &&
 859                  gd->arch.resv_ram < base[2] + size[2])
 860                 size[2] = gd->arch.resv_ram - base[2];
 861 #endif
 862
 863         if (mc_memory_base != 0) {
 864                 for (i = 0; i <= total_memory_banks; i++) {
 865                         if (base[i] == 0 && size[i] == 0) {
 866                                 base[i] = mc_memory_base;
 867                                 size[i] = mc_memory_size;
 868                                 break;
 869                         }
 870                 }
 871         }
 872
 873         fdt_fixup_memory_banks(blob, base, size, total_memory_banks);
 874
 875 #ifdef CONFIG_USB_HOST
 876         fsl_fdt_fixup_dr_usb(blob, bd);
 877 #endif
 878
 879 #ifdef CONFIG_FSL_MC_ENET
 880         fdt_fsl_mc_fixup_iommu_map_entry(blob);
 881         fdt_fixup_board_enet(blob);
 882 #endif
 883         fdt_fixup_icid(blob);
 884
 885 #if CONFIG_IS_ENABLED(TARGET_LX2160ARDB)
 886         board_rev = (QIXIS_READ(arch) & 0xf) - 1 + 'A';
 887         if (board_rev == 'C')
 888                 fdt_fixup_i2c_thermal_node(blob);
 889 #endif
 890
 891         return 0;
 892 }
 893 #endif
 894
 895 void qixis_dump_switch(void)
 896 {
 897         int i, nr_of_cfgsw;
 898
 899         QIXIS_WRITE(cms[0], 0x00);
 900         nr_of_cfgsw = QIXIS_READ(cms[1]);
 901
 902         puts("DIP switch settings dump:\n");
 903         for (i = 1; i <= nr_of_cfgsw; i++) {
 904                 QIXIS_WRITE(cms[0], i);
 905                 printf("SW%d = (0x%02x)\n", i, QIXIS_READ(cms[1]));
 906         }
 907 }