board/freescale/lx2160a/lx2160a.c

   1 // SPDX-License-Identifier: GPL-2.0+
   2 /*
   3  * Copyright 2018-2021 NXP
   4  */
   5
   6 #include <common.h>
   7 #include <clock_legacy.h>
   8 #include <display_options.h>
   9 #include <dm.h>
  10 #include <init.h>
  11 #include <asm/global_data.h>
  12 #include <dm/platform_data/serial_pl01x.h>
  13 #include <i2c.h>
  14 #include <malloc.h>
  15 #include <errno.h>
  16 #include <netdev.h>
  17 #include <fsl_ddr.h>
  18 #include <asm/io.h>
  19 #include <fdt_support.h>
  20 #include <linux/bitops.h>
  21 #include <linux/libfdt.h>
  22 #include <linux/delay.h>
  23 #include <fsl-mc/fsl_mc.h>
  24 #include <env_internal.h>
  25 #include <efi_loader.h>
  26 #include <asm/arch/mmu.h>
  27 #include <hwconfig.h>
  28 #include <asm/arch/clock.h>
  29 #include <asm/arch/config.h>
  30 #include <asm/arch/fsl_serdes.h>
  31 #include <asm/arch/soc.h>
  32 #include "../common/i2c_mux.h"
  33
  34 #include "../common/qixis.h"
  35 #include "../common/vid.h"
  36 #include <fsl_immap.h>
  37 #include <asm/arch-fsl-layerscape/fsl_icid.h>
  38 #include "lx2160a.h"
  39
  40 #ifdef CONFIG_EMC2305
  41 #include "../common/emc2305.h"
  42 #endif
  43
  44 #if defined(CONFIG_TARGET_LX2160AQDS) || defined(CONFIG_TARGET_LX2162AQDS)
  45 #define CFG_MUX_I2C_SDHC(reg, value)            ((reg & 0x3f) | value)
  46 #define SET_CFG_MUX1_SDHC1_SDHC(reg)            (reg & 0x3f)
  47 #define SET_CFG_MUX2_SDHC1_SPI(reg, value)      ((reg & 0xcf) | value)
  48 #define SET_CFG_MUX3_SDHC1_SPI(reg, value)      ((reg & 0xf8) | value)
  49 #define SET_CFG_MUX_SDHC2_DSPI(reg, value)      ((reg & 0xf8) | value)
  50 #define SET_CFG_MUX1_SDHC1_DSPI(reg, value)     ((reg & 0x3f) | value)
  51 #define SDHC1_BASE_PMUX_DSPI                    2
  52 #define SDHC2_BASE_PMUX_DSPI                    2
  53 #define IIC5_PMUX_SPI3                          3
  54 #endif /* CONFIG_TARGET_LX2160AQDS or CONFIG_TARGET_LX2162AQDS */
  55
  56 DECLARE_GLOBAL_DATA_PTR;
  57
  58 static struct pl01x_serial_plat serial0 = {
  59 #if CONFIG_CONS_INDEX == 0
  60         .base = CONFIG_SYS_SERIAL0,
  61 #elif CONFIG_CONS_INDEX == 1
  62         .base = CONFIG_SYS_SERIAL1,
  63 #else
  64 #error "Unsupported console index value."
  65 #endif
  66         .type = TYPE_PL011,
  67 };
  68
  69 U_BOOT_DRVINFO(nxp_serial0) = {
  70         .name = "serial_pl01x",
  71         .plat = &serial0,
  72 };
  73
  74 static struct pl01x_serial_plat serial1 = {
  75         .base = CONFIG_SYS_SERIAL1,
  76         .type = TYPE_PL011,
  77 };
  78
  79 U_BOOT_DRVINFO(nxp_serial1) = {
  80         .name = "serial_pl01x",
  81         .plat = &serial1,
  82 };
  83
  84 static void uart_get_clock(void)
  85 {
  86         serial0.clock = get_serial_clock();
  87         serial1.clock = get_serial_clock();
  88 }
  89
  90 int board_early_init_f(void)
  91 {
  92 #if defined(CONFIG_SYS_I2C_EARLY_INIT) && defined(CONFIG_SPL_BUILD)
  93         i2c_early_init_f();
  94 #endif
  95         /* get required clock for UART IP */
  96         uart_get_clock();
  97
  98 #ifdef CONFIG_EMC2305
  99         select_i2c_ch_pca9547(I2C_MUX_CH_EMC2305, 0);
 100         emc2305_init(I2C_EMC2305_ADDR);
 101         set_fan_speed(I2C_EMC2305_PWM, I2C_EMC2305_ADDR);
 102         select_i2c_ch_pca9547(I2C_MUX_CH_DEFAULT, 0);
 103 #endif
 104
 105         fsl_lsch3_early_init_f();
 106         return 0;
 107 }
 108
 109 #ifdef CONFIG_OF_BOARD_FIXUP
 110 int board_fix_fdt(void *fdt)
 111 {
 112         char *reg_names, *reg_name;
 113         int names_len, old_name_len, new_name_len, remaining_names_len;
 114         struct str_map {
 115                 char *old_str;
 116                 char *new_str;
 117         } reg_names_map[] = {
 118                 { "ccsr", "dbi" },
 119                 { "pf_ctrl", "ctrl" }
 120         };
 121         int off = -1, i = 0;
 122
 123         if (IS_SVR_REV(get_svr(), 1, 0))
 124                 return 0;
 125
 126         fdt_for_each_node_by_compatible(off, fdt, -1, "fsl,lx2160a-pcie") {
 127                 fdt_setprop(fdt, off, "compatible", "fsl,ls-pcie",
 128                             strlen("fsl,ls-pcie") + 1);
 129
 130                 reg_names = (char *)fdt_getprop(fdt, off, "reg-names",
 131                                                 &names_len);
 132                 if (!reg_names)
 133                         continue;
 134
 135                 reg_name = reg_names;
 136                 remaining_names_len = names_len - (reg_name - reg_names);
 137                 i = 0;
 138                 while ((i < ARRAY_SIZE(reg_names_map)) && remaining_names_len) {
 139                         old_name_len = strlen(reg_names_map[i].old_str);
 140                         new_name_len = strlen(reg_names_map[i].new_str);
 141                         if (memcmp(reg_name, reg_names_map[i].old_str,
 142                                    old_name_len) == 0) {
 143                                 /* first only leave required bytes for new_str
 144                                  * and copy rest of the string after it
 145                                  */
 146                                 memcpy(reg_name + new_name_len,
 147                                        reg_name + old_name_len,
 148                                        remaining_names_len - old_name_len);
 149                                 /* Now copy new_str */
 150                                 memcpy(reg_name, reg_names_map[i].new_str,
 151                                        new_name_len);
 152                                 names_len -= old_name_len;
 153                                 names_len += new_name_len;
 154                                 i++;
 155                         }
 156
 157                         reg_name = memchr(reg_name, '\0', remaining_names_len);
 158                         if (!reg_name)
 159                                 break;
 160
 161                         reg_name += 1;
 162
 163                         remaining_names_len = names_len -
 164                                               (reg_name - reg_names);
 165                 }
 166
 167                 fdt_setprop(fdt, off, "reg-names", reg_names, names_len);
 168         }
 169
 170         return 0;
 171 }
 172 #endif
 173
 174 #if defined(CONFIG_TARGET_LX2160AQDS) || defined(CONFIG_TARGET_LX2162AQDS)
 175 void esdhc_dspi_status_fixup(void *blob)
 176 {
 177         const char esdhc0_path[] = "/soc/esdhc@2140000";
 178         const char esdhc1_path[] = "/soc/esdhc@2150000";
 179         const char dspi0_path[] = "/soc/spi@2100000";
 180         const char dspi1_path[] = "/soc/spi@2110000";
 181         const char dspi2_path[] = "/soc/spi@2120000";
 182
 183         struct ccsr_gur __iomem *gur = (void *)(CFG_SYS_FSL_GUTS_ADDR);
 184         u32 sdhc1_base_pmux;
 185         u32 sdhc2_base_pmux;
 186         u32 iic5_pmux;
 187
 188         /* Check RCW field sdhc1_base_pmux to enable/disable
 189          * esdhc0/dspi0 DT node
 190          */
 191         sdhc1_base_pmux = gur_in32(&gur->rcwsr[FSL_CHASSIS3_RCWSR12_REGSR - 1])
 192                 & FSL_CHASSIS3_SDHC1_BASE_PMUX_MASK;
 193         sdhc1_base_pmux >>= FSL_CHASSIS3_SDHC1_BASE_PMUX_SHIFT;
 194
 195         if (sdhc1_base_pmux == SDHC1_BASE_PMUX_DSPI) {
 196                 do_fixup_by_path(blob, dspi0_path, "status", "okay",
 197                                  sizeof("okay"), 1);
 198                 do_fixup_by_path(blob, esdhc0_path, "status", "disabled",
 199                                  sizeof("disabled"), 1);
 200         } else {
 201                 do_fixup_by_path(blob, esdhc0_path, "status", "okay",
 202                                  sizeof("okay"), 1);
 203                 do_fixup_by_path(blob, dspi0_path, "status", "disabled",
 204                                  sizeof("disabled"), 1);
 205         }
 206
 207         /* Check RCW field sdhc2_base_pmux to enable/disable
 208          * esdhc1/dspi1 DT node
 209          */
 210         sdhc2_base_pmux = gur_in32(&gur->rcwsr[FSL_CHASSIS3_RCWSR13_REGSR - 1])
 211                 & FSL_CHASSIS3_SDHC2_BASE_PMUX_MASK;
 212         sdhc2_base_pmux >>= FSL_CHASSIS3_SDHC2_BASE_PMUX_SHIFT;
 213
 214         if (sdhc2_base_pmux == SDHC2_BASE_PMUX_DSPI) {
 215                 do_fixup_by_path(blob, dspi1_path, "status", "okay",
 216                                  sizeof("okay"), 1);
 217                 do_fixup_by_path(blob, esdhc1_path, "status", "disabled",
 218                                  sizeof("disabled"), 1);
 219         } else {
 220                 do_fixup_by_path(blob, esdhc1_path, "status", "okay",
 221                                  sizeof("okay"), 1);
 222                 do_fixup_by_path(blob, dspi1_path, "status", "disabled",
 223                                  sizeof("disabled"), 1);
 224         }
 225
 226         /* Check RCW field IIC5 to enable dspi2 DT node */
 227         iic5_pmux = gur_in32(&gur->rcwsr[FSL_CHASSIS3_RCWSR12_REGSR - 1])
 228                 & FSL_CHASSIS3_IIC5_PMUX_MASK;
 229         iic5_pmux >>= FSL_CHASSIS3_IIC5_PMUX_SHIFT;
 230
 231         if (iic5_pmux == IIC5_PMUX_SPI3)
 232                 do_fixup_by_path(blob, dspi2_path, "status", "okay",
 233                                  sizeof("okay"), 1);
 234         else
 235                 do_fixup_by_path(blob, dspi2_path, "status", "disabled",
 236                                  sizeof("disabled"), 1);
 237 }
 238 #endif
 239
 240 int esdhc_status_fixup(void *blob, const char *compat)
 241 {
 242 #if defined(CONFIG_TARGET_LX2160AQDS) || defined(CONFIG_TARGET_LX2162AQDS)
 243         /* Enable esdhc and dspi DT nodes based on RCW fields */
 244         esdhc_dspi_status_fixup(blob);
 245 #else
 246         /* Enable both esdhc DT nodes for LX2160ARDB */
 247         do_fixup_by_compat(blob, compat, "status", "okay",
 248                            sizeof("okay"), 1);
 249 #endif
 250         return 0;
 251 }
 252
 253 #if defined(CONFIG_VID)
 254 int i2c_multiplexer_select_vid_channel(u8 channel)
 255 {
 256         return select_i2c_ch_pca9547(channel, 0);
 257 }
 258
 259 int init_func_vid(void)
 260 {
 261         int set_vid;
 262
 263         if (IS_SVR_REV(get_svr(), 1, 0))
 264                 set_vid = adjust_vdd(800);
 265         else
 266                 set_vid = adjust_vdd(0);
 267
 268         if (set_vid < 0)
 269                 printf("core voltage not adjusted\n");
 270
 271         return 0;
 272 }
 273 #endif
 274
 275 int checkboard(void)
 276 {
 277         enum boot_src src = get_boot_src();
 278         char buf[64];
 279         u8 sw;
 280 #if defined(CONFIG_TARGET_LX2160AQDS) || defined(CONFIG_TARGET_LX2162AQDS)
 281         int clock;
 282         static const char *const freq[] = {"100", "125", "156.25",
 283                                            "161.13", "322.26", "", "", "",
 284                                            "", "", "", "", "", "", "",
 285                                            "100 separate SSCG"};
 286 #endif
 287
 288         cpu_name(buf);
 289 #if defined(CONFIG_TARGET_LX2160AQDS) || defined(CONFIG_TARGET_LX2162AQDS)
 290         printf("Board: %s-QDS, ", buf);
 291 #else
 292         printf("Board: %s-RDB, ", buf);
 293 #endif
 294
 295         sw = QIXIS_READ(arch);
 296         printf("Board version: %c, boot from ", (sw & 0xf) - 1 + 'A');
 297
 298         if (src == BOOT_SOURCE_SD_MMC) {
 299                 puts("SD\n");
 300         } else if (src == BOOT_SOURCE_SD_MMC2) {
 301                 puts("eMMC\n");
 302         } else {
 303                 sw = QIXIS_READ(brdcfg[0]);
 304                 sw = (sw >> QIXIS_XMAP_SHIFT) & QIXIS_XMAP_MASK;
 305                 switch (sw) {
 306                 case 0:
 307                 case 4:
 308                         puts("FlexSPI DEV#0\n");
 309                         break;
 310                 case 1:
 311                         puts("FlexSPI DEV#1\n");
 312                         break;
 313                 case 2:
 314                 case 3:
 315                         puts("FlexSPI EMU\n");
 316                         break;
 317                 default:
 318                         printf("invalid setting, xmap: %d\n", sw);
 319                         break;
 320                 }
 321         }
 322 #if defined(CONFIG_TARGET_LX2160ARDB)
 323         printf("FPGA: v%d.%d\n", QIXIS_READ(scver), QIXIS_READ(tagdata));
 324
 325         puts("SERDES1 Reference: Clock1 = 161.13MHz Clock2 = 161.13MHz\n");
 326         puts("SERDES2 Reference: Clock1 = 100MHz Clock2 = 100MHz\n");
 327         puts("SERDES3 Reference: Clock1 = 100MHz Clock2 = 100MHz\n");
 328 #else
 329         printf("FPGA: v%d (%s), build %d",
 330                (int)QIXIS_READ(scver), qixis_read_tag(buf),
 331                (int)qixis_read_minor());
 332         /* the timestamp string contains "\n" at the end */
 333         printf(" on %s", qixis_read_time(buf));
 334
 335         puts("SERDES1 Reference : ");
 336         sw = QIXIS_READ(brdcfg[2]);
 337         clock = sw >> 4;
 338         printf("Clock1 = %sMHz ", freq[clock]);
 339 #if defined(CONFIG_TARGET_LX2160AQDS)
 340         clock = sw & 0x0f;
 341         printf("Clock2 = %sMHz", freq[clock]);
 342 #endif
 343         sw = QIXIS_READ(brdcfg[3]);
 344         puts("\nSERDES2 Reference : ");
 345         clock = sw >> 4;
 346         printf("Clock1 = %sMHz ", freq[clock]);
 347         clock = sw & 0x0f;
 348         printf("Clock2 = %sMHz\n", freq[clock]);
 349 #if defined(CONFIG_TARGET_LX2160AQDS)
 350         sw = QIXIS_READ(brdcfg[12]);
 351         puts("SERDES3 Reference : ");
 352         clock = sw >> 4;
 353         printf("Clock1 = %sMHz Clock2 = %sMHz\n", freq[clock], freq[clock]);
 354 #endif
 355 #endif
 356         return 0;
 357 }
 358
 359 #if defined(CONFIG_TARGET_LX2160AQDS) || defined(CONFIG_TARGET_LX2162AQDS)
 360 static void esdhc_adapter_card_ident(void)
 361 {
 362         u8 card_id, val;
 363
 364         val = QIXIS_READ(sdhc1);
 365         card_id = val & QIXIS_SDID_MASK;
 366
 367         switch (card_id) {
 368         case QIXIS_ESDHC_ADAPTER_TYPE_SD:
 369                 /* Power cycle to card */
 370                 val &= ~QIXIS_SDHC1_S1V3;
 371                 QIXIS_WRITE(sdhc1, val);
 372                 mdelay(1);
 373                 val |= QIXIS_SDHC1_S1V3;
 374                 QIXIS_WRITE(sdhc1, val);
 375                 /* Route to SDHC1_VS */
 376                 val = QIXIS_READ(brdcfg[11]);
 377                 val |= QIXIS_SDHC1_VS;
 378                 QIXIS_WRITE(brdcfg[11], val);
 379                 break;
 380         default:
 381                 break;
 382         }
 383 }
 384
 385 int config_board_mux(void)
 386 {
 387         u8 reg11, reg5, reg13;
 388         struct ccsr_gur __iomem *gur = (void *)(CFG_SYS_FSL_GUTS_ADDR);
 389         u32 sdhc1_base_pmux;
 390         u32 sdhc2_base_pmux;
 391         u32 iic5_pmux;
 392
 393         /* Routes {I2C2_SCL, I2C2_SDA} to SDHC1 as {SDHC1_CD_B, SDHC1_WP}.
 394          * Routes {I2C3_SCL, I2C3_SDA} to CAN transceiver as {CAN1_TX,CAN1_RX}.
 395          * Routes {I2C4_SCL, I2C4_SDA} to CAN transceiver as {CAN2_TX,CAN2_RX}.
 396          * Qixis and remote systems are isolated from the I2C1 bus.
 397          * Processor connections are still available.
 398          * SPI2 CS2_B controls EN25S64 SPI memory device.
 399          * SPI3 CS2_B controls EN25S64 SPI memory device.
 400          * EC2 connects to PHY #2 using RGMII protocol.
 401          * CLK_OUT connects to FPGA for clock measurement.
 402          */
 403
 404         reg5 = QIXIS_READ(brdcfg[5]);
 405         reg5 = CFG_MUX_I2C_SDHC(reg5, 0x40);
 406         QIXIS_WRITE(brdcfg[5], reg5);
 407
 408         /* Check RCW field sdhc1_base_pmux
 409          * esdhc0 : sdhc1_base_pmux = 0
 410          * dspi0  : sdhc1_base_pmux = 2
 411          */
 412         sdhc1_base_pmux = gur_in32(&gur->rcwsr[FSL_CHASSIS3_RCWSR12_REGSR - 1])
 413                 & FSL_CHASSIS3_SDHC1_BASE_PMUX_MASK;
 414         sdhc1_base_pmux >>= FSL_CHASSIS3_SDHC1_BASE_PMUX_SHIFT;
 415
 416         if (sdhc1_base_pmux == SDHC1_BASE_PMUX_DSPI) {
 417                 reg11 = QIXIS_READ(brdcfg[11]);
 418                 reg11 = SET_CFG_MUX1_SDHC1_DSPI(reg11, 0x40);
 419                 QIXIS_WRITE(brdcfg[11], reg11);
 420         } else {
 421                 /* - Routes {SDHC1_CMD, SDHC1_CLK } to SDHC1 adapter slot.
 422                  *          {SDHC1_DAT3, SDHC1_DAT2} to SDHC1 adapter slot.
 423                  *          {SDHC1_DAT1, SDHC1_DAT0} to SDHC1 adapter slot.
 424                  */
 425                 reg11 = QIXIS_READ(brdcfg[11]);
 426                 reg11 = SET_CFG_MUX1_SDHC1_SDHC(reg11);
 427                 QIXIS_WRITE(brdcfg[11], reg11);
 428         }
 429
 430         /* Check RCW field sdhc2_base_pmux
 431          * esdhc1 : sdhc2_base_pmux = 0 (default)
 432          * dspi1  : sdhc2_base_pmux = 2
 433          */
 434         sdhc2_base_pmux = gur_in32(&gur->rcwsr[FSL_CHASSIS3_RCWSR13_REGSR - 1])
 435                 & FSL_CHASSIS3_SDHC2_BASE_PMUX_MASK;
 436         sdhc2_base_pmux >>= FSL_CHASSIS3_SDHC2_BASE_PMUX_SHIFT;
 437
 438         if (sdhc2_base_pmux == SDHC2_BASE_PMUX_DSPI) {
 439                 reg13 = QIXIS_READ(brdcfg[13]);
 440                 reg13 = SET_CFG_MUX_SDHC2_DSPI(reg13, 0x01);
 441                 QIXIS_WRITE(brdcfg[13], reg13);
 442         } else {
 443                 reg13 = QIXIS_READ(brdcfg[13]);
 444                 reg13 = SET_CFG_MUX_SDHC2_DSPI(reg13, 0x00);
 445                 QIXIS_WRITE(brdcfg[13], reg13);
 446         }
 447
 448         /* Check RCW field IIC5 to enable dspi2 DT nodei
 449          * dspi2: IIC5 = 3
 450          */
 451         iic5_pmux = gur_in32(&gur->rcwsr[FSL_CHASSIS3_RCWSR12_REGSR - 1])
 452                 & FSL_CHASSIS3_IIC5_PMUX_MASK;
 453         iic5_pmux >>= FSL_CHASSIS3_IIC5_PMUX_SHIFT;
 454
 455         if (iic5_pmux == IIC5_PMUX_SPI3) {
 456                 /* - Routes {SDHC1_DAT4} to SPI3 devices as {SPI3_M_CS0_B}. */
 457                 reg11 = QIXIS_READ(brdcfg[11]);
 458                 reg11 = SET_CFG_MUX2_SDHC1_SPI(reg11, 0x10);
 459                 QIXIS_WRITE(brdcfg[11], reg11);
 460
 461                 /* - Routes {SDHC1_DAT5, SDHC1_DAT6} nowhere.
 462                  * {SDHC1_DAT7, SDHC1_DS } to {nothing, SPI3_M0_CLK }.
 463                  * {I2C5_SCL, I2C5_SDA } to {SPI3_M0_MOSI, SPI3_M0_MISO}.
 464                  */
 465                 reg11 = QIXIS_READ(brdcfg[11]);
 466                 reg11 = SET_CFG_MUX3_SDHC1_SPI(reg11, 0x01);
 467                 QIXIS_WRITE(brdcfg[11], reg11);
 468         } else {
 469                 /*
 470                  * If {SDHC1_DAT4} has been configured to route to SDHC1_VS,
 471                  * do not change it.
 472                  * Otherwise route {SDHC1_DAT4} to SDHC1 adapter slot.
 473                  */
 474                 reg11 = QIXIS_READ(brdcfg[11]);
 475                 if ((reg11 & 0x30) != 0x30) {
 476                         reg11 = SET_CFG_MUX2_SDHC1_SPI(reg11, 0x00);
 477                         QIXIS_WRITE(brdcfg[11], reg11);
 478                 }
 479
 480                 /* - Routes {SDHC1_DAT5, SDHC1_DAT6} to SDHC1 adapter slot.
 481                  * {SDHC1_DAT7, SDHC1_DS } to SDHC1 adapter slot.
 482                  * {I2C5_SCL, I2C5_SDA } to SDHC1 adapter slot.
 483                  */
 484                 reg11 = QIXIS_READ(brdcfg[11]);
 485                 reg11 = SET_CFG_MUX3_SDHC1_SPI(reg11, 0x00);
 486                 QIXIS_WRITE(brdcfg[11], reg11);
 487         }
 488
 489         return 0;
 490 }
 491
 492 int board_early_init_r(void)
 493 {
 494         esdhc_adapter_card_ident();
 495         return 0;
 496 }
 497 #elif defined(CONFIG_TARGET_LX2160ARDB)
 498 int config_board_mux(void)
 499 {
 500         u8 brdcfg;
 501
 502         brdcfg = QIXIS_READ(brdcfg[4]);
 503         /* The BRDCFG4 register controls general board configuration.
 504          *|-------------------------------------------|
 505          *|Field  | Function                          |
 506          *|-------------------------------------------|
 507          *|5      | CAN I/O Enable (net CFG_CAN_EN_B):|
 508          *|CAN_EN | 0= CAN transceivers are disabled. |
 509          *|       | 1= CAN transceivers are enabled.  |
 510          *|-------------------------------------------|
 511          */
 512         brdcfg |= BIT_MASK(5);
 513         QIXIS_WRITE(brdcfg[4], brdcfg);
 514
 515         return 0;
 516 }
 517 #else
 518 int config_board_mux(void)
 519 {
 520         return 0;
 521 }
 522 #endif
 523
 524 unsigned long get_board_sys_clk(void)
 525 {
 526 #if defined(CONFIG_TARGET_LX2160AQDS) || defined(CONFIG_TARGET_LX2162AQDS)
 527         u8 sysclk_conf = QIXIS_READ(brdcfg[1]);
 528
 529         switch (sysclk_conf & 0x03) {
 530         case QIXIS_SYSCLK_100:
 531                 return 100000000;
 532         case QIXIS_SYSCLK_125:
 533                 return 125000000;
 534         case QIXIS_SYSCLK_133:
 535                 return 133333333;
 536         }
 537         return 100000000;
 538 #else
 539         return 100000000;
 540 #endif
 541 }
 542
 543 unsigned long get_board_ddr_clk(void)
 544 {
 545 #if defined(CONFIG_TARGET_LX2160AQDS) || defined(CONFIG_TARGET_LX2162AQDS)
 546         u8 ddrclk_conf = QIXIS_READ(brdcfg[1]);
 547
 548         switch ((ddrclk_conf & 0x30) >> 4) {
 549         case QIXIS_DDRCLK_100:
 550                 return 100000000;
 551         case QIXIS_DDRCLK_125:
 552                 return 125000000;
 553         case QIXIS_DDRCLK_133:
 554                 return 133333333;
 555         }
 556         return 100000000;
 557 #else
 558         return 100000000;
 559 #endif
 560 }
 561
 562 int board_init(void)
 563 {
 564 #if defined(CONFIG_FSL_MC_ENET) && defined(CONFIG_TARGET_LX2160ARDB)
 565         u32 __iomem *irq_ccsr = (u32 __iomem *)ISC_BASE;
 566 #endif
 567
 568         select_i2c_ch_pca9547(I2C_MUX_CH_DEFAULT, 0);
 569
 570 #if defined(CONFIG_FSL_MC_ENET) && defined(CONFIG_TARGET_LX2160ARDB)
 571         /* invert AQR107 IRQ pins polarity */
 572         out_le32(irq_ccsr + IRQCR_OFFSET / 4, AQR107_IRQ_MASK);
 573 #endif
 574
 575 #if !defined(CONFIG_SYS_EARLY_PCI_INIT) && defined(CONFIG_DM_ETH)
 576         pci_init();
 577 #endif
 578         return 0;
 579 }
 580
 581 void detail_board_ddr_info(void)
 582 {
 583         int i;
 584         u64 ddr_size = 0;
 585
 586         puts("\nDDR    ");
 587         for (i = 0; i < CONFIG_NR_DRAM_BANKS; i++)
 588                 ddr_size += gd->bd->bi_dram[i].size;
 589         print_size(ddr_size, "");
 590         print_ddr_info(0);
 591 }
 592
 593 #ifdef CONFIG_MISC_INIT_R
 594 int misc_init_r(void)
 595 {
 596         config_board_mux();
 597
 598         return 0;
 599 }
 600 #endif
 601
 602 #ifdef CONFIG_VID
 603 u16 soc_get_fuse_vid(int vid_index)
 604 {
 605         static const u16 vdd[32] = {
 606                 8250,
 607                 7875,
 608                 7750,
 609                 0,      /* reserved */
 610                 0,      /* reserved */
 611                 0,      /* reserved */
 612                 0,      /* reserved */
 613                 0,      /* reserved */
 614                 0,      /* reserved */
 615                 0,      /* reserved */
 616                 0,      /* reserved */
 617                 0,      /* reserved */
 618                 0,      /* reserved */
 619                 0,      /* reserved */
 620                 0,      /* reserved */
 621                 0,      /* reserved */
 622                 8000,
 623                 8125,
 624                 8250,
 625                 0,      /* reserved */
 626                 8500,
 627                 0,      /* reserved */
 628                 0,      /* reserved */
 629                 0,      /* reserved */
 630                 0,      /* reserved */
 631                 0,      /* reserved */
 632                 0,      /* reserved */
 633                 0,      /* reserved */
 634                 0,      /* reserved */
 635                 0,      /* reserved */
 636                 0,      /* reserved */
 637                 0,      /* reserved */
 638         };
 639
 640         return vdd[vid_index];
 641 };
 642 #endif
 643
 644 #ifdef CONFIG_FSL_MC_ENET
 645 extern int fdt_fixup_board_phy(void *fdt);
 646
 647 void fdt_fixup_board_enet(void *fdt)
 648 {
 649         int offset;
 650
 651         offset = fdt_path_offset(fdt, "/soc/fsl-mc");
 652
 653         if (offset < 0)
 654                 offset = fdt_path_offset(fdt, "/fsl-mc");
 655
 656         if (offset < 0) {
 657                 printf("%s: fsl-mc node not found in device tree (error %d)\n",
 658                        __func__, offset);
 659                 return;
 660         }
 661
 662         if (get_mc_boot_status() == 0 &&
 663             (is_lazy_dpl_addr_valid() || get_dpl_apply_status() == 0)) {
 664                 fdt_status_okay(fdt, offset);
 665 #ifndef CONFIG_DM_ETH
 666                 fdt_fixup_board_phy(fdt);
 667 #endif
 668         } else {
 669                 fdt_status_fail(fdt, offset);
 670         }
 671 }
 672
 673 void board_quiesce_devices(void)
 674 {
 675         fsl_mc_ldpaa_exit(gd->bd);
 676 }
 677 #endif
 678
 679 #if CONFIG_IS_ENABLED(TARGET_LX2160ARDB)
 680 int fdt_fixup_add_thermal(void *blob, int mux_node, int channel, int reg)
 681 {
 682         int err;
 683         int noff;
 684         int offset;
 685         char channel_node_name[50];
 686         char thermal_node_name[50];
 687         u32 phandle;
 688
 689         snprintf(channel_node_name, sizeof(channel_node_name),
 690                  "i2c@%x", channel);
 691         debug("channel_node_name = %s\n", channel_node_name);
 692
 693         snprintf(thermal_node_name, sizeof(thermal_node_name),
 694                  "temperature-sensor@%x", reg);
 695         debug("thermal_node_name = %s\n", thermal_node_name);
 696
 697         err = fdt_increase_size(blob, 200);
 698         if (err) {
 699                 printf("fdt_increase_size: err=%s\n", fdt_strerror(err));
 700                 return err;
 701         }
 702
 703         noff = fdt_subnode_offset(blob, mux_node, (const char *)
 704                                   channel_node_name);
 705         if (noff < 0) {
 706                 /* channel node not found - create it */
 707                 noff = fdt_add_subnode(blob, mux_node, channel_node_name);
 708                 if (noff < 0) {
 709                         printf("fdt_add_subnode: err=%s\n", fdt_strerror(err));
 710                         return err;
 711                 }
 712                 fdt_setprop_u32 (blob, noff, "#address-cells", 1);
 713                 fdt_setprop_u32 (blob, noff, "#size-cells", 0);
 714                 fdt_setprop_u32 (blob, noff, "reg", channel);
 715         }
 716
 717         /* Create thermal node*/
 718         offset = fdt_add_subnode(blob, noff, thermal_node_name);
 719         fdt_setprop(blob, offset, "compatible", "nxp,sa56004",
 720                     strlen("nxp,sa56004") + 1);
 721         fdt_setprop_u32 (blob, offset, "reg", reg);
 722
 723         /* fixup phandle*/
 724         noff = fdt_node_offset_by_compatible(blob, -1, "regulator-fixed");
 725         if (noff < 0) {
 726                 printf("%s : failed to get phandle\n", __func__);
 727                 return noff;
 728         }
 729         phandle = fdt_get_phandle(blob, noff);
 730         fdt_setprop_u32 (blob, offset, "vcc-supply", phandle);
 731
 732         return 0;
 733 }
 734
 735 void fdt_fixup_delete_thermal(void *blob, int mux_node, int channel, int reg)
 736 {
 737         int node;
 738         int value;
 739         int err;
 740         int subnode;
 741
 742         fdt_for_each_subnode(subnode, blob, mux_node) {
 743                 value = fdtdec_get_uint(blob, subnode, "reg", -1);
 744                 if (value == channel) {
 745                         /* delete thermal node */
 746                         fdt_for_each_subnode(node, blob, subnode) {
 747                                 value = fdtdec_get_uint(blob, node, "reg", -1);
 748                                 err = fdt_node_check_compatible(blob, node,
 749                                                                 "nxp,sa56004");
 750                                 if (!err && value == reg) {
 751                                         fdt_del_node(blob, node);
 752                                         break;
 753                                 }
 754                         }
 755                 }
 756         }
 757 }
 758
 759 void fdt_fixup_i2c_thermal_node(void *blob)
 760 {
 761         int i2coffset;
 762         int mux_node;
 763         int reg;
 764         int err;
 765
 766         i2coffset = fdt_node_offset_by_compat_reg(blob, "fsl,vf610-i2c",
 767                                                   0x2000000);
 768         if (i2coffset != -FDT_ERR_NOTFOUND) {
 769                 fdt_for_each_subnode(mux_node, blob, i2coffset) {
 770                         reg = fdtdec_get_uint(blob, mux_node, "reg", -1);
 771                         err = fdt_node_check_compatible(blob, mux_node,
 772                                                         "nxp,pca9547");
 773                         if (!err && reg == 0x77) {
 774                                 fdt_fixup_delete_thermal(blob, mux_node,
 775                                                          0x3, 0x4d);
 776                                 err = fdt_fixup_add_thermal(blob, mux_node,
 777                                                             0x3, 0x48);
 778                                 if (err)
 779                                         printf("%s: Add thermal node failed\n",
 780                                                __func__);
 781                         }
 782                 }
 783         } else {
 784                 printf("%s: i2c node not found\n", __func__);
 785         }
 786 }
 787 #endif
 788
 789 #ifdef CONFIG_OF_BOARD_SETUP
 790 int ft_board_setup(void *blob, struct bd_info *bd)
 791 {
 792         int i;
 793         u16 mc_memory_bank = 0;
 794
 795         u64 *base;
 796         u64 *size;
 797         u64 mc_memory_base = 0;
 798         u64 mc_memory_size = 0;
 799         u16 total_memory_banks;
 800         int err;
 801 #if CONFIG_IS_ENABLED(TARGET_LX2160ARDB)
 802         u8 board_rev;
 803 #endif
 804
 805         err = fdt_increase_size(blob, 512);
 806         if (err) {
 807                 printf("%s fdt_increase_size: err=%s\n", __func__,
 808                        fdt_strerror(err));
 809                 return err;
 810         }
 811
 812         ft_cpu_setup(blob, bd);
 813
 814         fdt_fixup_mc_ddr(&mc_memory_base, &mc_memory_size);
 815
 816         if (mc_memory_base != 0)
 817                 mc_memory_bank++;
 818
 819         total_memory_banks = CONFIG_NR_DRAM_BANKS + mc_memory_bank;
 820
 821         base = calloc(total_memory_banks, sizeof(u64));
 822         size = calloc(total_memory_banks, sizeof(u64));
 823
 824         /* fixup DT for the three GPP DDR banks */
 825         for (i = 0; i < CONFIG_NR_DRAM_BANKS; i++) {
 826                 base[i] = gd->bd->bi_dram[i].start;
 827                 size[i] = gd->bd->bi_dram[i].size;
 828         }
 829
 830 #ifdef CONFIG_RESV_RAM
 831         /* reduce size if reserved memory is within this bank */
 832         if (gd->arch.resv_ram >= base[0] &&
 833             gd->arch.resv_ram < base[0] + size[0])
 834                 size[0] = gd->arch.resv_ram - base[0];
 835         else if (gd->arch.resv_ram >= base[1] &&
 836                  gd->arch.resv_ram < base[1] + size[1])
 837                 size[1] = gd->arch.resv_ram - base[1];
 838         else if (gd->arch.resv_ram >= base[2] &&
 839                  gd->arch.resv_ram < base[2] + size[2])
 840                 size[2] = gd->arch.resv_ram - base[2];
 841 #endif
 842
 843         if (mc_memory_base != 0) {
 844                 for (i = 0; i <= total_memory_banks; i++) {
 845                         if (base[i] == 0 && size[i] == 0) {
 846                                 base[i] = mc_memory_base;
 847                                 size[i] = mc_memory_size;
 848                                 break;
 849                         }
 850                 }
 851         }
 852
 853         fdt_fixup_memory_banks(blob, base, size, total_memory_banks);
 854
 855 #ifdef CONFIG_USB_HOST
 856         fsl_fdt_fixup_dr_usb(blob, bd);
 857 #endif
 858
 859 #ifdef CONFIG_FSL_MC_ENET
 860         fdt_fsl_mc_fixup_iommu_map_entry(blob);
 861         fdt_fixup_board_enet(blob);
 862 #endif
 863         fdt_fixup_icid(blob);
 864
 865 #if CONFIG_IS_ENABLED(TARGET_LX2160ARDB)
 866         board_rev = (QIXIS_READ(arch) & 0xf) - 1 + 'A';
 867         if (board_rev == 'C')
 868                 fdt_fixup_i2c_thermal_node(blob);
 869 #endif
 870
 871         return 0;
 872 }
 873 #endif
 874
 875 void qixis_dump_switch(void)
 876 {
 877         int i, nr_of_cfgsw;
 878
 879         QIXIS_WRITE(cms[0], 0x00);
 880         nr_of_cfgsw = QIXIS_READ(cms[1]);
 881
 882         puts("DIP switch settings dump:\n");
 883         for (i = 1; i <= nr_of_cfgsw; i++) {
 884                 QIXIS_WRITE(cms[0], i);
 885                 printf("SW%d = (0x%02x)\n", i, QIXIS_READ(cms[1]));
 886         }
 887 }