1 // SPDX-License-Identifier: GPL-2.0+
9 #include <fdt_support.h>
22 #include <asm/arch/fsl_serdes.h>
23 #include <fsl-mc/fsl_mc.h>
24 #include <fsl-mc/ldpaa_wriop.h>
25 #include <linux/libfdt.h>
27 #include "../common/qixis.h"
29 DECLARE_GLOBAL_DATA_PTR;
33 #define EMI1 1 /* Mdio Bus 1 */
34 #define EMI2 2 /* Mdio Bus 2 */
36 #if defined(CONFIG_FSL_MC_ENET)
52 struct lx2162a_qds_mdio {
53 enum io_slot ioslot : 4;
55 struct mii_dev *realbus;
58 /* structure explaining the phy configuration on 8 lanes of a serdes*/
59 struct serdes_phy_config {
60 u8 serdes; /* serdes protocol */
63 /* -1 terminated array */
64 int phy_address[WRIOP_MAX_PHY_NUM + 1];
67 } phy_config[SRDS_MAX_LANES];
70 /* Table defining the phy configuration on 8 lanes of a serdes.
71 * Various assumptions have been made while defining this table.
72 * e.g. for serdes1 protocol 19 it is being assumed that X-M11-USXGMII
73 * card is being used for dpmac 3-4. (X-M12-XFI could also have been used)
74 * And also that this card is connected to IO Slot 1 (could have been connected
75 * to any of the 8 IO slots (IO slot 1 - IO slot 8)).
76 * similarly, it is also being assumed that MDIO 1 is selected on X-M7-40G card
77 * used in serdes1 protocol 19 (could have selected MDIO 2)
78 * To override these settings "dpmac" environment variable can be used after
79 * defining "dpmac_override" in hwconfig environment variable.
80 * This table has limited serdes protocol entries. It can be expanded as per
83 /*****************************************************************
84 *| SERDES_1 PROTOCOL | IO_SLOT | CARD |
85 ******************************************************************
86 *| 2 | IO_SLOT_1 | M4-PCIE-SGMII |
87 *| 3 | IO_SLOT_1 | M11-USXGMII |
88 *| 15 | IO_SLOT_1 | M13-25G |
89 *| 17 | IO_SLOT_1 | M13-25G |
90 *| 18 | IO_SLOT_1 | M11-USXGMII |
91 *| | IO_SLOT_6 | M13-25G |
92 *| 20 | IO_SLOT_1 | M7-40G |
93 *****************************************************************
95 static const struct serdes_phy_config serdes1_phy_config[] = {
97 {2, {{WRIOP1_DPMAC3, {SGMII_CARD_PORT1_PHY_ADDR, -1},
99 {WRIOP1_DPMAC4, {SGMII_CARD_PORT2_PHY_ADDR, -1},
101 {WRIOP1_DPMAC5, {SGMII_CARD_PORT3_PHY_ADDR, -1},
103 {WRIOP1_DPMAC6, {SGMII_CARD_PORT4_PHY_ADDR, -1},
104 EMI1, IO_SLOT_1} } },
105 {3, {{WRIOP1_DPMAC3, {AQ_PHY_ADDR1, -1},
107 {WRIOP1_DPMAC4, {AQ_PHY_ADDR2, -1},
109 {WRIOP1_DPMAC5, {AQ_PHY_ADDR3, -1},
111 {WRIOP1_DPMAC6, {AQ_PHY_ADDR4, -1},
112 EMI1, IO_SLOT_1} } },
113 {15, {{WRIOP1_DPMAC1, {INPHI_PHY_ADDR1, INPHI_PHY_ADDR2, -1},
115 {WRIOP1_DPMAC2, {INPHI_PHY_ADDR1, INPHI_PHY_ADDR2, -1},
116 EMI1, IO_SLOT_1} } },
117 {17, {{WRIOP1_DPMAC3, {INPHI_PHY_ADDR1, INPHI_PHY_ADDR2, -1},
119 {WRIOP1_DPMAC4, {INPHI_PHY_ADDR1, INPHI_PHY_ADDR2, -1},
121 {WRIOP1_DPMAC5, {INPHI_PHY_ADDR1, INPHI_PHY_ADDR2, -1},
123 {WRIOP1_DPMAC6, {INPHI_PHY_ADDR1, INPHI_PHY_ADDR2, -1},
124 EMI1, IO_SLOT_1} } },
125 {18, {{WRIOP1_DPMAC3, {AQ_PHY_ADDR1, -1},
127 {WRIOP1_DPMAC4, {AQ_PHY_ADDR2, -1},
129 {WRIOP1_DPMAC5, {INPHI_PHY_ADDR1, INPHI_PHY_ADDR2, -1},
131 {WRIOP1_DPMAC6, {INPHI_PHY_ADDR1, INPHI_PHY_ADDR2, -1},
132 EMI1, IO_SLOT_6} } },
133 {20, {{WRIOP1_DPMAC1, {CORTINA_PHY_ADDR1, -1},
137 /*****************************************************************
138 *| SERDES_2 PROTOCOL | IO_SLOT | CARD |
139 ******************************************************************
140 *| 2 | IO_SLOT_7 | M4-PCIE-SGMII |
141 *| | IO_SLOT_8 | M4-PCIE-SGMII |
142 *| 3 | IO_SLOT_7 | M4-PCIE-SGMII |
143 *| | IO_SLOT_8 | M4-PCIE-SGMII |
144 *| 5 | IO_SLOT_7 | M4-PCIE-SGMII |
145 *| 10 | IO_SLOT_7 | M4-PCIE-SGMII |
146 *| | IO_SLOT_8 | M4-PCIE-SGMII |
147 *| 11 | IO_SLOT_7 | M4-PCIE-SGMII |
148 *| | IO_SLOT_8 | M4-PCIE-SGMII |
149 *| 12 | IO_SLOT_7 | M4-PCIE-SGMII |
150 *| | IO_SLOT_8 | M4-PCIE-SGMII |
151 ******************************************************************
153 static const struct serdes_phy_config serdes2_phy_config[] = {
157 {10, {{WRIOP1_DPMAC11, {SGMII_CARD_PORT1_PHY_ADDR, -1},
159 {WRIOP1_DPMAC12, {SGMII_CARD_PORT2_PHY_ADDR, -1},
161 {WRIOP1_DPMAC17, {SGMII_CARD_PORT3_PHY_ADDR, -1},
163 {WRIOP1_DPMAC18, {SGMII_CARD_PORT4_PHY_ADDR, -1},
164 EMI1, IO_SLOT_7} } },
165 {11, {{WRIOP1_DPMAC12, {SGMII_CARD_PORT2_PHY_ADDR, -1},
167 {WRIOP1_DPMAC17, {SGMII_CARD_PORT3_PHY_ADDR, -1},
169 {WRIOP1_DPMAC18, {SGMII_CARD_PORT4_PHY_ADDR, -1},
171 {WRIOP1_DPMAC16, {SGMII_CARD_PORT2_PHY_ADDR, -1},
173 {WRIOP1_DPMAC13, {SGMII_CARD_PORT3_PHY_ADDR, -1},
175 {WRIOP1_DPMAC14, {SGMII_CARD_PORT4_PHY_ADDR, -1},
176 EMI1, IO_SLOT_8} } },
177 {12, {{WRIOP1_DPMAC11, {SGMII_CARD_PORT1_PHY_ADDR, -1},
179 {WRIOP1_DPMAC12, {SGMII_CARD_PORT2_PHY_ADDR, -1},
181 {WRIOP1_DPMAC17, {SGMII_CARD_PORT3_PHY_ADDR, -1},
183 {WRIOP1_DPMAC18, {SGMII_CARD_PORT4_PHY_ADDR, -1},
188 const struct phy_config *get_phy_config(u8 serdes,
189 const struct serdes_phy_config *table,
194 for (i = 0; i < table_size; i++) {
195 if (table[i].serdes == serdes)
196 return table[i].phy_config;
202 /* BRDCFG4 controls EMI routing for the board.
204 * 7-6 EMI Interface #1 Primary Routing (CFG_MUX1_EMI1) (1.8V):
205 * EMI1 00= On-board PHY #1
206 * 01= On-board PHY #2
208 * 11= Slots 1..8 multiplexer and translator.
209 * 5-3 EMI Interface #1 Secondary Routing (CFG_MUX2_EMI1) (2.5V):
218 * 2-0 EMI Interface #2 Routing (CFG_MUX_EMI2):
219 * EMI2 000= Slot #1 (secondary EMI)
220 * 001= Slot #2 (secondary EMI)
221 * 010= Slot #3 (secondary EMI)
222 * 011= Slot #4 (secondary EMI)
223 * 100= Slot #5 (secondary EMI)
224 * 101= Slot #6 (secondary EMI)
225 * 110= Slot #7 (secondary EMI)
226 * 111= Slot #8 (secondary EMI)
228 static int lx2162a_qds_get_mdio_mux_val(u8 realbusnum, enum io_slot ioslot)
230 switch (realbusnum) {
238 return (((ioslot - 1) << BRDCFG4_EMI1SEL_SHIFT) | 0xC0);
242 return ((ioslot - 1) << BRDCFG4_EMI2SEL_SHIFT);
248 static void lx2162a_qds_mux_mdio(struct lx2162a_qds_mdio *priv)
250 u8 brdcfg4, mux_val, reg;
252 brdcfg4 = QIXIS_READ(brdcfg[4]);
254 mux_val = lx2162a_qds_get_mdio_mux_val(priv->realbusnum, priv->ioslot);
256 switch (priv->realbusnum) {
258 brdcfg4 &= ~BRDCFG4_EMI1SEL_MASK;
262 brdcfg4 &= ~BRDCFG4_EMI2SEL_MASK;
268 QIXIS_WRITE(brdcfg[4], brdcfg4);
271 static int lx2162a_qds_mdio_read(struct mii_dev *bus, int addr,
272 int devad, int regnum)
274 struct lx2162a_qds_mdio *priv = bus->priv;
276 lx2162a_qds_mux_mdio(priv);
278 return priv->realbus->read(priv->realbus, addr, devad, regnum);
281 static int lx2162a_qds_mdio_write(struct mii_dev *bus, int addr, int devad,
282 int regnum, u16 value)
284 struct lx2162a_qds_mdio *priv = bus->priv;
286 lx2162a_qds_mux_mdio(priv);
288 return priv->realbus->write(priv->realbus, addr, devad, regnum, value);
291 static int lx2162a_qds_mdio_reset(struct mii_dev *bus)
293 struct lx2162a_qds_mdio *priv = bus->priv;
295 return priv->realbus->reset(priv->realbus);
298 static struct mii_dev *lx2162a_qds_mdio_init(u8 realbusnum, enum io_slot ioslot)
300 struct lx2162a_qds_mdio *pmdio;
302 /*should be within MDIO_NAME_LEN*/
303 char dummy_mdio_name[] = "LX2162A_QDS_MDIO1_IOSLOT1";
305 if (realbusnum == EMI2) {
306 if (ioslot < IO_SLOT_1 || ioslot > IO_SLOT_8) {
307 printf("invalid ioslot %d\n", ioslot);
310 } else if (realbusnum == EMI1) {
311 if (ioslot < IO_SLOT_1 || ioslot > EMI1_RGMII2) {
312 printf("invalid ioslot %d\n", ioslot);
316 printf("not supported real mdio bus %d\n", realbusnum);
320 if (ioslot == EMI1_RGMII1)
321 strcpy(dummy_mdio_name, "LX2162A_QDS_MDIO1_RGMII1");
322 else if (ioslot == EMI1_RGMII2)
323 strcpy(dummy_mdio_name, "LX2162A_QDS_MDIO1_RGMII2");
325 sprintf(dummy_mdio_name, "LX2162A_QDS_MDIO%d_IOSLOT%d",
327 bus = miiphy_get_dev_by_name(dummy_mdio_name);
334 printf("Failed to allocate %s bus\n", dummy_mdio_name);
338 pmdio = malloc(sizeof(*pmdio));
340 printf("Failed to allocate %s private data\n", dummy_mdio_name);
345 switch (realbusnum) {
348 miiphy_get_dev_by_name(DEFAULT_WRIOP_MDIO1_NAME);
352 miiphy_get_dev_by_name(DEFAULT_WRIOP_MDIO2_NAME);
356 if (!pmdio->realbus) {
357 printf("No real mdio bus num %d found\n", realbusnum);
363 pmdio->realbusnum = realbusnum;
364 pmdio->ioslot = ioslot;
365 bus->read = lx2162a_qds_mdio_read;
366 bus->write = lx2162a_qds_mdio_write;
367 bus->reset = lx2162a_qds_mdio_reset;
368 strcpy(bus->name, dummy_mdio_name);
371 if (!mdio_register(bus))
374 printf("No bus with name %s\n", dummy_mdio_name);
380 static inline void do_phy_config(const struct phy_config *phy_config)
383 int i, phy_num, phy_address;
385 for (i = 0; i < SRDS_MAX_LANES; i++) {
386 if (!phy_config[i].dpmacid)
390 phy_num < ARRAY_SIZE(phy_config[i].phy_address);
392 phy_address = phy_config[i].phy_address[phy_num];
393 if (phy_address == -1)
395 wriop_set_phy_address(phy_config[i].dpmacid,
396 phy_num, phy_address);
398 /*Register the muxing front-ends to the MDIO buses*/
399 bus = lx2162a_qds_mdio_init(phy_config[i].mdio_bus,
400 phy_config[i].ioslot);
402 printf("could not get bus for mdio %d ioslot %d\n",
403 phy_config[i].mdio_bus,
404 phy_config[i].ioslot);
406 wriop_set_mdio(phy_config[i].dpmacid, bus);
410 static inline void do_dpmac_config(int dpmac, const char *arg_dpmacid,
415 u8 realbusnum, ioslot;
418 char *phystr = "phy00";
420 /*search phy in dpmac arg*/
421 for (phy_num = 0; phy_num < WRIOP_MAX_PHY_NUM; phy_num++) {
422 sprintf(phystr, "phy%d", phy_num + 1);
423 ret = hwconfig_subarg_f(arg_dpmacid, phystr, &len, env_dpmac);
425 /*look for phy instead of phy1*/
427 ret = hwconfig_subarg_f(arg_dpmacid, "phy",
433 if (len != 4 || strncmp(ret, "0x", 2))
434 printf("invalid phy format in %s variable.\n"
435 "specify phy%d for %s in hex format e.g. 0x12\n",
436 env_dpmac, phy_num + 1, arg_dpmacid);
438 wriop_set_phy_address(dpmac, phy_num,
439 simple_strtoul(ret, NULL, 16));
442 /*search mdio in dpmac arg*/
443 ret = hwconfig_subarg_f(arg_dpmacid, "mdio", &len, env_dpmac);
445 realbusnum = *ret - '0';
447 realbusnum = EMI_NONE;
450 /*search io in dpmac arg*/
451 ret = hwconfig_subarg_f(arg_dpmacid, "io", &len, env_dpmac);
455 ioslot = IO_SLOT_NONE;
456 /*Register the muxing front-ends to the MDIO buses*/
457 bus = lx2162a_qds_mdio_init(realbusnum, ioslot);
459 printf("could not get bus for mdio %d ioslot %d\n",
462 wriop_set_mdio(dpmac, bus);
467 #endif /* !CONFIG_DM_ETH */
469 int board_eth_init(struct bd_info *bis)
471 #ifndef CONFIG_DM_ETH
472 #if defined(CONFIG_FSL_MC_ENET)
473 struct memac_mdio_info mdio_info;
474 struct memac_mdio_controller *regs;
478 char dpmacid[] = "dpmac00", srds[] = "00_00_00";
481 const struct phy_config *phy_config;
482 struct ccsr_gur *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR);
483 u32 srds_s1, srds_s2;
485 srds_s1 = in_le32(&gur->rcwsr[28]) &
486 FSL_CHASSIS3_RCWSR28_SRDS1_PRTCL_MASK;
487 srds_s1 >>= FSL_CHASSIS3_RCWSR28_SRDS1_PRTCL_SHIFT;
489 srds_s2 = in_le32(&gur->rcwsr[28]) &
490 FSL_CHASSIS3_RCWSR28_SRDS2_PRTCL_MASK;
491 srds_s2 >>= FSL_CHASSIS3_RCWSR28_SRDS2_PRTCL_SHIFT;
493 sprintf(srds, "%d_%d", srds_s1, srds_s2);
495 regs = (struct memac_mdio_controller *)CONFIG_SYS_FSL_WRIOP1_MDIO1;
496 mdio_info.regs = regs;
497 mdio_info.name = DEFAULT_WRIOP_MDIO1_NAME;
499 /*Register the EMI 1*/
500 fm_memac_mdio_init(bis, &mdio_info);
502 regs = (struct memac_mdio_controller *)CONFIG_SYS_FSL_WRIOP1_MDIO2;
503 mdio_info.regs = regs;
504 mdio_info.name = DEFAULT_WRIOP_MDIO2_NAME;
506 /*Register the EMI 2*/
507 fm_memac_mdio_init(bis, &mdio_info);
509 /* "dpmac" environment variable can be used after
510 * defining "dpmac_override" in hwconfig environment variable.
512 if (hwconfig("dpmac_override")) {
513 env_dpmac = env_get("dpmac");
515 ret = hwconfig_arg_f("srds", &len, env_dpmac);
517 if (strncmp(ret, srds, strlen(srds))) {
518 printf("SERDES configuration changed.\n"
519 "previous: %.*s, current: %s.\n"
520 "update dpmac variable.\n",
521 (int)len, ret, srds);
524 printf("SERDES configuration not found.\n"
525 "Please add srds:%s in dpmac variable\n",
529 for (i = WRIOP1_DPMAC1; i < NUM_WRIOP_PORTS; i++) {
530 /* Look for dpmac1 to dpmac24(current max) arg
531 * in dpmac environment variable
533 sprintf(dpmacid, "dpmac%d", i);
534 ret = hwconfig_arg_f(dpmacid, &len, env_dpmac);
536 do_dpmac_config(i, dpmacid, env_dpmac);
539 printf("Warning: environment dpmac not found.\n"
540 "DPAA network interfaces may not work\n");
543 /*Look for phy config for serdes1 in phy config table*/
544 phy_config = get_phy_config(srds_s1, serdes1_phy_config,
545 ARRAY_SIZE(serdes1_phy_config));
547 printf("%s WRIOP: Unsupported SerDes1 Protocol %d\n",
550 do_phy_config(phy_config);
552 phy_config = get_phy_config(srds_s2, serdes2_phy_config,
553 ARRAY_SIZE(serdes2_phy_config));
555 printf("%s WRIOP: Unsupported SerDes2 Protocol %d\n",
558 do_phy_config(phy_config);
562 if (wriop_get_enet_if(WRIOP1_DPMAC17) == PHY_INTERFACE_MODE_RGMII_ID) {
563 wriop_set_phy_address(WRIOP1_DPMAC17, 0, RGMII_PHY_ADDR1);
564 bus = lx2162a_qds_mdio_init(EMI1, EMI1_RGMII1);
566 printf("could not get bus for RGMII1\n");
568 wriop_set_mdio(WRIOP1_DPMAC17, bus);
571 if (wriop_get_enet_if(WRIOP1_DPMAC18) == PHY_INTERFACE_MODE_RGMII_ID) {
572 wriop_set_phy_address(WRIOP1_DPMAC18, 0, RGMII_PHY_ADDR2);
573 bus = lx2162a_qds_mdio_init(EMI1, EMI1_RGMII2);
575 printf("could not get bus for RGMII2\n");
577 wriop_set_mdio(WRIOP1_DPMAC18, bus);
581 #endif /* CONFIG_FMAN_ENET */
582 #endif /* !CONFIG_DM_ETH */
584 #ifdef CONFIG_PHY_AQUANTIA
586 * Export functions to be used by AQ firmware
589 gd->jt->strcpy = strcpy;
590 gd->jt->mdelay = mdelay;
591 gd->jt->mdio_get_current_dev = mdio_get_current_dev;
592 gd->jt->phy_find_by_mask = phy_find_by_mask;
593 gd->jt->mdio_phydev_for_ethname = mdio_phydev_for_ethname;
594 gd->jt->miiphy_set_current_dev = miiphy_set_current_dev;
600 return pci_eth_init(bis);
604 #if defined(CONFIG_RESET_PHY_R)
607 #if defined(CONFIG_FSL_MC_ENET)
611 #endif /* CONFIG_RESET_PHY_R */
613 #ifndef CONFIG_DM_ETH
614 #if defined(CONFIG_FSL_MC_ENET)
615 int fdt_fixup_dpmac_phy_handle(void *fdt, int dpmac_id, int node_phandle)
619 char dpmac_str[] = "dpmacs@00";
620 const char *phy_string;
622 offset = fdt_path_offset(fdt, "/soc/fsl-mc/dpmacs");
625 offset = fdt_path_offset(fdt, "/fsl-mc/dpmacs");
628 printf("dpmacs node not found in device tree\n");
632 sprintf(dpmac_str, "dpmac@%x", dpmac_id);
633 debug("dpmac_str = %s\n", dpmac_str);
635 offset = fdt_subnode_offset(fdt, offset, dpmac_str);
637 printf("%s node not found in device tree\n", dpmac_str);
641 phy_string = fdt_getprop(fdt, offset, "phy-connection-type", NULL);
642 if (is_backplane_mode(phy_string)) {
643 /* Backplane KR mode: skip fixups */
644 printf("Interface %d in backplane KR mode\n", dpmac_id);
648 ret = fdt_appendprop_cell(fdt, offset, "phy-handle", node_phandle);
650 printf("%d@%s %d\n", __LINE__, __func__, ret);
652 phy_string = phy_string_for_interface(wriop_get_enet_if(dpmac_id));
653 ret = fdt_setprop_string(fdt, offset, "phy-connection-type",
656 printf("%d@%s %d\n", __LINE__, __func__, ret);
661 int fdt_get_ioslot_offset(void *fdt, struct mii_dev *mii_dev, int fpga_offset)
663 char mdio_ioslot_str[] = "mdio@00";
664 struct lx2162a_qds_mdio *priv;
669 /*Test if the MDIO bus is real mdio bus or muxing front end ?*/
670 if (strncmp(mii_dev->name, "LX2162A_QDS_MDIO",
671 strlen("LX2162A_QDS_MDIO")))
674 /*Get the real MDIO bus num and ioslot info from bus's priv data*/
675 priv = mii_dev->priv;
677 debug("real_bus_num = %d, ioslot = %d\n",
678 priv->realbusnum, priv->ioslot);
680 if (priv->realbusnum == EMI1)
681 reg = CONFIG_SYS_FSL_WRIOP1_MDIO1;
683 reg = CONFIG_SYS_FSL_WRIOP1_MDIO2;
685 offset = fdt_node_offset_by_compat_reg(fdt, "fsl,fman-memac-mdio", reg);
687 printf("mdio@%llx node not found in device tree\n", reg);
691 phandle = fdt_get_phandle(fdt, offset);
692 phandle = cpu_to_fdt32(phandle);
693 offset = fdt_node_offset_by_prop_value(fdt, -1, "mdio-parent-bus",
696 printf("mdio-mux-%d node not found in device tree\n",
697 priv->realbusnum == EMI1 ? 1 : 2);
701 mux_val = lx2162a_qds_get_mdio_mux_val(priv->realbusnum, priv->ioslot);
702 if (priv->realbusnum == EMI1)
703 mux_val >>= BRDCFG4_EMI1SEL_SHIFT;
705 mux_val >>= BRDCFG4_EMI2SEL_SHIFT;
706 sprintf(mdio_ioslot_str, "mdio@%x", (u8)mux_val);
708 offset = fdt_subnode_offset(fdt, offset, mdio_ioslot_str);
710 printf("%s node not found in device tree\n", mdio_ioslot_str);
717 int fdt_create_phy_node(void *fdt, int offset, u8 phyaddr, int *subnodeoffset,
718 struct phy_device *phy_dev, int phandle)
720 char phy_node_name[] = "ethernet-phy@00";
721 char phy_id_compatible_str[] = "ethernet-phy-id0000.0000,";
724 sprintf(phy_node_name, "ethernet-phy@%x", phyaddr);
725 debug("phy_node_name = %s\n", phy_node_name);
727 *subnodeoffset = fdt_add_subnode(fdt, offset, phy_node_name);
728 if (*subnodeoffset <= 0) {
729 printf("Could not add subnode %s inside node %s err = %s\n",
730 phy_node_name, fdt_get_name(fdt, offset, NULL),
731 fdt_strerror(*subnodeoffset));
732 return *subnodeoffset;
735 sprintf(phy_id_compatible_str, "ethernet-phy-id%04x.%04x,",
736 phy_dev->phy_id >> 16, phy_dev->phy_id & 0xFFFF);
737 debug("phy_id_compatible_str %s\n", phy_id_compatible_str);
739 ret = fdt_setprop_string(fdt, *subnodeoffset, "compatible",
740 phy_id_compatible_str);
742 printf("%d@%s %d\n", __LINE__, __func__, ret);
746 if (phy_dev->is_c45) {
747 ret = fdt_appendprop_string(fdt, *subnodeoffset, "compatible",
748 "ethernet-phy-ieee802.3-c45");
750 printf("%d@%s %d\n", __LINE__, __func__, ret);
754 ret = fdt_appendprop_string(fdt, *subnodeoffset, "compatible",
755 "ethernet-phy-ieee802.3-c22");
757 printf("%d@%s %d\n", __LINE__, __func__, ret);
762 ret = fdt_setprop_cell(fdt, *subnodeoffset, "reg", phyaddr);
764 printf("%d@%s %d\n", __LINE__, __func__, ret);
768 ret = fdt_set_phandle(fdt, *subnodeoffset, phandle);
770 printf("%d@%s %d\n", __LINE__, __func__, ret);
776 fdt_del_node(fdt, *subnodeoffset);
781 #define is_rgmii(dpmac_id) \
782 wriop_get_enet_if((dpmac_id)) == PHY_INTERFACE_MODE_RGMII_ID
784 int fdt_fixup_board_phy(void *fdt)
786 int fpga_offset, offset, subnodeoffset;
787 struct mii_dev *mii_dev;
788 struct list_head *mii_devs, *entry;
789 int ret, dpmac_id, phandle, i;
790 struct phy_device *phy_dev;
791 char ethname[ETH_NAME_LEN];
792 phy_interface_t phy_iface;
795 /* we know FPGA is connected to i2c0, therefore search path directly,
796 * instead of compatible property, as it saves time
798 fpga_offset = fdt_path_offset(fdt, "/soc/i2c@2000000/fpga");
801 fpga_offset = fdt_path_offset(fdt, "/i2c@2000000/fpga");
803 if (fpga_offset < 0) {
804 printf("i2c@2000000/fpga node not found in device tree\n");
808 phandle = fdt_alloc_phandle(fdt);
809 mii_devs = mdio_get_list_head();
811 list_for_each(entry, mii_devs) {
812 mii_dev = list_entry(entry, struct mii_dev, link);
813 debug("mii_dev name : %s\n", mii_dev->name);
814 offset = fdt_get_ioslot_offset(fdt, mii_dev, fpga_offset);
818 // Look for phy devices attached to MDIO bus muxing front end
819 // and create their entries with compatible being the device id
820 for (i = 0; i < PHY_MAX_ADDR; i++) {
821 phy_dev = mii_dev->phymap[i];
825 // TODO: use sscanf instead of loop
826 dpmac_id = WRIOP1_DPMAC1;
827 while (dpmac_id < NUM_WRIOP_PORTS) {
828 phy_iface = wriop_get_enet_if(dpmac_id);
829 snprintf(ethname, ETH_NAME_LEN, "DPMAC%d@%s",
831 phy_string_for_interface(phy_iface));
832 if (strcmp(ethname, phy_dev->dev->name) == 0)
836 if (dpmac_id == NUM_WRIOP_PORTS)
839 if ((dpmac_id == 17 || dpmac_id == 18) &&
843 ret = fdt_create_phy_node(fdt, offset, i,
849 ret = fdt_fixup_dpmac_phy_handle(fdt,
852 fdt_del_node(fdt, subnodeoffset);
855 /* calculate offset again as new node addition may have
858 offset = fdt_get_ioslot_offset(fdt, mii_dev,
869 #endif // CONFIG_FSL_MC_ENET
872 #if defined(CONFIG_DM_ETH) && defined(CONFIG_MULTI_DTB_FIT)
874 /* Structure to hold SERDES protocols supported in case of
875 * CONFIG_DM_ETH enabled (network interfaces are described in the DTS).
877 * @serdes_block: the index of the SERDES block
878 * @serdes_protocol: the decimal value of the protocol supported
879 * @dts_needed: DTS notes describing the current configuration are needed
881 * When dts_needed is true, the board_fit_config_name_match() function
882 * will try to exactly match the current configuration of the block with a DTS
885 static struct serdes_configuration {
889 } supported_protocols[] = {
890 /* Serdes block #1 */
898 /* Serdes block #2 */
907 #define SUPPORTED_SERDES_PROTOCOLS ARRAY_SIZE(supported_protocols)
909 static bool protocol_supported(u8 serdes_block, u32 protocol)
911 struct serdes_configuration serdes_conf;
914 for (i = 0; i < SUPPORTED_SERDES_PROTOCOLS; i++) {
915 serdes_conf = supported_protocols[i];
916 if (serdes_conf.serdes_block == serdes_block &&
917 serdes_conf.serdes_protocol == protocol)
924 static void get_str_protocol(u8 serdes_block, u32 protocol, char *str)
926 struct serdes_configuration serdes_conf;
929 for (i = 0; i < SUPPORTED_SERDES_PROTOCOLS; i++) {
930 serdes_conf = supported_protocols[i];
931 if (serdes_conf.serdes_block == serdes_block &&
932 serdes_conf.serdes_protocol == protocol) {
933 if (serdes_conf.dts_needed == true)
934 sprintf(str, "%u", protocol);
942 int board_fit_config_name_match(const char *name)
944 struct ccsr_gur *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR);
945 u32 rcw_status = in_le32(&gur->rcwsr[28]);
946 char srds_s1_str[2], srds_s2_str[2];
947 u32 srds_s1, srds_s2;
948 char expected_dts[100];
950 srds_s1 = rcw_status & FSL_CHASSIS3_RCWSR28_SRDS1_PRTCL_MASK;
951 srds_s1 >>= FSL_CHASSIS3_RCWSR28_SRDS1_PRTCL_SHIFT;
953 srds_s2 = rcw_status & FSL_CHASSIS3_RCWSR28_SRDS2_PRTCL_MASK;
954 srds_s2 >>= FSL_CHASSIS3_RCWSR28_SRDS2_PRTCL_SHIFT;
956 /* Check for supported protocols. The default DTS will be used
959 if (!protocol_supported(1, srds_s1) ||
960 !protocol_supported(2, srds_s2))
963 get_str_protocol(1, srds_s1, srds_s1_str);
964 get_str_protocol(2, srds_s2, srds_s2_str);
966 sprintf(expected_dts, "fsl-lx2160a-qds-%s-%s",
967 srds_s1_str, srds_s2_str);
969 if (!strcmp(name, expected_dts))