board/freescale/lx2160a/eth_lx2160ardb.c

   1 // SPDX-License-Identifier: GPL-2.0+
   2 /*
   3  * Copyright 2018 NXP
   4  *
   5  */
   6
   7 #include <common.h>
   8 #include <command.h>
   9 #include <fdt_support.h>
  10 #include <net.h>
  11 #include <netdev.h>
  12 #include <malloc.h>
  13 #include <fsl_mdio.h>
  14 #include <miiphy.h>
  15 #include <phy.h>
  16 #include <fm_eth.h>
  17 #include <asm/io.h>
  18 #include <exports.h>
  19 #include <asm/arch/fsl_serdes.h>
  20 #include <fsl-mc/fsl_mc.h>
  21 #include <fsl-mc/ldpaa_wriop.h>
  22
  23 DECLARE_GLOBAL_DATA_PTR;
  24
  25 static bool get_inphi_phy_id(struct mii_dev *bus, int addr, int devad)
  26 {
  27         int phy_reg;
  28         u32 phy_id;
  29
  30         phy_reg = bus->read(bus, addr, devad, MII_PHYSID1);
  31         phy_id = (phy_reg & 0xffff) << 16;
  32
  33         phy_reg = bus->read(bus, addr, devad, MII_PHYSID2);
  34         phy_id |= (phy_reg & 0xffff);
  35
  36         if (phy_id == PHY_UID_IN112525_S03)
  37                 return true;
  38         else
  39                 return false;
  40 }
  41
  42 int board_eth_init(struct bd_info *bis)
  43 {
  44 #if defined(CONFIG_FSL_MC_ENET)
  45         struct memac_mdio_info mdio_info;
  46         struct memac_mdio_controller *reg;
  47         int i, interface;
  48         struct mii_dev *dev;
  49         struct ccsr_gur *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR);
  50         u32 srds_s1;
  51
  52         srds_s1 = in_le32(&gur->rcwsr[28]) &
  53                                 FSL_CHASSIS3_RCWSR28_SRDS1_PRTCL_MASK;
  54         srds_s1 >>= FSL_CHASSIS3_RCWSR28_SRDS1_PRTCL_SHIFT;
  55
  56         reg = (struct memac_mdio_controller *)CONFIG_SYS_FSL_WRIOP1_MDIO1;
  57         mdio_info.regs = reg;
  58         mdio_info.name = DEFAULT_WRIOP_MDIO1_NAME;
  59
  60         /* Register the EMI 1 */
  61         fm_memac_mdio_init(bis, &mdio_info);
  62
  63         reg = (struct memac_mdio_controller *)CONFIG_SYS_FSL_WRIOP1_MDIO2;
  64         mdio_info.regs = reg;
  65         mdio_info.name = DEFAULT_WRIOP_MDIO2_NAME;
  66
  67         /* Register the EMI 2 */
  68         fm_memac_mdio_init(bis, &mdio_info);
  69
  70         dev = miiphy_get_dev_by_name(DEFAULT_WRIOP_MDIO2_NAME);
  71         switch (srds_s1) {
  72         case 19:
  73                 wriop_set_phy_address(WRIOP1_DPMAC2, 0,
  74                                       CORTINA_PHY_ADDR1);
  75                 wriop_set_phy_address(WRIOP1_DPMAC3, 0,
  76                                       AQR107_PHY_ADDR1);
  77                 wriop_set_phy_address(WRIOP1_DPMAC4, 0,
  78                                       AQR107_PHY_ADDR2);
  79                 if (get_inphi_phy_id(dev, INPHI_PHY_ADDR1, MDIO_MMD_VEND1)) {
  80                         wriop_set_phy_address(WRIOP1_DPMAC5, 0,
  81                                               INPHI_PHY_ADDR1);
  82                         wriop_set_phy_address(WRIOP1_DPMAC6, 0,
  83                                               INPHI_PHY_ADDR1);
  84                 }
  85                 wriop_set_phy_address(WRIOP1_DPMAC17, 0,
  86                                       RGMII_PHY_ADDR1);
  87                 wriop_set_phy_address(WRIOP1_DPMAC18, 0,
  88                                       RGMII_PHY_ADDR2);
  89                 break;
  90
  91         case 18:
  92                 wriop_set_phy_address(WRIOP1_DPMAC7, 0,
  93                                       CORTINA_PHY_ADDR1);
  94                 wriop_set_phy_address(WRIOP1_DPMAC8, 0,
  95                                       CORTINA_PHY_ADDR1);
  96                 wriop_set_phy_address(WRIOP1_DPMAC9, 0,
  97                                       CORTINA_PHY_ADDR1);
  98                 wriop_set_phy_address(WRIOP1_DPMAC10, 0,
  99                                       CORTINA_PHY_ADDR1);
 100                 wriop_set_phy_address(WRIOP1_DPMAC3, 0,
 101                                       AQR107_PHY_ADDR1);
 102                 wriop_set_phy_address(WRIOP1_DPMAC4, 0,
 103                                       AQR107_PHY_ADDR2);
 104                 if (get_inphi_phy_id(dev, INPHI_PHY_ADDR1, MDIO_MMD_VEND1)) {
 105                         wriop_set_phy_address(WRIOP1_DPMAC5, 0,
 106                                               INPHI_PHY_ADDR1);
 107                         wriop_set_phy_address(WRIOP1_DPMAC6, 0,
 108                                               INPHI_PHY_ADDR1);
 109                 }
 110                 wriop_set_phy_address(WRIOP1_DPMAC17, 0,
 111                                       RGMII_PHY_ADDR1);
 112                 wriop_set_phy_address(WRIOP1_DPMAC18, 0,
 113                                       RGMII_PHY_ADDR2);
 114                 break;
 115
 116         default:
 117                 printf("SerDes1 protocol 0x%x is not supported on LX2160ARDB\n",
 118                        srds_s1);
 119                 goto next;
 120         }
 121
 122         for (i = WRIOP1_DPMAC2; i <= WRIOP1_DPMAC10; i++) {
 123                 interface = wriop_get_enet_if(i);
 124                 switch (interface) {
 125                 case PHY_INTERFACE_MODE_XGMII:
 126                         dev = miiphy_get_dev_by_name(DEFAULT_WRIOP_MDIO1_NAME);
 127                         wriop_set_mdio(i, dev);
 128                         break;
 129                 case PHY_INTERFACE_MODE_25G_AUI:
 130                         dev = miiphy_get_dev_by_name(DEFAULT_WRIOP_MDIO2_NAME);
 131                         wriop_set_mdio(i, dev);
 132                         break;
 133                 case PHY_INTERFACE_MODE_XLAUI:
 134                         dev = miiphy_get_dev_by_name(DEFAULT_WRIOP_MDIO1_NAME);
 135                         wriop_set_mdio(i, dev);
 136                         break;
 137                 default:
 138                         break;
 139                 }
 140         }
 141         for (i = WRIOP1_DPMAC17; i <= WRIOP1_DPMAC18; i++) {
 142                 interface = wriop_get_enet_if(i);
 143                 switch (interface) {
 144                 case PHY_INTERFACE_MODE_RGMII:
 145                 case PHY_INTERFACE_MODE_RGMII_ID:
 146                         dev = miiphy_get_dev_by_name(DEFAULT_WRIOP_MDIO1_NAME);
 147                         wriop_set_mdio(i, dev);
 148                         break;
 149                 default:
 150                         break;
 151                 }
 152         }
 153
 154 next:
 155         cpu_eth_init(bis);
 156 #endif /* CONFIG_FSL_MC_ENET */
 157
 158 #ifdef CONFIG_PHY_AQUANTIA
 159         /*
 160          * Export functions to be used by AQ firmware
 161          * upload application
 162          */
 163         gd->jt->strcpy = strcpy;
 164         gd->jt->mdelay = mdelay;
 165         gd->jt->mdio_get_current_dev = mdio_get_current_dev;
 166         gd->jt->phy_find_by_mask = phy_find_by_mask;
 167         gd->jt->mdio_phydev_for_ethname = mdio_phydev_for_ethname;
 168         gd->jt->miiphy_set_current_dev = miiphy_set_current_dev;
 169 #endif
 170         return pci_eth_init(bis);
 171 }
 172
 173 #if defined(CONFIG_RESET_PHY_R)
 174 void reset_phy(void)
 175 {
 176 #if defined(CONFIG_FSL_MC_ENET)
 177         mc_env_boot();
 178 #endif
 179 }
 180 #endif /* CONFIG_RESET_PHY_R */
 181
 182 int fdt_fixup_board_phy(void *fdt)
 183 {
 184         int mdio_offset;
 185         int ret;
 186         struct mii_dev *dev;
 187
 188         ret = 0;
 189
 190         dev = miiphy_get_dev_by_name(DEFAULT_WRIOP_MDIO2_NAME);
 191         if (!get_inphi_phy_id(dev, INPHI_PHY_ADDR1, MDIO_MMD_VEND1)) {
 192                 mdio_offset = fdt_path_offset(fdt, "/soc/mdio@0x8B97000");
 193
 194                 if (mdio_offset < 0)
 195                         mdio_offset = fdt_path_offset(fdt, "/mdio@0x8B97000");
 196
 197                 if (mdio_offset < 0) {
 198                         printf("mdio@0x8B9700 node not found in dts\n");
 199                         return mdio_offset;
 200                 }
 201
 202                 ret = fdt_setprop_string(fdt, mdio_offset, "status",
 203                                          "disabled");
 204                 if (ret) {
 205                         printf("Could not set disable mdio@0x8B97000 %s\n",
 206                                fdt_strerror(ret));
 207                         return ret;
 208                 }
 209         }
 210
 211         return ret;
 212 }