board/freescale/lx2160a/eth_lx2160ardb.c

   1 // SPDX-License-Identifier: GPL-2.0+
   2 /*
   3  * Copyright 2018, 2020 NXP
   4  *
   5  */
   6
   7 #include <common.h>
   8 #include <command.h>
   9 #include <fdt_support.h>
  10 #include <net.h>
  11 #include <netdev.h>
  12 #include <malloc.h>
  13 #include <fsl_mdio.h>
  14 #include <miiphy.h>
  15 #include <phy.h>
  16 #include <fm_eth.h>
  17 #include <asm/io.h>
  18 #include <exports.h>
  19 #include <asm/arch/fsl_serdes.h>
  20 #include <fsl-mc/fsl_mc.h>
  21 #include <fsl-mc/ldpaa_wriop.h>
  22 #include "lx2160a.h"
  23
  24 DECLARE_GLOBAL_DATA_PTR;
  25
  26 static bool get_inphi_phy_id(struct mii_dev *bus, int addr, int devad)
  27 {
  28         int phy_reg;
  29         u32 phy_id;
  30
  31         phy_reg = bus->read(bus, addr, devad, MII_PHYSID1);
  32         phy_id = (phy_reg & 0xffff) << 16;
  33
  34         phy_reg = bus->read(bus, addr, devad, MII_PHYSID2);
  35         phy_id |= (phy_reg & 0xffff);
  36
  37         if (phy_id == PHY_UID_IN112525_S03)
  38                 return true;
  39         else
  40                 return false;
  41 }
  42
  43 int board_eth_init(struct bd_info *bis)
  44 {
  45 #if defined(CONFIG_FSL_MC_ENET)
  46         struct memac_mdio_info mdio_info;
  47         struct memac_mdio_controller *reg;
  48         int i, interface;
  49         struct mii_dev *dev;
  50         struct ccsr_gur *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR);
  51         u32 srds_s1;
  52
  53         srds_s1 = in_le32(&gur->rcwsr[28]) &
  54                                 FSL_CHASSIS3_RCWSR28_SRDS1_PRTCL_MASK;
  55         srds_s1 >>= FSL_CHASSIS3_RCWSR28_SRDS1_PRTCL_SHIFT;
  56
  57         reg = (struct memac_mdio_controller *)CONFIG_SYS_FSL_WRIOP1_MDIO1;
  58         mdio_info.regs = reg;
  59         mdio_info.name = DEFAULT_WRIOP_MDIO1_NAME;
  60
  61         /* Register the EMI 1 */
  62         fm_memac_mdio_init(bis, &mdio_info);
  63
  64         reg = (struct memac_mdio_controller *)CONFIG_SYS_FSL_WRIOP1_MDIO2;
  65         mdio_info.regs = reg;
  66         mdio_info.name = DEFAULT_WRIOP_MDIO2_NAME;
  67
  68         /* Register the EMI 2 */
  69         fm_memac_mdio_init(bis, &mdio_info);
  70
  71         dev = miiphy_get_dev_by_name(DEFAULT_WRIOP_MDIO2_NAME);
  72         switch (srds_s1) {
  73         case 19:
  74                 wriop_set_phy_address(WRIOP1_DPMAC2, 0,
  75                                       CORTINA_PHY_ADDR1);
  76                 wriop_set_phy_address(WRIOP1_DPMAC3, 0,
  77                                       AQR107_PHY_ADDR1);
  78                 wriop_set_phy_address(WRIOP1_DPMAC4, 0,
  79                                       AQR107_PHY_ADDR2);
  80                 if (get_inphi_phy_id(dev, INPHI_PHY_ADDR1, MDIO_MMD_VEND1)) {
  81                         wriop_set_phy_address(WRIOP1_DPMAC5, 0,
  82                                               INPHI_PHY_ADDR1);
  83                         wriop_set_phy_address(WRIOP1_DPMAC6, 0,
  84                                               INPHI_PHY_ADDR1);
  85                 }
  86                 wriop_set_phy_address(WRIOP1_DPMAC17, 0,
  87                                       RGMII_PHY_ADDR1);
  88                 wriop_set_phy_address(WRIOP1_DPMAC18, 0,
  89                                       RGMII_PHY_ADDR2);
  90                 break;
  91
  92         case 18:
  93                 wriop_set_phy_address(WRIOP1_DPMAC7, 0,
  94                                       CORTINA_PHY_ADDR1);
  95                 wriop_set_phy_address(WRIOP1_DPMAC8, 0,
  96                                       CORTINA_PHY_ADDR1);
  97                 wriop_set_phy_address(WRIOP1_DPMAC9, 0,
  98                                       CORTINA_PHY_ADDR1);
  99                 wriop_set_phy_address(WRIOP1_DPMAC10, 0,
 100                                       CORTINA_PHY_ADDR1);
 101                 wriop_set_phy_address(WRIOP1_DPMAC3, 0,
 102                                       AQR107_PHY_ADDR1);
 103                 wriop_set_phy_address(WRIOP1_DPMAC4, 0,
 104                                       AQR107_PHY_ADDR2);
 105                 if (get_inphi_phy_id(dev, INPHI_PHY_ADDR1, MDIO_MMD_VEND1)) {
 106                         wriop_set_phy_address(WRIOP1_DPMAC5, 0,
 107                                               INPHI_PHY_ADDR1);
 108                         wriop_set_phy_address(WRIOP1_DPMAC6, 0,
 109                                               INPHI_PHY_ADDR1);
 110                 }
 111                 wriop_set_phy_address(WRIOP1_DPMAC17, 0,
 112                                       RGMII_PHY_ADDR1);
 113                 wriop_set_phy_address(WRIOP1_DPMAC18, 0,
 114                                       RGMII_PHY_ADDR2);
 115                 break;
 116
 117         default:
 118                 printf("SerDes1 protocol 0x%x is not supported on LX2160ARDB\n",
 119                        srds_s1);
 120                 goto next;
 121         }
 122
 123         for (i = WRIOP1_DPMAC2; i <= WRIOP1_DPMAC10; i++) {
 124                 interface = wriop_get_enet_if(i);
 125                 switch (interface) {
 126                 case PHY_INTERFACE_MODE_XGMII:
 127                         dev = miiphy_get_dev_by_name(DEFAULT_WRIOP_MDIO1_NAME);
 128                         wriop_set_mdio(i, dev);
 129                         break;
 130                 case PHY_INTERFACE_MODE_25G_AUI:
 131                         dev = miiphy_get_dev_by_name(DEFAULT_WRIOP_MDIO2_NAME);
 132                         wriop_set_mdio(i, dev);
 133                         break;
 134                 case PHY_INTERFACE_MODE_XLAUI:
 135                         dev = miiphy_get_dev_by_name(DEFAULT_WRIOP_MDIO1_NAME);
 136                         wriop_set_mdio(i, dev);
 137                         break;
 138                 default:
 139                         break;
 140                 }
 141         }
 142         for (i = WRIOP1_DPMAC17; i <= WRIOP1_DPMAC18; i++) {
 143                 interface = wriop_get_enet_if(i);
 144                 switch (interface) {
 145                 case PHY_INTERFACE_MODE_RGMII:
 146                 case PHY_INTERFACE_MODE_RGMII_ID:
 147                         dev = miiphy_get_dev_by_name(DEFAULT_WRIOP_MDIO1_NAME);
 148                         wriop_set_mdio(i, dev);
 149                         break;
 150                 default:
 151                         break;
 152                 }
 153         }
 154
 155 next:
 156         cpu_eth_init(bis);
 157 #endif /* CONFIG_FSL_MC_ENET */
 158
 159 #ifdef CONFIG_PHY_AQUANTIA
 160         /*
 161          * Export functions to be used by AQ firmware
 162          * upload application
 163          */
 164         gd->jt->strcpy = strcpy;
 165         gd->jt->mdelay = mdelay;
 166         gd->jt->mdio_get_current_dev = mdio_get_current_dev;
 167         gd->jt->phy_find_by_mask = phy_find_by_mask;
 168         gd->jt->mdio_phydev_for_ethname = mdio_phydev_for_ethname;
 169         gd->jt->miiphy_set_current_dev = miiphy_set_current_dev;
 170 #endif
 171         return pci_eth_init(bis);
 172 }
 173
 174 #if defined(CONFIG_RESET_PHY_R)
 175 void reset_phy(void)
 176 {
 177 #if defined(CONFIG_FSL_MC_ENET)
 178         mc_env_boot();
 179 #endif
 180 }
 181 #endif /* CONFIG_RESET_PHY_R */
 182
 183 int fdt_fixup_board_phy(void *fdt)
 184 {
 185         int mdio_offset;
 186         int ret;
 187         struct mii_dev *dev;
 188
 189         ret = 0;
 190
 191         dev = miiphy_get_dev_by_name(DEFAULT_WRIOP_MDIO2_NAME);
 192         if (!get_inphi_phy_id(dev, INPHI_PHY_ADDR1, MDIO_MMD_VEND1)) {
 193                 mdio_offset = fdt_path_offset(fdt, "/soc/mdio@0x8B97000");
 194
 195                 if (mdio_offset < 0)
 196                         mdio_offset = fdt_path_offset(fdt, "/mdio@0x8B97000");
 197
 198                 if (mdio_offset < 0) {
 199                         printf("mdio@0x8B9700 node not found in dts\n");
 200                         return mdio_offset;
 201                 }
 202
 203                 ret = fdt_setprop_string(fdt, mdio_offset, "status",
 204                                          "disabled");
 205                 if (ret) {
 206                         printf("Could not set disable mdio@0x8B97000 %s\n",
 207                                fdt_strerror(ret));
 208                         return ret;
 209                 }
 210         }
 211
 212         return ret;
 213 }