1 // SPDX-License-Identifier: GPL-2.0+
3 * Copyright 2018-2020 NXP
9 #include <fdt_support.h>
21 #include <asm/arch/fsl_serdes.h>
22 #include <fsl-mc/fsl_mc.h>
23 #include <fsl-mc/ldpaa_wriop.h>
24 #include <linux/libfdt.h>
26 #include "../common/qixis.h"
28 DECLARE_GLOBAL_DATA_PTR;
31 #define EMI1 1 /* Mdio Bus 1 */
32 #define EMI2 2 /* Mdio Bus 2 */
34 #if defined(CONFIG_FSL_MC_ENET)
50 struct lx2160a_qds_mdio {
51 enum io_slot ioslot : 4;
53 struct mii_dev *realbus;
56 /* structure explaining the phy configuration on 8 lanes of a serdes*/
57 struct serdes_phy_config {
58 u8 serdes; /* serdes protocol */
61 /* -1 terminated array */
62 int phy_address[WRIOP_MAX_PHY_NUM + 1];
65 } phy_config[SRDS_MAX_LANES];
68 /* Table defining the phy configuration on 8 lanes of a serdes.
69 * Various assumptions have been made while defining this table.
70 * e.g. for serdes1 protocol 19 it is being assumed that X-M11-USXGMII
71 * card is being used for dpmac 3-4. (X-M12-XFI could also have been used)
72 * And also that this card is connected to IO Slot 1 (could have been connected
73 * to any of the 8 IO slots (IO slot 1 - IO slot 8)).
74 * similarly, it is also being assumed that MDIO 1 is selected on X-M7-40G card
75 * used in serdes1 protocol 19 (could have selected MDIO 2)
76 * To override these settings "dpmac" environment variable can be used after
77 * defining "dpmac_override" in hwconfig environment variable.
78 * This table has limited serdes protocol entries. It can be expanded as per
81 static const struct serdes_phy_config serdes1_phy_config[] = {
82 {3, {{WRIOP1_DPMAC3, {AQ_PHY_ADDR1, -1},
84 {WRIOP1_DPMAC4, {AQ_PHY_ADDR2, -1},
86 {WRIOP1_DPMAC5, {AQ_PHY_ADDR3, -1},
88 {WRIOP1_DPMAC6, {AQ_PHY_ADDR4, -1},
90 {7, {{WRIOP1_DPMAC3, {AQ_PHY_ADDR1, -1},
92 {WRIOP1_DPMAC4, {AQ_PHY_ADDR2, -1},
94 {WRIOP1_DPMAC5, {AQ_PHY_ADDR3, -1},
96 {WRIOP1_DPMAC6, {AQ_PHY_ADDR4, -1},
98 {WRIOP1_DPMAC7, {SGMII_CARD_PORT1_PHY_ADDR, -1},
100 {WRIOP1_DPMAC8, {SGMII_CARD_PORT2_PHY_ADDR, -1},
102 {WRIOP1_DPMAC9, {SGMII_CARD_PORT3_PHY_ADDR, -1},
104 {WRIOP1_DPMAC10, {SGMII_CARD_PORT4_PHY_ADDR, -1},
105 EMI1, IO_SLOT_2} } },
107 {13, {{WRIOP1_DPMAC1, {INPHI_PHY_ADDR1, INPHI_PHY_ADDR2, -1},
109 {WRIOP1_DPMAC2, {INPHI_PHY_ADDR1, INPHI_PHY_ADDR2, -1},
110 EMI1, IO_SLOT_2} } },
111 {14, {{WRIOP1_DPMAC1, {INPHI_PHY_ADDR1, INPHI_PHY_ADDR2, -1},
112 EMI1, IO_SLOT_1} } },
113 {15, {{WRIOP1_DPMAC1, {INPHI_PHY_ADDR1, INPHI_PHY_ADDR2, -1},
115 {WRIOP1_DPMAC2, {INPHI_PHY_ADDR1, INPHI_PHY_ADDR2, -1},
116 EMI1, IO_SLOT_1} } },
117 {17, {{WRIOP1_DPMAC3, {INPHI_PHY_ADDR1, INPHI_PHY_ADDR2, -1},
119 {WRIOP1_DPMAC4, {INPHI_PHY_ADDR1, INPHI_PHY_ADDR2, -1},
121 {WRIOP1_DPMAC5, {INPHI_PHY_ADDR1, INPHI_PHY_ADDR2, -1},
123 {WRIOP1_DPMAC6, {INPHI_PHY_ADDR1, INPHI_PHY_ADDR2, -1},
124 EMI1, IO_SLOT_1} } },
125 {19, {{WRIOP1_DPMAC2, {CORTINA_PHY_ADDR1, -1},
127 {WRIOP1_DPMAC3, {AQ_PHY_ADDR1, -1},
129 {WRIOP1_DPMAC4, {AQ_PHY_ADDR2, -1},
131 {WRIOP1_DPMAC5, {INPHI_PHY_ADDR1, INPHI_PHY_ADDR2, -1},
133 {WRIOP1_DPMAC6, {INPHI_PHY_ADDR1, INPHI_PHY_ADDR2, -1},
134 EMI1, IO_SLOT_6} } },
135 {20, {{WRIOP1_DPMAC1, {CORTINA_PHY_ADDR1, -1},
137 {WRIOP1_DPMAC2, {CORTINA_PHY_ADDR1, -1},
141 static const struct serdes_phy_config serdes2_phy_config[] = {
145 {11, {{WRIOP1_DPMAC12, {SGMII_CARD_PORT2_PHY_ADDR, -1},
147 {WRIOP1_DPMAC17, {SGMII_CARD_PORT3_PHY_ADDR, -1},
149 {WRIOP1_DPMAC18, {SGMII_CARD_PORT4_PHY_ADDR, -1},
151 {WRIOP1_DPMAC16, {SGMII_CARD_PORT2_PHY_ADDR, -1},
153 {WRIOP1_DPMAC13, {SGMII_CARD_PORT3_PHY_ADDR, -1},
155 {WRIOP1_DPMAC14, {SGMII_CARD_PORT4_PHY_ADDR, -1},
156 EMI1, IO_SLOT_8} } },
159 static const struct serdes_phy_config serdes3_phy_config[] = {
165 const struct phy_config *get_phy_config(u8 serdes,
166 const struct serdes_phy_config *table,
171 for (i = 0; i < table_size; i++) {
172 if (table[i].serdes == serdes)
173 return table[i].phy_config;
179 /* BRDCFG4 controls EMI routing for the board.
181 * 7-6 EMI Interface #1 Primary Routing (CFG_MUX1_EMI1) (1.8V):
182 * EMI1 00= On-board PHY #1
183 * 01= On-board PHY #2
185 * 11= Slots 1..8 multiplexer and translator.
186 * 5-3 EMI Interface #1 Secondary Routing (CFG_MUX2_EMI1) (2.5V):
195 * 2-0 EMI Interface #2 Routing (CFG_MUX_EMI2):
196 * EMI2 000= Slot #1 (secondary EMI)
197 * 001= Slot #2 (secondary EMI)
198 * 010= Slot #3 (secondary EMI)
199 * 011= Slot #4 (secondary EMI)
200 * 100= Slot #5 (secondary EMI)
201 * 101= Slot #6 (secondary EMI)
202 * 110= Slot #7 (secondary EMI)
203 * 111= Slot #8 (secondary EMI)
205 static int lx2160a_qds_get_mdio_mux_val(u8 realbusnum, enum io_slot ioslot)
207 switch (realbusnum) {
215 return (((ioslot - 1) << BRDCFG4_EMI1SEL_SHIFT) | 0xC0);
219 return ((ioslot - 1) << BRDCFG4_EMI2SEL_SHIFT);
225 static void lx2160a_qds_mux_mdio(struct lx2160a_qds_mdio *priv)
227 u8 brdcfg4, mux_val, reg;
229 brdcfg4 = QIXIS_READ(brdcfg[4]);
231 mux_val = lx2160a_qds_get_mdio_mux_val(priv->realbusnum, priv->ioslot);
233 switch (priv->realbusnum) {
235 brdcfg4 &= ~BRDCFG4_EMI1SEL_MASK;
239 brdcfg4 &= ~BRDCFG4_EMI2SEL_MASK;
245 QIXIS_WRITE(brdcfg[4], brdcfg4);
248 static int lx2160a_qds_mdio_read(struct mii_dev *bus, int addr,
249 int devad, int regnum)
251 struct lx2160a_qds_mdio *priv = bus->priv;
253 lx2160a_qds_mux_mdio(priv);
255 return priv->realbus->read(priv->realbus, addr, devad, regnum);
258 static int lx2160a_qds_mdio_write(struct mii_dev *bus, int addr, int devad,
259 int regnum, u16 value)
261 struct lx2160a_qds_mdio *priv = bus->priv;
263 lx2160a_qds_mux_mdio(priv);
265 return priv->realbus->write(priv->realbus, addr, devad, regnum, value);
268 static int lx2160a_qds_mdio_reset(struct mii_dev *bus)
270 struct lx2160a_qds_mdio *priv = bus->priv;
272 return priv->realbus->reset(priv->realbus);
275 static struct mii_dev *lx2160a_qds_mdio_init(u8 realbusnum, enum io_slot ioslot)
277 struct lx2160a_qds_mdio *pmdio;
279 /*should be within MDIO_NAME_LEN*/
280 char dummy_mdio_name[] = "LX2160A_QDS_MDIO1_IOSLOT1";
282 if (realbusnum == EMI2) {
283 if (ioslot < IO_SLOT_1 || ioslot > IO_SLOT_8) {
284 printf("invalid ioslot %d\n", ioslot);
287 } else if (realbusnum == EMI1) {
288 if (ioslot < IO_SLOT_1 || ioslot > EMI1_RGMII2) {
289 printf("invalid ioslot %d\n", ioslot);
293 printf("not supported real mdio bus %d\n", realbusnum);
297 if (ioslot == EMI1_RGMII1)
298 strcpy(dummy_mdio_name, "LX2160A_QDS_MDIO1_RGMII1");
299 else if (ioslot == EMI1_RGMII2)
300 strcpy(dummy_mdio_name, "LX2160A_QDS_MDIO1_RGMII2");
302 sprintf(dummy_mdio_name, "LX2160A_QDS_MDIO%d_IOSLOT%d",
304 bus = miiphy_get_dev_by_name(dummy_mdio_name);
311 printf("Failed to allocate %s bus\n", dummy_mdio_name);
315 pmdio = malloc(sizeof(*pmdio));
317 printf("Failed to allocate %s private data\n", dummy_mdio_name);
322 switch (realbusnum) {
325 miiphy_get_dev_by_name(DEFAULT_WRIOP_MDIO1_NAME);
329 miiphy_get_dev_by_name(DEFAULT_WRIOP_MDIO2_NAME);
333 if (!pmdio->realbus) {
334 printf("No real mdio bus num %d found\n", realbusnum);
340 pmdio->realbusnum = realbusnum;
341 pmdio->ioslot = ioslot;
342 bus->read = lx2160a_qds_mdio_read;
343 bus->write = lx2160a_qds_mdio_write;
344 bus->reset = lx2160a_qds_mdio_reset;
345 strcpy(bus->name, dummy_mdio_name);
348 if (!mdio_register(bus))
351 printf("No bus with name %s\n", dummy_mdio_name);
357 static inline void do_phy_config(const struct phy_config *phy_config)
360 int i, phy_num, phy_address;
362 for (i = 0; i < SRDS_MAX_LANES; i++) {
363 if (!phy_config[i].dpmacid)
367 phy_num < ARRAY_SIZE(phy_config[i].phy_address);
369 phy_address = phy_config[i].phy_address[phy_num];
370 if (phy_address == -1)
372 wriop_set_phy_address(phy_config[i].dpmacid,
373 phy_num, phy_address);
375 /*Register the muxing front-ends to the MDIO buses*/
376 bus = lx2160a_qds_mdio_init(phy_config[i].mdio_bus,
377 phy_config[i].ioslot);
379 printf("could not get bus for mdio %d ioslot %d\n",
380 phy_config[i].mdio_bus,
381 phy_config[i].ioslot);
383 wriop_set_mdio(phy_config[i].dpmacid, bus);
387 static inline void do_dpmac_config(int dpmac, const char *arg_dpmacid,
392 u8 realbusnum, ioslot;
395 char *phystr = "phy00";
397 /*search phy in dpmac arg*/
398 for (phy_num = 0; phy_num < WRIOP_MAX_PHY_NUM; phy_num++) {
399 sprintf(phystr, "phy%d", phy_num + 1);
400 ret = hwconfig_subarg_f(arg_dpmacid, phystr, &len, env_dpmac);
402 /*look for phy instead of phy1*/
404 ret = hwconfig_subarg_f(arg_dpmacid, "phy",
410 if (len != 4 || strncmp(ret, "0x", 2))
411 printf("invalid phy format in %s variable.\n"
412 "specify phy%d for %s in hex format e.g. 0x12\n",
413 env_dpmac, phy_num + 1, arg_dpmacid);
415 wriop_set_phy_address(dpmac, phy_num,
416 simple_strtoul(ret, NULL, 16));
419 /*search mdio in dpmac arg*/
420 ret = hwconfig_subarg_f(arg_dpmacid, "mdio", &len, env_dpmac);
422 realbusnum = *ret - '0';
424 realbusnum = EMI_NONE;
427 /*search io in dpmac arg*/
428 ret = hwconfig_subarg_f(arg_dpmacid, "io", &len, env_dpmac);
432 ioslot = IO_SLOT_NONE;
433 /*Register the muxing front-ends to the MDIO buses*/
434 bus = lx2160a_qds_mdio_init(realbusnum, ioslot);
436 printf("could not get bus for mdio %d ioslot %d\n",
439 wriop_set_mdio(dpmac, bus);
445 int board_eth_init(bd_t *bis)
447 #if defined(CONFIG_FSL_MC_ENET)
448 struct memac_mdio_info mdio_info;
449 struct memac_mdio_controller *regs;
453 char dpmacid[] = "dpmac00", srds[] = "00_00_00";
456 const struct phy_config *phy_config;
457 struct ccsr_gur *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR);
458 u32 srds_s1, srds_s2, srds_s3;
460 srds_s1 = in_le32(&gur->rcwsr[28]) &
461 FSL_CHASSIS3_RCWSR28_SRDS1_PRTCL_MASK;
462 srds_s1 >>= FSL_CHASSIS3_RCWSR28_SRDS1_PRTCL_SHIFT;
464 srds_s2 = in_le32(&gur->rcwsr[28]) &
465 FSL_CHASSIS3_RCWSR28_SRDS2_PRTCL_MASK;
466 srds_s2 >>= FSL_CHASSIS3_RCWSR28_SRDS2_PRTCL_SHIFT;
468 srds_s3 = in_le32(&gur->rcwsr[28]) &
469 FSL_CHASSIS3_RCWSR28_SRDS3_PRTCL_MASK;
470 srds_s3 >>= FSL_CHASSIS3_RCWSR28_SRDS3_PRTCL_SHIFT;
472 sprintf(srds, "%d_%d_%d", srds_s1, srds_s2, srds_s3);
474 regs = (struct memac_mdio_controller *)CONFIG_SYS_FSL_WRIOP1_MDIO1;
475 mdio_info.regs = regs;
476 mdio_info.name = DEFAULT_WRIOP_MDIO1_NAME;
478 /*Register the EMI 1*/
479 fm_memac_mdio_init(bis, &mdio_info);
481 regs = (struct memac_mdio_controller *)CONFIG_SYS_FSL_WRIOP1_MDIO2;
482 mdio_info.regs = regs;
483 mdio_info.name = DEFAULT_WRIOP_MDIO2_NAME;
485 /*Register the EMI 2*/
486 fm_memac_mdio_init(bis, &mdio_info);
488 /* "dpmac" environment variable can be used after
489 * defining "dpmac_override" in hwconfig environment variable.
491 if (hwconfig("dpmac_override")) {
492 env_dpmac = env_get("dpmac");
494 ret = hwconfig_arg_f("srds", &len, env_dpmac);
496 if (strncmp(ret, srds, strlen(srds))) {
497 printf("SERDES configuration changed.\n"
498 "previous: %.*s, current: %s.\n"
499 "update dpmac variable.\n",
500 (int)len, ret, srds);
503 printf("SERDES configuration not found.\n"
504 "Please add srds:%s in dpmac variable\n",
508 for (i = WRIOP1_DPMAC1; i < NUM_WRIOP_PORTS; i++) {
509 /* Look for dpmac1 to dpmac24(current max) arg
510 * in dpmac environment variable
512 sprintf(dpmacid, "dpmac%d", i);
513 ret = hwconfig_arg_f(dpmacid, &len, env_dpmac);
515 do_dpmac_config(i, dpmacid, env_dpmac);
518 printf("Warning: environment dpmac not found.\n"
519 "DPAA network interfaces may not work\n");
522 /*Look for phy config for serdes1 in phy config table*/
523 phy_config = get_phy_config(srds_s1, serdes1_phy_config,
524 ARRAY_SIZE(serdes1_phy_config));
526 printf("%s WRIOP: Unsupported SerDes1 Protocol %d\n",
529 do_phy_config(phy_config);
531 phy_config = get_phy_config(srds_s2, serdes2_phy_config,
532 ARRAY_SIZE(serdes2_phy_config));
534 printf("%s WRIOP: Unsupported SerDes2 Protocol %d\n",
537 do_phy_config(phy_config);
539 phy_config = get_phy_config(srds_s3, serdes3_phy_config,
540 ARRAY_SIZE(serdes3_phy_config));
542 printf("%s WRIOP: Unsupported SerDes3 Protocol %d\n",
545 do_phy_config(phy_config);
549 if (wriop_get_enet_if(WRIOP1_DPMAC17) == PHY_INTERFACE_MODE_RGMII_ID) {
550 wriop_set_phy_address(WRIOP1_DPMAC17, 0, RGMII_PHY_ADDR1);
551 bus = lx2160a_qds_mdio_init(EMI1, EMI1_RGMII1);
553 printf("could not get bus for RGMII1\n");
555 wriop_set_mdio(WRIOP1_DPMAC17, bus);
558 if (wriop_get_enet_if(WRIOP1_DPMAC18) == PHY_INTERFACE_MODE_RGMII_ID) {
559 wriop_set_phy_address(WRIOP1_DPMAC18, 0, RGMII_PHY_ADDR2);
560 bus = lx2160a_qds_mdio_init(EMI1, EMI1_RGMII2);
562 printf("could not get bus for RGMII2\n");
564 wriop_set_mdio(WRIOP1_DPMAC18, bus);
568 #endif /* CONFIG_FMAN_ENET */
570 #ifdef CONFIG_PHY_AQUANTIA
572 * Export functions to be used by AQ firmware
575 gd->jt->strcpy = strcpy;
576 gd->jt->mdelay = mdelay;
577 gd->jt->mdio_get_current_dev = mdio_get_current_dev;
578 gd->jt->phy_find_by_mask = phy_find_by_mask;
579 gd->jt->mdio_phydev_for_ethname = mdio_phydev_for_ethname;
580 gd->jt->miiphy_set_current_dev = miiphy_set_current_dev;
582 return pci_eth_init(bis);
585 #if defined(CONFIG_RESET_PHY_R)
588 #if defined(CONFIG_FSL_MC_ENET)
592 #endif /* CONFIG_RESET_PHY_R */
594 #if defined(CONFIG_FSL_MC_ENET)
595 int fdt_fixup_dpmac_phy_handle(void *fdt, int dpmac_id, int node_phandle)
599 char dpmac_str[] = "dpmacs@00";
600 const char *phy_string;
602 offset = fdt_path_offset(fdt, "/soc/fsl-mc/dpmacs");
605 offset = fdt_path_offset(fdt, "/fsl-mc/dpmacs");
608 printf("dpmacs node not found in device tree\n");
612 sprintf(dpmac_str, "dpmac@%x", dpmac_id);
613 debug("dpmac_str = %s\n", dpmac_str);
615 offset = fdt_subnode_offset(fdt, offset, dpmac_str);
617 printf("%s node not found in device tree\n", dpmac_str);
621 phy_string = fdt_getprop(fdt, offset, "phy-connection-type", NULL);
622 if (is_backplane_mode(phy_string)) {
623 /* Backplane KR mode: skip fixups */
624 printf("Interface %d in backplane KR mode\n", dpmac_id);
628 ret = fdt_appendprop_cell(fdt, offset, "phy-handle", node_phandle);
630 printf("%d@%s %d\n", __LINE__, __func__, ret);
632 phy_string = phy_string_for_interface(wriop_get_enet_if(dpmac_id));
633 ret = fdt_setprop_string(fdt, offset, "phy-connection-type",
636 printf("%d@%s %d\n", __LINE__, __func__, ret);
641 int fdt_get_ioslot_offset(void *fdt, struct mii_dev *mii_dev, int fpga_offset)
643 char mdio_ioslot_str[] = "mdio@00";
644 struct lx2160a_qds_mdio *priv;
649 /*Test if the MDIO bus is real mdio bus or muxing front end ?*/
650 if (strncmp(mii_dev->name, "LX2160A_QDS_MDIO",
651 strlen("LX2160A_QDS_MDIO")))
654 /*Get the real MDIO bus num and ioslot info from bus's priv data*/
655 priv = mii_dev->priv;
657 debug("real_bus_num = %d, ioslot = %d\n",
658 priv->realbusnum, priv->ioslot);
660 if (priv->realbusnum == EMI1)
661 reg = CONFIG_SYS_FSL_WRIOP1_MDIO1;
663 reg = CONFIG_SYS_FSL_WRIOP1_MDIO2;
665 offset = fdt_node_offset_by_compat_reg(fdt, "fsl,fman-memac-mdio", reg);
667 printf("mdio@%llx node not found in device tree\n", reg);
671 phandle = fdt_get_phandle(fdt, offset);
672 phandle = cpu_to_fdt32(phandle);
673 offset = fdt_node_offset_by_prop_value(fdt, -1, "mdio-parent-bus",
676 printf("mdio-mux-%d node not found in device tree\n",
677 priv->realbusnum == EMI1 ? 1 : 2);
681 mux_val = lx2160a_qds_get_mdio_mux_val(priv->realbusnum, priv->ioslot);
682 if (priv->realbusnum == EMI1)
683 mux_val >>= BRDCFG4_EMI1SEL_SHIFT;
685 mux_val >>= BRDCFG4_EMI2SEL_SHIFT;
686 sprintf(mdio_ioslot_str, "mdio@%x", (u8)mux_val);
688 offset = fdt_subnode_offset(fdt, offset, mdio_ioslot_str);
690 printf("%s node not found in device tree\n", mdio_ioslot_str);
697 int fdt_create_phy_node(void *fdt, int offset, u8 phyaddr, int *subnodeoffset,
698 struct phy_device *phy_dev, int phandle)
700 char phy_node_name[] = "ethernet-phy@00";
701 char phy_id_compatible_str[] = "ethernet-phy-id0000.0000,";
704 sprintf(phy_node_name, "ethernet-phy@%x", phyaddr);
705 debug("phy_node_name = %s\n", phy_node_name);
707 *subnodeoffset = fdt_add_subnode(fdt, offset, phy_node_name);
708 if (*subnodeoffset <= 0) {
709 printf("Could not add subnode %s inside node %s err = %s\n",
710 phy_node_name, fdt_get_name(fdt, offset, NULL),
711 fdt_strerror(*subnodeoffset));
712 return *subnodeoffset;
715 sprintf(phy_id_compatible_str, "ethernet-phy-id%04x.%04x,",
716 phy_dev->phy_id >> 16, phy_dev->phy_id & 0xFFFF);
717 debug("phy_id_compatible_str %s\n", phy_id_compatible_str);
719 ret = fdt_setprop_string(fdt, *subnodeoffset, "compatible",
720 phy_id_compatible_str);
722 printf("%d@%s %d\n", __LINE__, __func__, ret);
726 if (phy_dev->is_c45) {
727 ret = fdt_appendprop_string(fdt, *subnodeoffset, "compatible",
728 "ethernet-phy-ieee802.3-c45");
730 printf("%d@%s %d\n", __LINE__, __func__, ret);
734 ret = fdt_appendprop_string(fdt, *subnodeoffset, "compatible",
735 "ethernet-phy-ieee802.3-c22");
737 printf("%d@%s %d\n", __LINE__, __func__, ret);
742 ret = fdt_setprop_cell(fdt, *subnodeoffset, "reg", phyaddr);
744 printf("%d@%s %d\n", __LINE__, __func__, ret);
748 ret = fdt_set_phandle(fdt, *subnodeoffset, phandle);
750 printf("%d@%s %d\n", __LINE__, __func__, ret);
756 fdt_del_node(fdt, *subnodeoffset);
761 int fdt_fixup_board_phy(void *fdt)
763 int fpga_offset, offset, subnodeoffset;
764 struct mii_dev *mii_dev;
765 struct list_head *mii_devs, *entry;
766 int ret, dpmac_id, phandle, i;
767 struct phy_device *phy_dev;
768 char ethname[ETH_NAME_LEN];
769 phy_interface_t phy_iface;
772 /* we know FPGA is connected to i2c0, therefore search path directly,
773 * instead of compatible property, as it saves time
775 fpga_offset = fdt_path_offset(fdt, "/soc/i2c@2000000/fpga");
778 fpga_offset = fdt_path_offset(fdt, "/i2c@2000000/fpga");
780 if (fpga_offset < 0) {
781 printf("i2c@2000000/fpga node not found in device tree\n");
785 phandle = fdt_alloc_phandle(fdt);
786 mii_devs = mdio_get_list_head();
788 list_for_each(entry, mii_devs) {
789 mii_dev = list_entry(entry, struct mii_dev, link);
790 debug("mii_dev name : %s\n", mii_dev->name);
791 offset = fdt_get_ioslot_offset(fdt, mii_dev, fpga_offset);
795 // Look for phy devices attached to MDIO bus muxing front end
796 // and create their entries with compatible being the device id
797 for (i = 0; i < PHY_MAX_ADDR; i++) {
798 phy_dev = mii_dev->phymap[i];
802 // TODO: use sscanf instead of loop
803 dpmac_id = WRIOP1_DPMAC1;
804 while (dpmac_id < NUM_WRIOP_PORTS) {
805 phy_iface = wriop_get_enet_if(dpmac_id);
806 snprintf(ethname, ETH_NAME_LEN, "DPMAC%d@%s",
808 phy_string_for_interface(phy_iface));
809 if (strcmp(ethname, phy_dev->dev->name) == 0)
813 if (dpmac_id == NUM_WRIOP_PORTS)
815 ret = fdt_create_phy_node(fdt, offset, i,
821 ret = fdt_fixup_dpmac_phy_handle(fdt,
824 fdt_del_node(fdt, subnodeoffset);
827 /* calculate offset again as new node addition may have
830 offset = fdt_get_ioslot_offset(fdt, mii_dev,
841 #endif // CONFIG_FSL_MC_ENET