1 // SPDX-License-Identifier: GPL-2.0+
3 * Copyright 2018-2020 NXP
9 #include <fdt_support.h>
20 #include <asm/global_data.h>
23 #include <asm/arch/fsl_serdes.h>
24 #include <fsl-mc/fsl_mc.h>
25 #include <fsl-mc/ldpaa_wriop.h>
26 #include <linux/libfdt.h>
28 #include "../common/qixis.h"
30 DECLARE_GLOBAL_DATA_PTR;
34 #define EMI1 1 /* Mdio Bus 1 */
35 #define EMI2 2 /* Mdio Bus 2 */
37 #if defined(CONFIG_FSL_MC_ENET)
53 struct lx2160a_qds_mdio {
54 enum io_slot ioslot : 4;
56 struct mii_dev *realbus;
59 /* structure explaining the phy configuration on 8 lanes of a serdes*/
60 struct serdes_phy_config {
61 u8 serdes; /* serdes protocol */
64 /* -1 terminated array */
65 int phy_address[WRIOP_MAX_PHY_NUM + 1];
68 } phy_config[SRDS_MAX_LANES];
71 /* Table defining the phy configuration on 8 lanes of a serdes.
72 * Various assumptions have been made while defining this table.
73 * e.g. for serdes1 protocol 19 it is being assumed that X-M11-USXGMII
74 * card is being used for dpmac 3-4. (X-M12-XFI could also have been used)
75 * And also that this card is connected to IO Slot 1 (could have been connected
76 * to any of the 8 IO slots (IO slot 1 - IO slot 8)).
77 * similarly, it is also being assumed that MDIO 1 is selected on X-M7-40G card
78 * used in serdes1 protocol 19 (could have selected MDIO 2)
79 * To override these settings "dpmac" environment variable can be used after
80 * defining "dpmac_override" in hwconfig environment variable.
81 * This table has limited serdes protocol entries. It can be expanded as per
84 static const struct serdes_phy_config serdes1_phy_config[] = {
85 {3, {{WRIOP1_DPMAC3, {AQ_PHY_ADDR1, -1},
87 {WRIOP1_DPMAC4, {AQ_PHY_ADDR2, -1},
89 {WRIOP1_DPMAC5, {AQ_PHY_ADDR3, -1},
91 {WRIOP1_DPMAC6, {AQ_PHY_ADDR4, -1},
93 {7, {{WRIOP1_DPMAC3, {AQ_PHY_ADDR1, -1},
95 {WRIOP1_DPMAC4, {AQ_PHY_ADDR2, -1},
97 {WRIOP1_DPMAC5, {AQ_PHY_ADDR3, -1},
99 {WRIOP1_DPMAC6, {AQ_PHY_ADDR4, -1},
101 {WRIOP1_DPMAC7, {SGMII_CARD_PORT1_PHY_ADDR, -1},
103 {WRIOP1_DPMAC8, {SGMII_CARD_PORT2_PHY_ADDR, -1},
105 {WRIOP1_DPMAC9, {SGMII_CARD_PORT3_PHY_ADDR, -1},
107 {WRIOP1_DPMAC10, {SGMII_CARD_PORT4_PHY_ADDR, -1},
108 EMI1, IO_SLOT_2} } },
110 {13, {{WRIOP1_DPMAC1, {INPHI_PHY_ADDR1, INPHI_PHY_ADDR2, -1},
112 {WRIOP1_DPMAC2, {INPHI_PHY_ADDR1, INPHI_PHY_ADDR2, -1},
113 EMI1, IO_SLOT_2} } },
114 {14, {{WRIOP1_DPMAC1, {INPHI_PHY_ADDR1, INPHI_PHY_ADDR2, -1},
115 EMI1, IO_SLOT_1} } },
116 {15, {{WRIOP1_DPMAC1, {INPHI_PHY_ADDR1, INPHI_PHY_ADDR2, -1},
118 {WRIOP1_DPMAC2, {INPHI_PHY_ADDR1, INPHI_PHY_ADDR2, -1},
119 EMI1, IO_SLOT_1} } },
120 {17, {{WRIOP1_DPMAC3, {INPHI_PHY_ADDR1, INPHI_PHY_ADDR2, -1},
122 {WRIOP1_DPMAC4, {INPHI_PHY_ADDR1, INPHI_PHY_ADDR2, -1},
124 {WRIOP1_DPMAC5, {INPHI_PHY_ADDR1, INPHI_PHY_ADDR2, -1},
126 {WRIOP1_DPMAC6, {INPHI_PHY_ADDR1, INPHI_PHY_ADDR2, -1},
127 EMI1, IO_SLOT_1} } },
128 {19, {{WRIOP1_DPMAC2, {CORTINA_PHY_ADDR1, -1},
130 {WRIOP1_DPMAC3, {AQ_PHY_ADDR1, -1},
132 {WRIOP1_DPMAC4, {AQ_PHY_ADDR2, -1},
134 {WRIOP1_DPMAC5, {INPHI_PHY_ADDR1, INPHI_PHY_ADDR2, -1},
136 {WRIOP1_DPMAC6, {INPHI_PHY_ADDR1, INPHI_PHY_ADDR2, -1},
137 EMI1, IO_SLOT_6} } },
138 {20, {{WRIOP1_DPMAC1, {CORTINA_PHY_ADDR1, -1},
140 {WRIOP1_DPMAC2, {CORTINA_PHY_ADDR1, -1},
144 static const struct serdes_phy_config serdes2_phy_config[] = {
148 {11, {{WRIOP1_DPMAC12, {SGMII_CARD_PORT2_PHY_ADDR, -1},
150 {WRIOP1_DPMAC17, {SGMII_CARD_PORT3_PHY_ADDR, -1},
152 {WRIOP1_DPMAC18, {SGMII_CARD_PORT4_PHY_ADDR, -1},
154 {WRIOP1_DPMAC16, {SGMII_CARD_PORT2_PHY_ADDR, -1},
156 {WRIOP1_DPMAC13, {SGMII_CARD_PORT3_PHY_ADDR, -1},
158 {WRIOP1_DPMAC14, {SGMII_CARD_PORT4_PHY_ADDR, -1},
159 EMI1, IO_SLOT_8} } },
162 static const struct serdes_phy_config serdes3_phy_config[] = {
168 const struct phy_config *get_phy_config(u8 serdes,
169 const struct serdes_phy_config *table,
174 for (i = 0; i < table_size; i++) {
175 if (table[i].serdes == serdes)
176 return table[i].phy_config;
182 /* BRDCFG4 controls EMI routing for the board.
184 * 7-6 EMI Interface #1 Primary Routing (CFG_MUX1_EMI1) (1.8V):
185 * EMI1 00= On-board PHY #1
186 * 01= On-board PHY #2
188 * 11= Slots 1..8 multiplexer and translator.
189 * 5-3 EMI Interface #1 Secondary Routing (CFG_MUX2_EMI1) (2.5V):
198 * 2-0 EMI Interface #2 Routing (CFG_MUX_EMI2):
199 * EMI2 000= Slot #1 (secondary EMI)
200 * 001= Slot #2 (secondary EMI)
201 * 010= Slot #3 (secondary EMI)
202 * 011= Slot #4 (secondary EMI)
203 * 100= Slot #5 (secondary EMI)
204 * 101= Slot #6 (secondary EMI)
205 * 110= Slot #7 (secondary EMI)
206 * 111= Slot #8 (secondary EMI)
208 static int lx2160a_qds_get_mdio_mux_val(u8 realbusnum, enum io_slot ioslot)
210 switch (realbusnum) {
218 return (((ioslot - 1) << BRDCFG4_EMI1SEL_SHIFT) | 0xC0);
222 return ((ioslot - 1) << BRDCFG4_EMI2SEL_SHIFT);
228 static void lx2160a_qds_mux_mdio(struct lx2160a_qds_mdio *priv)
230 u8 brdcfg4, mux_val, reg;
232 brdcfg4 = QIXIS_READ(brdcfg[4]);
234 mux_val = lx2160a_qds_get_mdio_mux_val(priv->realbusnum, priv->ioslot);
236 switch (priv->realbusnum) {
238 brdcfg4 &= ~BRDCFG4_EMI1SEL_MASK;
242 brdcfg4 &= ~BRDCFG4_EMI2SEL_MASK;
248 QIXIS_WRITE(brdcfg[4], brdcfg4);
251 static int lx2160a_qds_mdio_read(struct mii_dev *bus, int addr,
252 int devad, int regnum)
254 struct lx2160a_qds_mdio *priv = bus->priv;
256 lx2160a_qds_mux_mdio(priv);
258 return priv->realbus->read(priv->realbus, addr, devad, regnum);
261 static int lx2160a_qds_mdio_write(struct mii_dev *bus, int addr, int devad,
262 int regnum, u16 value)
264 struct lx2160a_qds_mdio *priv = bus->priv;
266 lx2160a_qds_mux_mdio(priv);
268 return priv->realbus->write(priv->realbus, addr, devad, regnum, value);
271 static int lx2160a_qds_mdio_reset(struct mii_dev *bus)
273 struct lx2160a_qds_mdio *priv = bus->priv;
275 return priv->realbus->reset(priv->realbus);
278 static struct mii_dev *lx2160a_qds_mdio_init(u8 realbusnum, enum io_slot ioslot)
280 struct lx2160a_qds_mdio *pmdio;
282 /*should be within MDIO_NAME_LEN*/
283 char dummy_mdio_name[] = "LX2160A_QDS_MDIO1_IOSLOT1";
285 if (realbusnum == EMI2) {
286 if (ioslot < IO_SLOT_1 || ioslot > IO_SLOT_8) {
287 printf("invalid ioslot %d\n", ioslot);
290 } else if (realbusnum == EMI1) {
291 if (ioslot < IO_SLOT_1 || ioslot > EMI1_RGMII2) {
292 printf("invalid ioslot %d\n", ioslot);
296 printf("not supported real mdio bus %d\n", realbusnum);
300 if (ioslot == EMI1_RGMII1)
301 strcpy(dummy_mdio_name, "LX2160A_QDS_MDIO1_RGMII1");
302 else if (ioslot == EMI1_RGMII2)
303 strcpy(dummy_mdio_name, "LX2160A_QDS_MDIO1_RGMII2");
305 sprintf(dummy_mdio_name, "LX2160A_QDS_MDIO%d_IOSLOT%d",
307 bus = miiphy_get_dev_by_name(dummy_mdio_name);
314 printf("Failed to allocate %s bus\n", dummy_mdio_name);
318 pmdio = malloc(sizeof(*pmdio));
320 printf("Failed to allocate %s private data\n", dummy_mdio_name);
325 switch (realbusnum) {
328 miiphy_get_dev_by_name(DEFAULT_WRIOP_MDIO1_NAME);
332 miiphy_get_dev_by_name(DEFAULT_WRIOP_MDIO2_NAME);
336 if (!pmdio->realbus) {
337 printf("No real mdio bus num %d found\n", realbusnum);
343 pmdio->realbusnum = realbusnum;
344 pmdio->ioslot = ioslot;
345 bus->read = lx2160a_qds_mdio_read;
346 bus->write = lx2160a_qds_mdio_write;
347 bus->reset = lx2160a_qds_mdio_reset;
348 strcpy(bus->name, dummy_mdio_name);
351 if (!mdio_register(bus))
354 printf("No bus with name %s\n", dummy_mdio_name);
360 static inline void do_phy_config(const struct phy_config *phy_config)
363 int i, phy_num, phy_address;
365 for (i = 0; i < SRDS_MAX_LANES; i++) {
366 if (!phy_config[i].dpmacid)
370 phy_num < ARRAY_SIZE(phy_config[i].phy_address);
372 phy_address = phy_config[i].phy_address[phy_num];
373 if (phy_address == -1)
375 wriop_set_phy_address(phy_config[i].dpmacid,
376 phy_num, phy_address);
378 /*Register the muxing front-ends to the MDIO buses*/
379 bus = lx2160a_qds_mdio_init(phy_config[i].mdio_bus,
380 phy_config[i].ioslot);
382 printf("could not get bus for mdio %d ioslot %d\n",
383 phy_config[i].mdio_bus,
384 phy_config[i].ioslot);
386 wriop_set_mdio(phy_config[i].dpmacid, bus);
390 static inline void do_dpmac_config(int dpmac, const char *arg_dpmacid,
395 u8 realbusnum, ioslot;
398 char *phystr = "phy00";
400 /*search phy in dpmac arg*/
401 for (phy_num = 0; phy_num < WRIOP_MAX_PHY_NUM; phy_num++) {
402 sprintf(phystr, "phy%d", phy_num + 1);
403 ret = hwconfig_subarg_f(arg_dpmacid, phystr, &len, env_dpmac);
405 /*look for phy instead of phy1*/
407 ret = hwconfig_subarg_f(arg_dpmacid, "phy",
413 if (len != 4 || strncmp(ret, "0x", 2))
414 printf("invalid phy format in %s variable.\n"
415 "specify phy%d for %s in hex format e.g. 0x12\n",
416 env_dpmac, phy_num + 1, arg_dpmacid);
418 wriop_set_phy_address(dpmac, phy_num,
422 /*search mdio in dpmac arg*/
423 ret = hwconfig_subarg_f(arg_dpmacid, "mdio", &len, env_dpmac);
425 realbusnum = *ret - '0';
427 realbusnum = EMI_NONE;
430 /*search io in dpmac arg*/
431 ret = hwconfig_subarg_f(arg_dpmacid, "io", &len, env_dpmac);
435 ioslot = IO_SLOT_NONE;
436 /*Register the muxing front-ends to the MDIO buses*/
437 bus = lx2160a_qds_mdio_init(realbusnum, ioslot);
439 printf("could not get bus for mdio %d ioslot %d\n",
442 wriop_set_mdio(dpmac, bus);
447 #endif /* !CONFIG_DM_ETH */
449 int board_eth_init(struct bd_info *bis)
451 #ifndef CONFIG_DM_ETH
452 #if defined(CONFIG_FSL_MC_ENET)
453 struct memac_mdio_info mdio_info;
454 struct memac_mdio_controller *regs;
458 char dpmacid[] = "dpmac00", srds[] = "00_00_00";
461 const struct phy_config *phy_config;
462 struct ccsr_gur *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR);
463 u32 srds_s1, srds_s2, srds_s3;
465 srds_s1 = in_le32(&gur->rcwsr[28]) &
466 FSL_CHASSIS3_RCWSR28_SRDS1_PRTCL_MASK;
467 srds_s1 >>= FSL_CHASSIS3_RCWSR28_SRDS1_PRTCL_SHIFT;
469 srds_s2 = in_le32(&gur->rcwsr[28]) &
470 FSL_CHASSIS3_RCWSR28_SRDS2_PRTCL_MASK;
471 srds_s2 >>= FSL_CHASSIS3_RCWSR28_SRDS2_PRTCL_SHIFT;
473 srds_s3 = in_le32(&gur->rcwsr[28]) &
474 FSL_CHASSIS3_RCWSR28_SRDS3_PRTCL_MASK;
475 srds_s3 >>= FSL_CHASSIS3_RCWSR28_SRDS3_PRTCL_SHIFT;
477 sprintf(srds, "%d_%d_%d", srds_s1, srds_s2, srds_s3);
479 regs = (struct memac_mdio_controller *)CONFIG_SYS_FSL_WRIOP1_MDIO1;
480 mdio_info.regs = regs;
481 mdio_info.name = DEFAULT_WRIOP_MDIO1_NAME;
483 /*Register the EMI 1*/
484 fm_memac_mdio_init(bis, &mdio_info);
486 regs = (struct memac_mdio_controller *)CONFIG_SYS_FSL_WRIOP1_MDIO2;
487 mdio_info.regs = regs;
488 mdio_info.name = DEFAULT_WRIOP_MDIO2_NAME;
490 /*Register the EMI 2*/
491 fm_memac_mdio_init(bis, &mdio_info);
493 /* "dpmac" environment variable can be used after
494 * defining "dpmac_override" in hwconfig environment variable.
496 if (hwconfig("dpmac_override")) {
497 env_dpmac = env_get("dpmac");
499 ret = hwconfig_arg_f("srds", &len, env_dpmac);
501 if (strncmp(ret, srds, strlen(srds))) {
502 printf("SERDES configuration changed.\n"
503 "previous: %.*s, current: %s.\n"
504 "update dpmac variable.\n",
505 (int)len, ret, srds);
508 printf("SERDES configuration not found.\n"
509 "Please add srds:%s in dpmac variable\n",
513 for (i = WRIOP1_DPMAC1; i < NUM_WRIOP_PORTS; i++) {
514 /* Look for dpmac1 to dpmac24(current max) arg
515 * in dpmac environment variable
517 sprintf(dpmacid, "dpmac%d", i);
518 ret = hwconfig_arg_f(dpmacid, &len, env_dpmac);
520 do_dpmac_config(i, dpmacid, env_dpmac);
523 printf("Warning: environment dpmac not found.\n"
524 "DPAA network interfaces may not work\n");
527 /*Look for phy config for serdes1 in phy config table*/
528 phy_config = get_phy_config(srds_s1, serdes1_phy_config,
529 ARRAY_SIZE(serdes1_phy_config));
531 printf("%s WRIOP: Unsupported SerDes1 Protocol %d\n",
534 do_phy_config(phy_config);
536 phy_config = get_phy_config(srds_s2, serdes2_phy_config,
537 ARRAY_SIZE(serdes2_phy_config));
539 printf("%s WRIOP: Unsupported SerDes2 Protocol %d\n",
542 do_phy_config(phy_config);
544 phy_config = get_phy_config(srds_s3, serdes3_phy_config,
545 ARRAY_SIZE(serdes3_phy_config));
547 printf("%s WRIOP: Unsupported SerDes3 Protocol %d\n",
550 do_phy_config(phy_config);
554 if (wriop_get_enet_if(WRIOP1_DPMAC17) == PHY_INTERFACE_MODE_RGMII_ID) {
555 wriop_set_phy_address(WRIOP1_DPMAC17, 0, RGMII_PHY_ADDR1);
556 bus = lx2160a_qds_mdio_init(EMI1, EMI1_RGMII1);
558 printf("could not get bus for RGMII1\n");
560 wriop_set_mdio(WRIOP1_DPMAC17, bus);
563 if (wriop_get_enet_if(WRIOP1_DPMAC18) == PHY_INTERFACE_MODE_RGMII_ID) {
564 wriop_set_phy_address(WRIOP1_DPMAC18, 0, RGMII_PHY_ADDR2);
565 bus = lx2160a_qds_mdio_init(EMI1, EMI1_RGMII2);
567 printf("could not get bus for RGMII2\n");
569 wriop_set_mdio(WRIOP1_DPMAC18, bus);
573 #endif /* CONFIG_FMAN_ENET */
574 #endif /* !CONFIG_DM_ETH */
576 #ifdef CONFIG_PHY_AQUANTIA
578 * Export functions to be used by AQ firmware
581 gd->jt->strcpy = strcpy;
582 gd->jt->mdelay = mdelay;
583 gd->jt->mdio_get_current_dev = mdio_get_current_dev;
584 gd->jt->phy_find_by_mask = phy_find_by_mask;
585 gd->jt->mdio_phydev_for_ethname = mdio_phydev_for_ethname;
586 gd->jt->miiphy_set_current_dev = miiphy_set_current_dev;
592 return pci_eth_init(bis);
596 #if defined(CONFIG_RESET_PHY_R)
599 #if defined(CONFIG_FSL_MC_ENET)
603 #endif /* CONFIG_RESET_PHY_R */
605 #ifndef CONFIG_DM_ETH
606 #if defined(CONFIG_FSL_MC_ENET)
607 int fdt_fixup_dpmac_phy_handle(void *fdt, int dpmac_id, int node_phandle)
611 char dpmac_str[] = "dpmacs@00";
612 const char *phy_string;
614 offset = fdt_path_offset(fdt, "/soc/fsl-mc/dpmacs");
617 offset = fdt_path_offset(fdt, "/fsl-mc/dpmacs");
620 printf("dpmacs node not found in device tree\n");
624 sprintf(dpmac_str, "dpmac@%x", dpmac_id);
625 debug("dpmac_str = %s\n", dpmac_str);
627 offset = fdt_subnode_offset(fdt, offset, dpmac_str);
629 printf("%s node not found in device tree\n", dpmac_str);
633 phy_string = fdt_getprop(fdt, offset, "phy-connection-type", NULL);
634 if (is_backplane_mode(phy_string)) {
635 /* Backplane KR mode: skip fixups */
636 printf("Interface %d in backplane KR mode\n", dpmac_id);
640 ret = fdt_appendprop_cell(fdt, offset, "phy-handle", node_phandle);
642 printf("%d@%s %d\n", __LINE__, __func__, ret);
644 phy_string = phy_string_for_interface(wriop_get_enet_if(dpmac_id));
645 ret = fdt_setprop_string(fdt, offset, "phy-connection-type",
648 printf("%d@%s %d\n", __LINE__, __func__, ret);
653 int fdt_get_ioslot_offset(void *fdt, struct mii_dev *mii_dev, int fpga_offset)
655 char mdio_ioslot_str[] = "mdio@00";
656 struct lx2160a_qds_mdio *priv;
661 /*Test if the MDIO bus is real mdio bus or muxing front end ?*/
662 if (strncmp(mii_dev->name, "LX2160A_QDS_MDIO",
663 strlen("LX2160A_QDS_MDIO")))
666 /*Get the real MDIO bus num and ioslot info from bus's priv data*/
667 priv = mii_dev->priv;
669 debug("real_bus_num = %d, ioslot = %d\n",
670 priv->realbusnum, priv->ioslot);
672 if (priv->realbusnum == EMI1)
673 reg = CONFIG_SYS_FSL_WRIOP1_MDIO1;
675 reg = CONFIG_SYS_FSL_WRIOP1_MDIO2;
677 offset = fdt_node_offset_by_compat_reg(fdt, "fsl,fman-memac-mdio", reg);
679 printf("mdio@%llx node not found in device tree\n", reg);
683 phandle = fdt_get_phandle(fdt, offset);
684 phandle = cpu_to_fdt32(phandle);
685 offset = fdt_node_offset_by_prop_value(fdt, -1, "mdio-parent-bus",
688 printf("mdio-mux-%d node not found in device tree\n",
689 priv->realbusnum == EMI1 ? 1 : 2);
693 mux_val = lx2160a_qds_get_mdio_mux_val(priv->realbusnum, priv->ioslot);
694 if (priv->realbusnum == EMI1)
695 mux_val >>= BRDCFG4_EMI1SEL_SHIFT;
697 mux_val >>= BRDCFG4_EMI2SEL_SHIFT;
698 sprintf(mdio_ioslot_str, "mdio@%x", (u8)mux_val);
700 offset = fdt_subnode_offset(fdt, offset, mdio_ioslot_str);
702 printf("%s node not found in device tree\n", mdio_ioslot_str);
709 int fdt_create_phy_node(void *fdt, int offset, u8 phyaddr, int *subnodeoffset,
710 struct phy_device *phy_dev, int phandle)
712 char phy_node_name[] = "ethernet-phy@00";
713 char phy_id_compatible_str[] = "ethernet-phy-id0000.0000,";
716 sprintf(phy_node_name, "ethernet-phy@%x", phyaddr);
717 debug("phy_node_name = %s\n", phy_node_name);
719 *subnodeoffset = fdt_add_subnode(fdt, offset, phy_node_name);
720 if (*subnodeoffset <= 0) {
721 printf("Could not add subnode %s inside node %s err = %s\n",
722 phy_node_name, fdt_get_name(fdt, offset, NULL),
723 fdt_strerror(*subnodeoffset));
724 return *subnodeoffset;
727 sprintf(phy_id_compatible_str, "ethernet-phy-id%04x.%04x,",
728 phy_dev->phy_id >> 16, phy_dev->phy_id & 0xFFFF);
729 debug("phy_id_compatible_str %s\n", phy_id_compatible_str);
731 ret = fdt_setprop_string(fdt, *subnodeoffset, "compatible",
732 phy_id_compatible_str);
734 printf("%d@%s %d\n", __LINE__, __func__, ret);
738 if (phy_dev->is_c45) {
739 ret = fdt_appendprop_string(fdt, *subnodeoffset, "compatible",
740 "ethernet-phy-ieee802.3-c45");
742 printf("%d@%s %d\n", __LINE__, __func__, ret);
746 ret = fdt_appendprop_string(fdt, *subnodeoffset, "compatible",
747 "ethernet-phy-ieee802.3-c22");
749 printf("%d@%s %d\n", __LINE__, __func__, ret);
754 ret = fdt_setprop_cell(fdt, *subnodeoffset, "reg", phyaddr);
756 printf("%d@%s %d\n", __LINE__, __func__, ret);
760 ret = fdt_set_phandle(fdt, *subnodeoffset, phandle);
762 printf("%d@%s %d\n", __LINE__, __func__, ret);
768 fdt_del_node(fdt, *subnodeoffset);
773 int fdt_fixup_board_phy(void *fdt)
775 int fpga_offset, offset, subnodeoffset;
776 struct mii_dev *mii_dev;
777 struct list_head *mii_devs, *entry;
778 int ret, dpmac_id, i;
779 struct phy_device *phy_dev;
780 char ethname[ETH_NAME_LEN];
781 phy_interface_t phy_iface;
785 /* we know FPGA is connected to i2c0, therefore search path directly,
786 * instead of compatible property, as it saves time
788 fpga_offset = fdt_path_offset(fdt, "/soc/i2c@2000000/fpga");
791 fpga_offset = fdt_path_offset(fdt, "/i2c@2000000/fpga");
793 if (fpga_offset < 0) {
794 printf("i2c@2000000/fpga node not found in device tree\n");
798 ret = fdt_generate_phandle(fdt, &phandle);
802 mii_devs = mdio_get_list_head();
804 list_for_each(entry, mii_devs) {
805 mii_dev = list_entry(entry, struct mii_dev, link);
806 debug("mii_dev name : %s\n", mii_dev->name);
807 offset = fdt_get_ioslot_offset(fdt, mii_dev, fpga_offset);
811 // Look for phy devices attached to MDIO bus muxing front end
812 // and create their entries with compatible being the device id
813 for (i = 0; i < PHY_MAX_ADDR; i++) {
814 phy_dev = mii_dev->phymap[i];
818 // TODO: use sscanf instead of loop
819 dpmac_id = WRIOP1_DPMAC1;
820 while (dpmac_id < NUM_WRIOP_PORTS) {
821 phy_iface = wriop_get_enet_if(dpmac_id);
822 snprintf(ethname, ETH_NAME_LEN, "DPMAC%d@%s",
824 phy_string_for_interface(phy_iface));
825 if (strcmp(ethname, phy_dev->dev->name) == 0)
829 if (dpmac_id == NUM_WRIOP_PORTS)
831 ret = fdt_create_phy_node(fdt, offset, i,
837 ret = fdt_fixup_dpmac_phy_handle(fdt,
840 fdt_del_node(fdt, subnodeoffset);
843 /* calculate offset again as new node addition may have
846 offset = fdt_get_ioslot_offset(fdt, mii_dev,
857 #endif // CONFIG_FSL_MC_ENET
860 #if defined(CONFIG_DM_ETH) && defined(CONFIG_MULTI_DTB_FIT)
862 /* Structure to hold SERDES protocols supported in case of
863 * CONFIG_DM_ETH enabled (network interfaces are described in the DTS).
865 * @serdes_block: the index of the SERDES block
866 * @serdes_protocol: the decimal value of the protocol supported
867 * @dts_needed: DTS notes describing the current configuration are needed
869 * When dts_needed is true, the board_fit_config_name_match() function
870 * will try to exactly match the current configuration of the block with a DTS
873 static struct serdes_configuration {
877 } supported_protocols[] = {
878 /* Serdes block #1 */
884 /* Serdes block #2 */
890 /* Serdes block #3 */
895 #define SUPPORTED_SERDES_PROTOCOLS ARRAY_SIZE(supported_protocols)
897 static bool protocol_supported(u8 serdes_block, u32 protocol)
899 struct serdes_configuration serdes_conf;
902 for (i = 0; i < SUPPORTED_SERDES_PROTOCOLS; i++) {
903 serdes_conf = supported_protocols[i];
904 if (serdes_conf.serdes_block == serdes_block &&
905 serdes_conf.serdes_protocol == protocol)
912 static void get_str_protocol(u8 serdes_block, u32 protocol, char *str)
914 struct serdes_configuration serdes_conf;
917 for (i = 0; i < SUPPORTED_SERDES_PROTOCOLS; i++) {
918 serdes_conf = supported_protocols[i];
919 if (serdes_conf.serdes_block == serdes_block &&
920 serdes_conf.serdes_protocol == protocol) {
921 if (serdes_conf.dts_needed == true)
922 sprintf(str, "%u", protocol);
930 int board_fit_config_name_match(const char *name)
932 struct ccsr_gur *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR);
933 u32 rcw_status = in_le32(&gur->rcwsr[28]);
934 char srds_s1_str[2], srds_s2_str[2], srds_s3_str[2];
935 u32 srds_s1, srds_s2, srds_s3;
936 char expected_dts[100];
938 srds_s1 = rcw_status & FSL_CHASSIS3_RCWSR28_SRDS1_PRTCL_MASK;
939 srds_s1 >>= FSL_CHASSIS3_RCWSR28_SRDS1_PRTCL_SHIFT;
941 srds_s2 = rcw_status & FSL_CHASSIS3_RCWSR28_SRDS2_PRTCL_MASK;
942 srds_s2 >>= FSL_CHASSIS3_RCWSR28_SRDS2_PRTCL_SHIFT;
944 srds_s3 = rcw_status & FSL_CHASSIS3_RCWSR28_SRDS3_PRTCL_MASK;
945 srds_s3 >>= FSL_CHASSIS3_RCWSR28_SRDS3_PRTCL_SHIFT;
947 /* Check for supported protocols. The default DTS will be used
950 if (!protocol_supported(1, srds_s1) ||
951 !protocol_supported(2, srds_s2) ||
952 !protocol_supported(3, srds_s3))
955 get_str_protocol(1, srds_s1, srds_s1_str);
956 get_str_protocol(2, srds_s2, srds_s2_str);
957 get_str_protocol(3, srds_s3, srds_s3_str);
959 sprintf(expected_dts, "fsl-lx2160a-qds-%s-%s-%s",
960 srds_s1_str, srds_s2_str, srds_s3_str);
962 if (!strcmp(name, expected_dts))