2 * Copyright (C) 2017 NXP Semiconductors
3 * Copyright 2015 Freescale Semiconductor
5 * SPDX-License-Identifier: GPL-2.0+
15 #include <fdt_support.h>
17 #include <fsl-mc/fsl_mc.h>
18 #include <environment.h>
19 #include <efi_loader.h>
21 #include <asm/arch/mmu.h>
22 #include <asm/arch/soc.h>
23 #include <asm/arch/ppa.h>
26 #ifdef CONFIG_FSL_QIXIS
27 #include "../common/qixis.h"
28 #include "ls2080ardb_qixis.h"
30 #include "../common/vid.h"
32 #define PIN_MUX_SEL_SDHC 0x00
33 #define PIN_MUX_SEL_DSPI 0x0a
35 #define SET_SDHC_MUX_SEL(reg, value) ((reg & 0xf0) | value)
36 DECLARE_GLOBAL_DATA_PTR;
43 unsigned long long get_qixis_addr(void)
45 unsigned long long addr;
47 if (gd->flags & GD_FLG_RELOC)
48 addr = QIXIS_BASE_PHYS;
50 addr = QIXIS_BASE_PHYS_EARLY;
53 * IFC address under 256MB is mapped to 0x30000000, any address above
54 * is mapped to 0x5_10000000 up to 4GB.
56 addr = addr > 0x10000000 ? addr + 0x500000000ULL : addr + 0x30000000;
63 #ifdef CONFIG_FSL_QIXIS
69 printf("Board: %s-RDB, ", buf);
71 #ifdef CONFIG_TARGET_LS2081ARDB
72 #ifdef CONFIG_FSL_QIXIS
73 sw = QIXIS_READ(arch);
74 printf("Board Arch: V%d, ", sw >> 4);
75 printf("Board version: %c, ", (sw & 0xf) + 'A');
77 sw = QIXIS_READ(brdcfg[0]);
78 sw = (sw & QIXIS_QMAP_MASK) >> QIXIS_QMAP_SHIFT;
81 puts("boot from QSPI DEV#0\n");
82 puts("QSPI_CSA_1 mapped to QSPI DEV#1\n");
85 puts("boot from QSPI DEV#1\n");
86 puts("QSPI_CSA_1 mapped to QSPI DEV#0\n");
89 puts("boot from QSPI EMU\n");
90 puts("QSPI_CSA_1 mapped to QSPI DEV#0\n");
93 puts("boot from QSPI EMU\n");
94 puts("QSPI_CSA_1 mapped to QSPI DEV#1\n");
97 puts("boot from QSPI DEV#0\n");
98 puts("QSPI_CSA_1 mapped to QSPI EMU\n");
101 printf("invalid setting of SW%u\n", sw);
105 puts("SERDES1 Reference : ");
106 printf("Clock1 = 100MHz ");
107 printf("Clock2 = 161.13MHz");
109 #ifdef CONFIG_FSL_QIXIS
110 sw = QIXIS_READ(arch);
111 printf("Board Arch: V%d, ", sw >> 4);
112 printf("Board version: %c, boot from ", (sw & 0xf) + 'A');
114 sw = QIXIS_READ(brdcfg[0]);
115 sw = (sw & QIXIS_LBMAP_MASK) >> QIXIS_LBMAP_SHIFT;
118 printf("vBank: %d\n", sw);
122 printf("invalid setting of SW%u\n", QIXIS_LBMAP_SWITCH);
124 printf("FPGA: v%d.%d\n", QIXIS_READ(scver), QIXIS_READ(tagdata));
126 puts("SERDES1 Reference : ");
127 printf("Clock1 = 156.25MHz ");
128 printf("Clock2 = 156.25MHz");
131 puts("\nSERDES2 Reference : ");
132 printf("Clock1 = 100MHz ");
133 printf("Clock2 = 100MHz\n");
138 unsigned long get_board_sys_clk(void)
140 #ifdef CONFIG_FSL_QIXIS
141 u8 sysclk_conf = QIXIS_READ(brdcfg[1]);
143 switch (sysclk_conf & 0x0F) {
144 case QIXIS_SYSCLK_83:
146 case QIXIS_SYSCLK_100:
148 case QIXIS_SYSCLK_125:
150 case QIXIS_SYSCLK_133:
152 case QIXIS_SYSCLK_150:
154 case QIXIS_SYSCLK_160:
156 case QIXIS_SYSCLK_166:
163 int select_i2c_ch_pca9547(u8 ch)
167 ret = i2c_write(I2C_MUX_PCA_ADDR_PRI, 0, 1, &ch, 1);
169 puts("PCA: failed to select proper channel\n");
176 int i2c_multiplexer_select_vid_channel(u8 channel)
178 return select_i2c_ch_pca9547(channel);
181 int config_board_mux(int ctrl_type)
183 #ifdef CONFIG_FSL_QIXIS
186 reg5 = QIXIS_READ(brdcfg[5]);
190 reg5 = SET_SDHC_MUX_SEL(reg5, PIN_MUX_SEL_SDHC);
193 reg5 = SET_SDHC_MUX_SEL(reg5, PIN_MUX_SEL_DSPI);
196 printf("Wrong mux interface type\n");
200 QIXIS_WRITE(brdcfg[5], reg5);
207 #ifdef CONFIG_FSL_MC_ENET
208 u32 __iomem *irq_ccsr = (u32 __iomem *)ISC_BASE;
211 init_final_memctl_regs();
213 #ifdef CONFIG_ENV_IS_NOWHERE
214 gd->env_addr = (ulong)&default_environment[0];
216 select_i2c_ch_pca9547(I2C_MUX_CH_DEFAULT);
218 #ifdef CONFIG_FSL_QIXIS
219 QIXIS_WRITE(rst_ctl, QIXIS_RST_CTL_RESET_EN);
221 #ifdef CONFIG_FSL_LS_PPA
225 #ifdef CONFIG_FSL_MC_ENET
226 /* invert AQR405 IRQ pins polarity */
227 out_le32(irq_ccsr + IRQCR_OFFSET / 4, AQR405_IRQ_MASK);
229 #ifdef CONFIG_FSL_CAAM
236 int board_early_init_f(void)
238 #ifdef CONFIG_SYS_I2C_EARLY_INIT
241 fsl_lsch3_early_init_f();
245 int misc_init_r(void)
248 u32 __iomem *dcfg_ccsr = (u32 __iomem *)DCFG_BASE;
251 val = in_le32(dcfg_ccsr + DCFG_RCWSR13 / 4);
253 env_hwconfig = getenv("hwconfig");
255 if (hwconfig_f("dspi", env_hwconfig) &&
256 DCFG_RCWSR13_DSPI == (val & (u32)(0xf << 8)))
257 config_board_mux(MUX_TYPE_DSPI);
259 config_board_mux(MUX_TYPE_SDHC);
262 * LS2081ARDB RevF board has smart voltage translator
263 * which needs to be programmed to enable high speed SD interface
264 * by setting GPIO4_10 output to zero
266 #ifdef CONFIG_TARGET_LS2081ARDB
267 out_le32(GPIO4_GPDIR_ADDR, (1 << 21 |
268 in_le32(GPIO4_GPDIR_ADDR)));
269 out_le32(GPIO4_GPDAT_ADDR, (~(1 << 21) &
270 in_le32(GPIO4_GPDAT_ADDR)));
272 if (hwconfig("sdhc"))
273 config_board_mux(MUX_TYPE_SDHC);
276 printf("Warning: Adjusting core voltage failed.\n");
281 void detail_board_ddr_info(void)
284 print_size(gd->bd->bi_dram[0].size + gd->bd->bi_dram[1].size, "");
286 #ifdef CONFIG_SYS_FSL_HAS_DP_DDR
287 if (soc_has_dp_ddr() && gd->bd->bi_dram[2].size) {
289 print_size(gd->bd->bi_dram[2].size, "");
290 print_ddr_info(CONFIG_DP_DDR_CTRL);
295 #if defined(CONFIG_ARCH_MISC_INIT)
296 int arch_misc_init(void)
302 #ifdef CONFIG_FSL_MC_ENET
303 void fdt_fixup_board_enet(void *fdt)
307 offset = fdt_path_offset(fdt, "/soc/fsl-mc");
310 offset = fdt_path_offset(fdt, "/fsl-mc");
313 printf("%s: ERROR: fsl-mc node not found in device tree (error %d)\n",
318 if (get_mc_boot_status() == 0)
319 fdt_status_okay(fdt, offset);
321 fdt_status_fail(fdt, offset);
324 void board_quiesce_devices(void)
326 fsl_mc_ldpaa_exit(gd->bd);
330 #ifdef CONFIG_OF_BOARD_SETUP
331 void fsl_fdt_fixup_flash(void *fdt)
336 * IFC and QSPI are muxed on board.
337 * So disable IFC node in dts if QSPI is enabled or
338 * disable QSPI node in dts in case QSPI is not enabled.
340 #ifdef CONFIG_FSL_QSPI
341 offset = fdt_path_offset(fdt, "/soc/ifc");
344 offset = fdt_path_offset(fdt, "/ifc");
346 offset = fdt_path_offset(fdt, "/soc/quadspi");
349 offset = fdt_path_offset(fdt, "/quadspi");
354 fdt_status_disabled(fdt, offset);
357 int ft_board_setup(void *blob, bd_t *bd)
359 u64 base[CONFIG_NR_DRAM_BANKS];
360 u64 size[CONFIG_NR_DRAM_BANKS];
362 ft_cpu_setup(blob, bd);
364 /* fixup DT for the two GPP DDR banks */
365 base[0] = gd->bd->bi_dram[0].start;
366 size[0] = gd->bd->bi_dram[0].size;
367 base[1] = gd->bd->bi_dram[1].start;
368 size[1] = gd->bd->bi_dram[1].size;
370 #ifdef CONFIG_RESV_RAM
371 /* reduce size if reserved memory is within this bank */
372 if (gd->arch.resv_ram >= base[0] &&
373 gd->arch.resv_ram < base[0] + size[0])
374 size[0] = gd->arch.resv_ram - base[0];
375 else if (gd->arch.resv_ram >= base[1] &&
376 gd->arch.resv_ram < base[1] + size[1])
377 size[1] = gd->arch.resv_ram - base[1];
380 fdt_fixup_memory_banks(blob, base, size, 2);
382 fsl_fdt_fixup_dr_usb(blob, bd);
384 fsl_fdt_fixup_flash(blob);
386 #ifdef CONFIG_FSL_MC_ENET
387 fdt_fixup_board_enet(blob);
394 void qixis_dump_switch(void)
396 #ifdef CONFIG_FSL_QIXIS
399 QIXIS_WRITE(cms[0], 0x00);
400 nr_of_cfgsw = QIXIS_READ(cms[1]);
402 puts("DIP switch settings dump:\n");
403 for (i = 1; i <= nr_of_cfgsw; i++) {
404 QIXIS_WRITE(cms[0], i);
405 printf("SW%d = (0x%02x)\n", i, QIXIS_READ(cms[1]));
411 * Board rev C and earlier has duplicated I2C addresses for 2nd controller.
412 * Both slots has 0x54, resulting 2nd slot unusable.
414 void update_spd_address(unsigned int ctrl_num,
418 #ifndef CONFIG_TARGET_LS2081ARDB
419 #ifdef CONFIG_FSL_QIXIS
422 sw = QIXIS_READ(arch);
423 if ((sw & 0xf) < 0x3) {
424 if (ctrl_num == 1 && slot == 0)
425 *addr = SPD_EEPROM_ADDRESS4;
426 else if (ctrl_num == 1 && slot == 1)
427 *addr = SPD_EEPROM_ADDRESS3;