2 * Copyright 2015 Freescale Semiconductor
4 * SPDX-License-Identifier: GPL-2.0+
14 #include <fdt_support.h>
16 #include <fsl_debug_server.h>
17 #include <fsl-mc/fsl_mc.h>
18 #include <environment.h>
20 #include <asm/arch/soc.h>
22 #include "../common/qixis.h"
23 #include "ls2080ardb_qixis.h"
25 #define PIN_MUX_SEL_SDHC 0x00
26 #define PIN_MUX_SEL_DSPI 0x0a
28 #define SET_SDHC_MUX_SEL(reg, value) ((reg & 0xf0) | value)
29 DECLARE_GLOBAL_DATA_PTR;
36 unsigned long long get_qixis_addr(void)
38 unsigned long long addr;
40 if (gd->flags & GD_FLG_RELOC)
41 addr = QIXIS_BASE_PHYS;
43 addr = QIXIS_BASE_PHYS_EARLY;
46 * IFC address under 256MB is mapped to 0x30000000, any address above
47 * is mapped to 0x5_10000000 up to 4GB.
49 addr = addr > 0x10000000 ? addr + 0x500000000ULL : addr + 0x30000000;
60 printf("Board: %s-RDB, ", buf);
62 sw = QIXIS_READ(arch);
63 printf("Board Arch: V%d, ", sw >> 4);
64 printf("Board version: %c, boot from ", (sw & 0xf) + 'A');
66 sw = QIXIS_READ(brdcfg[0]);
67 sw = (sw & QIXIS_LBMAP_MASK) >> QIXIS_LBMAP_SHIFT;
70 printf("vBank: %d\n", sw);
74 printf("invalid setting of SW%u\n", QIXIS_LBMAP_SWITCH);
76 printf("FPGA: v%d.%d\n", QIXIS_READ(scver), QIXIS_READ(tagdata));
78 puts("SERDES1 Reference : ");
79 printf("Clock1 = 156.25MHz ");
80 printf("Clock2 = 156.25MHz");
82 puts("\nSERDES2 Reference : ");
83 printf("Clock1 = 100MHz ");
84 printf("Clock2 = 100MHz\n");
89 unsigned long get_board_sys_clk(void)
91 u8 sysclk_conf = QIXIS_READ(brdcfg[1]);
93 switch (sysclk_conf & 0x0F) {
96 case QIXIS_SYSCLK_100:
98 case QIXIS_SYSCLK_125:
100 case QIXIS_SYSCLK_133:
102 case QIXIS_SYSCLK_150:
104 case QIXIS_SYSCLK_160:
106 case QIXIS_SYSCLK_166:
112 int select_i2c_ch_pca9547(u8 ch)
116 ret = i2c_write(I2C_MUX_PCA_ADDR_PRI, 0, 1, &ch, 1);
118 puts("PCA: failed to select proper channel\n");
125 int config_board_mux(int ctrl_type)
129 reg5 = QIXIS_READ(brdcfg[5]);
133 reg5 = SET_SDHC_MUX_SEL(reg5, PIN_MUX_SEL_SDHC);
136 reg5 = SET_SDHC_MUX_SEL(reg5, PIN_MUX_SEL_DSPI);
139 printf("Wrong mux interface type\n");
143 QIXIS_WRITE(brdcfg[5], reg5);
151 u32 __iomem *dcfg_ccsr = (u32 __iomem *)DCFG_BASE;
154 init_final_memctl_regs();
156 val = in_le32(dcfg_ccsr + DCFG_RCWSR13 / 4);
158 env_hwconfig = getenv("hwconfig");
160 if (hwconfig_f("dspi", env_hwconfig) &&
161 DCFG_RCWSR13_DSPI == (val & (u32)(0xf << 8)))
162 config_board_mux(MUX_TYPE_DSPI);
164 config_board_mux(MUX_TYPE_SDHC);
166 #ifdef CONFIG_ENV_IS_NOWHERE
167 gd->env_addr = (ulong)&default_environment[0];
169 select_i2c_ch_pca9547(I2C_MUX_CH_DEFAULT);
171 QIXIS_WRITE(rst_ctl, QIXIS_RST_CTL_RESET_EN);
176 int board_early_init_f(void)
178 fsl_lsch3_early_init_f();
182 int misc_init_r(void)
184 if (hwconfig("sdhc"))
185 config_board_mux(MUX_TYPE_SDHC);
190 void detail_board_ddr_info(void)
193 print_size(gd->bd->bi_dram[0].size + gd->bd->bi_dram[1].size, "");
195 #ifdef CONFIG_SYS_FSL_HAS_DP_DDR
196 if (gd->bd->bi_dram[2].size) {
198 print_size(gd->bd->bi_dram[2].size, "");
199 print_ddr_info(CONFIG_DP_DDR_CTRL);
206 gd->ram_size = initdram(0);
211 #if defined(CONFIG_ARCH_MISC_INIT)
212 int arch_misc_init(void)
214 #ifdef CONFIG_FSL_DEBUG_SERVER
222 unsigned long get_dram_size_to_hide(void)
224 unsigned long dram_to_hide = 0;
226 /* Carve the Debug Server private DRAM block from the end of DRAM */
227 #ifdef CONFIG_FSL_DEBUG_SERVER
228 dram_to_hide += debug_server_get_dram_block_size();
231 /* Carve the MC private DRAM block from the end of DRAM */
232 #ifdef CONFIG_FSL_MC_ENET
233 dram_to_hide += mc_get_dram_block_size();
236 return roundup(dram_to_hide, CONFIG_SYS_MEM_TOP_HIDE_MIN);
239 #ifdef CONFIG_FSL_MC_ENET
240 void fdt_fixup_board_enet(void *fdt)
244 offset = fdt_path_offset(fdt, "/fsl-mc");
247 offset = fdt_path_offset(fdt, "/fsl,dprc@0");
250 printf("%s: ERROR: fsl-mc node not found in device tree (error %d)\n",
255 if (get_mc_boot_status() == 0)
256 fdt_status_okay(fdt, offset);
258 fdt_status_fail(fdt, offset);
262 #ifdef CONFIG_OF_BOARD_SETUP
263 int ft_board_setup(void *blob, bd_t *bd)
266 u64 base[CONFIG_NR_DRAM_BANKS];
267 u64 size[CONFIG_NR_DRAM_BANKS];
269 ft_cpu_setup(blob, bd);
271 /* fixup DT for the two GPP DDR banks */
272 base[0] = gd->bd->bi_dram[0].start;
273 size[0] = gd->bd->bi_dram[0].size;
274 base[1] = gd->bd->bi_dram[1].start;
275 size[1] = gd->bd->bi_dram[1].size;
277 fdt_fixup_memory_banks(blob, base, size, 2);
279 #ifdef CONFIG_FSL_MC_ENET
280 fdt_fixup_board_enet(blob);
281 err = fsl_mc_ldpaa_exit(bd);
290 void qixis_dump_switch(void)
294 QIXIS_WRITE(cms[0], 0x00);
295 nr_of_cfgsw = QIXIS_READ(cms[1]);
297 puts("DIP switch settings dump:\n");
298 for (i = 1; i <= nr_of_cfgsw; i++) {
299 QIXIS_WRITE(cms[0], i);
300 printf("SW%d = (0x%02x)\n", i, QIXIS_READ(cms[1]));
305 * Board rev C and earlier has duplicated I2C addresses for 2nd controller.
306 * Both slots has 0x54, resulting 2nd slot unusable.
308 void update_spd_address(unsigned int ctrl_num,
314 sw = QIXIS_READ(arch);
315 if ((sw & 0xf) < 0x3) {
316 if (ctrl_num == 1 && slot == 0)
317 *addr = SPD_EEPROM_ADDRESS4;
318 else if (ctrl_num == 1 && slot == 1)
319 *addr = SPD_EEPROM_ADDRESS3;