board/freescale/ls2080ardb/eth_ls2080rdb.c

   1 /*
   2  * Copyright 2015 Freescale Semiconductor, Inc.
   3  *
   4  *
   5  * SPDX-License-Identifier:     GPL-2.0+
   6  */
   7
   8 #include <common.h>
   9 #include <command.h>
  10 #include <netdev.h>
  11 #include <malloc.h>
  12 #include <fsl_mdio.h>
  13 #include <miiphy.h>
  14 #include <phy.h>
  15 #include <fm_eth.h>
  16 #include <asm/io.h>
  17 #include <exports.h>
  18 #include <asm/arch/fsl_serdes.h>
  19 #include <fsl-mc/ldpaa_wriop.h>
  20
  21 DECLARE_GLOBAL_DATA_PTR;
  22
  23 int load_firmware_cortina(struct phy_device *phy_dev)
  24 {
  25         if (phy_dev->drv->config)
  26                 return phy_dev->drv->config(phy_dev);
  27
  28         return 0;
  29 }
  30
  31 void load_phy_firmware(void)
  32 {
  33         int i;
  34         u8 phy_addr;
  35         struct phy_device *phy_dev;
  36         struct mii_dev *dev;
  37         phy_interface_t interface;
  38
  39         /*Initialize and upload firmware for all the PHYs*/
  40         for (i = WRIOP1_DPMAC1; i <= WRIOP1_DPMAC8; i++) {
  41                 interface = wriop_get_enet_if(i);
  42                 if (interface == PHY_INTERFACE_MODE_XGMII) {
  43                         dev = wriop_get_mdio(i);
  44                         phy_addr = wriop_get_phy_address(i);
  45                         phy_dev = phy_find_by_mask(dev, 1 << phy_addr,
  46                                                 interface);
  47                         if (!phy_dev) {
  48                                 printf("No phydev for phyaddr %d\n", phy_addr);
  49                                 continue;
  50                         }
  51
  52                         /*Flash firmware for All CS4340 PHYS */
  53                         if (phy_dev->phy_id == PHY_UID_CS4340)
  54                                 load_firmware_cortina(phy_dev);
  55                 }
  56         }
  57 }
  58
  59 int board_eth_init(bd_t *bis)
  60 {
  61 #if defined(CONFIG_FSL_MC_ENET)
  62         int i, interface;
  63         struct memac_mdio_info mdio_info;
  64         struct mii_dev *dev;
  65         struct ccsr_gur *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR);
  66         u32 srds_s1;
  67         struct memac_mdio_controller *reg;
  68
  69         srds_s1 = in_le32(&gur->rcwsr[28]) &
  70                                 FSL_CHASSIS3_RCWSR28_SRDS1_PRTCL_MASK;
  71         srds_s1 >>= FSL_CHASSIS3_RCWSR28_SRDS1_PRTCL_SHIFT;
  72
  73         reg = (struct memac_mdio_controller *)CONFIG_SYS_FSL_WRIOP1_MDIO1;
  74         mdio_info.regs = reg;
  75         mdio_info.name = DEFAULT_WRIOP_MDIO1_NAME;
  76
  77         /* Register the EMI 1 */
  78         fm_memac_mdio_init(bis, &mdio_info);
  79
  80         reg = (struct memac_mdio_controller *)CONFIG_SYS_FSL_WRIOP1_MDIO2;
  81         mdio_info.regs = reg;
  82         mdio_info.name = DEFAULT_WRIOP_MDIO2_NAME;
  83
  84         /* Register the EMI 2 */
  85         fm_memac_mdio_init(bis, &mdio_info);
  86
  87         switch (srds_s1) {
  88         case 0x2A:
  89                 wriop_set_phy_address(WRIOP1_DPMAC1, CORTINA_PHY_ADDR1);
  90                 wriop_set_phy_address(WRIOP1_DPMAC2, CORTINA_PHY_ADDR2);
  91                 wriop_set_phy_address(WRIOP1_DPMAC3, CORTINA_PHY_ADDR3);
  92                 wriop_set_phy_address(WRIOP1_DPMAC4, CORTINA_PHY_ADDR4);
  93                 wriop_set_phy_address(WRIOP1_DPMAC5, AQ_PHY_ADDR1);
  94                 wriop_set_phy_address(WRIOP1_DPMAC6, AQ_PHY_ADDR2);
  95                 wriop_set_phy_address(WRIOP1_DPMAC7, AQ_PHY_ADDR3);
  96                 wriop_set_phy_address(WRIOP1_DPMAC8, AQ_PHY_ADDR4);
  97
  98                 break;
  99         default:
 100                 printf("SerDes1 protocol 0x%x is not supported on LS2080aRDB\n",
 101                        srds_s1);
 102                 break;
 103         }
 104
 105         for (i = WRIOP1_DPMAC1; i <= WRIOP1_DPMAC4; i++) {
 106                 interface = wriop_get_enet_if(i);
 107                 switch (interface) {
 108                 case PHY_INTERFACE_MODE_XGMII:
 109                         dev = miiphy_get_dev_by_name(DEFAULT_WRIOP_MDIO1_NAME);
 110                         wriop_set_mdio(i, dev);
 111                         break;
 112                 default:
 113                         break;
 114                 }
 115         }
 116
 117         for (i = WRIOP1_DPMAC5; i <= WRIOP1_DPMAC8; i++) {
 118                 switch (wriop_get_enet_if(i)) {
 119                 case PHY_INTERFACE_MODE_XGMII:
 120                         dev = miiphy_get_dev_by_name(DEFAULT_WRIOP_MDIO2_NAME);
 121                         wriop_set_mdio(i, dev);
 122                         break;
 123                 default:
 124                         break;
 125                 }
 126         }
 127
 128         /* Load CORTINA CS4340 PHY firmware */
 129         load_phy_firmware();
 130
 131         cpu_eth_init(bis);
 132 #endif /* CONFIG_FMAN_ENET */
 133
 134 #ifdef CONFIG_PHY_AQUANTIA
 135         /*
 136          * Export functions to be used by AQ firmware
 137          * upload application
 138          */
 139         gd->jt->strcpy = strcpy;
 140         gd->jt->mdelay = mdelay;
 141         gd->jt->mdio_get_current_dev = mdio_get_current_dev;
 142         gd->jt->phy_find_by_mask = phy_find_by_mask;
 143         gd->jt->mdio_phydev_for_ethname = mdio_phydev_for_ethname;
 144         gd->jt->miiphy_set_current_dev = miiphy_set_current_dev;
 145 #endif
 146         return pci_eth_init(bis);
 147 }