1 // SPDX-License-Identifier: GPL-2.0+
3 * Copyright 2015 Freescale Semiconductor, Inc.
12 #include <asm/arch/fsl_serdes.h>
19 #include <fsl-mc/fsl_mc.h>
20 #include <fsl-mc/ldpaa_wriop.h>
22 #include "../common/qixis.h"
24 #include "ls2080aqds_qixis.h"
26 #define MC_BOOT_ENV_VAR "mcinitcmd"
28 #if defined(CONFIG_FSL_MC_ENET) && !defined(CONFIG_SPL_BUILD)
29 /* - In LS2080A there are only 16 SERDES lanes, spread across 2 SERDES banks.
30 * Bank 1 -> Lanes A, B, C, D, E, F, G, H
31 * Bank 2 -> Lanes A,B, C, D, E, F, G, H
34 /* Mapping of 16 SERDES lanes to LS2080A QDS board slots. A value of '0' here
35 * means that the mapping must be determined dynamically, or that the lane
36 * maps to something other than a board slot.
39 static u8 lane_to_slot_fsm1[] = {
40 0, 0, 0, 0, 0, 0, 0, 0
43 static u8 lane_to_slot_fsm2[] = {
44 0, 0, 0, 0, 0, 0, 0, 0
47 /* On the Vitesse VSC8234XHG SGMII riser card there are 4 SGMII PHYs
51 static int xqsgii_riser_phy_addr[] = {
52 XQSGMII_CARD_PHY1_PORT0_ADDR,
53 XQSGMII_CARD_PHY2_PORT0_ADDR,
54 XQSGMII_CARD_PHY3_PORT0_ADDR,
55 XQSGMII_CARD_PHY4_PORT0_ADDR,
56 XQSGMII_CARD_PHY3_PORT2_ADDR,
57 XQSGMII_CARD_PHY1_PORT2_ADDR,
58 XQSGMII_CARD_PHY4_PORT2_ADDR,
59 XQSGMII_CARD_PHY2_PORT2_ADDR,
62 static int sgmii_riser_phy_addr[] = {
63 SGMII_CARD_PORT1_PHY_ADDR,
64 SGMII_CARD_PORT2_PHY_ADDR,
65 SGMII_CARD_PORT3_PHY_ADDR,
66 SGMII_CARD_PORT4_PHY_ADDR,
69 /* Slot2 does not have EMI connections */
80 static const char * const mdio_names[] = {
87 DEFAULT_WRIOP_MDIO2_NAME,
90 struct ls2080a_qds_mdio {
92 struct mii_dev *realbus;
100 static void sgmii_configure_repeater(int serdes_port)
105 int dpmac_id = 0, dpmac, mii_bus = 0;
106 unsigned short value;
107 char dev[2][20] = {"LS2080A_QDS_MDIO0", "LS2080A_QDS_MDIO3"};
108 uint8_t i2c_addr[] = {0x58, 0x59, 0x5a, 0x5b, 0x5c, 0x5d, 0x5f, 0x60};
110 uint8_t ch_a_eq[] = {0x1, 0x2, 0x3, 0x7};
111 uint8_t ch_a_ctl2[] = {0x81, 0x82, 0x83, 0x84};
112 uint8_t ch_b_eq[] = {0x1, 0x2, 0x3, 0x7};
113 uint8_t ch_b_ctl2[] = {0x81, 0x82, 0x83, 0x84};
115 u8 reg_val[6] = {0x18, 0x38, 0x4, 0x14, 0xb5, 0x20};
116 struct reg_pair reg_pair[10] = {
117 {6, ®_val[0]}, {4, ®_val[1]},
118 {8, ®_val[2]}, {0xf, NULL},
119 {0x11, NULL}, {0x16, NULL},
120 {0x18, NULL}, {0x23, ®_val[3]},
121 {0x2d, ®_val[4]}, {4, ®_val[5]},
124 int *riser_phy_addr = &xqsgii_riser_phy_addr[0];
126 struct udevice *udev;
129 /* Set I2c to Slot 1 */
130 #ifndef CONFIG_DM_I2C
131 ret = i2c_write(0x77, 0, 0, &a, 1);
133 ret = i2c_get_chip_for_busnum(0, 0x77, 1, &udev);
135 ret = dm_i2c_write(udev, 0, &a, 1);
140 for (dpmac = 0; dpmac < 8; dpmac++) {
141 /* Check the PHY status */
142 switch (serdes_port) {
145 dpmac_id = dpmac + 1;
149 dpmac_id = dpmac + 9;
151 #ifndef CONFIG_DM_I2C
152 ret = i2c_write(0x76, 0, 0, &a, 1);
154 ret = i2c_get_chip_for_busnum(0, 0x76, 1, &udev);
156 ret = dm_i2c_write(udev, 0, &a, 1);
163 ret = miiphy_set_current_dev(dev[mii_bus]);
167 bus = mdio_get_current_dev();
168 debug("Reading from bus %s\n", bus->name);
170 ret = miiphy_write(dev[mii_bus], riser_phy_addr[dpmac], 0x1f,
176 ret = miiphy_read(dev[mii_bus], riser_phy_addr[dpmac], 0x11,
183 if ((value & 0xfff) == 0x401) {
184 printf("DPMAC %d:PHY is ..... Configured\n", dpmac_id);
185 miiphy_write(dev[mii_bus], riser_phy_addr[dpmac],
190 for (i = 0; i < 4; i++) {
191 for (j = 0; j < 4; j++) {
192 reg_pair[3].val = &ch_a_eq[i];
193 reg_pair[4].val = &ch_a_ctl2[j];
194 reg_pair[5].val = &ch_b_eq[i];
195 reg_pair[6].val = &ch_b_ctl2[j];
197 for (k = 0; k < 10; k++) {
198 #ifndef CONFIG_DM_I2C
199 ret = i2c_write(i2c_addr[dpmac],
201 1, reg_pair[k].val, 1);
203 ret = i2c_get_chip_for_busnum(0,
207 ret = dm_i2c_write(udev,
216 ret = miiphy_read(dev[mii_bus],
217 riser_phy_addr[dpmac],
223 ret = miiphy_read(dev[mii_bus],
224 riser_phy_addr[dpmac],
229 if ((value & 0xfff) == 0x401) {
230 printf("DPMAC %d :PHY is configured ",
232 printf("after setting repeater 0x%x\n",
237 printf("DPMAC %d :PHY is failed to ",
239 printf("configure the repeater 0x%x\n",
244 miiphy_write(dev[mii_bus], riser_phy_addr[dpmac], 0x1f, 0);
248 printf("DPMAC %d ..... FAILED to configure PHY\n", dpmac_id);
252 static void qsgmii_configure_repeater(int dpmac)
256 int i2c_phy_addr = 0;
258 int i2c_addr[] = {0x58, 0x59, 0x5a, 0x5b};
260 uint8_t ch_a_eq[] = {0x1, 0x2, 0x3, 0x7};
261 uint8_t ch_a_ctl2[] = {0x81, 0x82, 0x83, 0x84};
262 uint8_t ch_b_eq[] = {0x1, 0x2, 0x3, 0x7};
263 uint8_t ch_b_ctl2[] = {0x81, 0x82, 0x83, 0x84};
265 u8 reg_val[6] = {0x18, 0x38, 0x4, 0x14, 0xb5, 0x20};
266 struct reg_pair reg_pair[10] = {
267 {6, ®_val[0]}, {4, ®_val[1]},
268 {8, ®_val[2]}, {0xf, NULL},
269 {0x11, NULL}, {0x16, NULL},
270 {0x18, NULL}, {0x23, ®_val[3]},
271 {0x2d, ®_val[4]}, {4, ®_val[5]},
274 const char *dev = "LS2080A_QDS_MDIO0";
276 unsigned short value;
278 struct udevice *udev;
281 /* Set I2c to Slot 1 */
282 #ifndef CONFIG_DM_I2C
283 ret = i2c_write(0x77, 0, 0, &a, 1);
285 ret = i2c_get_chip_for_busnum(0, 0x77, 1, &udev);
287 ret = dm_i2c_write(udev, 0, &a, 1);
297 i2c_phy_addr = i2c_addr[0];
305 i2c_phy_addr = i2c_addr[1];
313 i2c_phy_addr = i2c_addr[2];
321 i2c_phy_addr = i2c_addr[3];
326 /* Check the PHY status */
327 ret = miiphy_set_current_dev(dev);
328 ret = miiphy_write(dev, phy_addr, 0x1f, 3);
330 ret = miiphy_read(dev, phy_addr, 0x11, &value);
332 ret = miiphy_read(dev, phy_addr, 0x11, &value);
334 if ((value & 0xf) == 0xf) {
335 printf("DPMAC %d :PHY is ..... Configured\n", dpmac);
339 for (i = 0; i < 4; i++) {
340 for (j = 0; j < 4; j++) {
341 reg_pair[3].val = &ch_a_eq[i];
342 reg_pair[4].val = &ch_a_ctl2[j];
343 reg_pair[5].val = &ch_b_eq[i];
344 reg_pair[6].val = &ch_b_ctl2[j];
346 for (k = 0; k < 10; k++) {
347 #ifndef CONFIG_DM_I2C
348 ret = i2c_write(i2c_phy_addr,
350 1, reg_pair[k].val, 1);
352 ret = i2c_get_chip_for_busnum(0,
356 ret = dm_i2c_write(udev,
365 ret = miiphy_read(dev, phy_addr, 0x11, &value);
369 ret = miiphy_read(dev, phy_addr, 0x11, &value);
373 if ((value & 0xf) == 0xf) {
374 printf("DPMAC %d :PHY is ..... Configured\n",
381 printf("DPMAC %d :PHY ..... FAILED to configure PHY\n", dpmac);
385 static const char *ls2080a_qds_mdio_name_for_muxval(u8 muxval)
387 return mdio_names[muxval];
390 struct mii_dev *mii_dev_for_muxval(u8 muxval)
393 const char *name = ls2080a_qds_mdio_name_for_muxval(muxval);
396 printf("No bus for muxval %x\n", muxval);
400 bus = miiphy_get_dev_by_name(name);
403 printf("No bus by name %s\n", name);
410 static void ls2080a_qds_enable_SFP_TX(u8 muxval)
414 brdcfg9 = QIXIS_READ(brdcfg[9]);
415 brdcfg9 &= ~BRDCFG9_SFPTX_MASK;
416 brdcfg9 |= (muxval << BRDCFG9_SFPTX_SHIFT);
417 QIXIS_WRITE(brdcfg[9], brdcfg9);
420 static void ls2080a_qds_mux_mdio(u8 muxval)
425 brdcfg4 = QIXIS_READ(brdcfg[4]);
426 brdcfg4 &= ~BRDCFG4_EMISEL_MASK;
427 brdcfg4 |= (muxval << BRDCFG4_EMISEL_SHIFT);
428 QIXIS_WRITE(brdcfg[4], brdcfg4);
432 static int ls2080a_qds_mdio_read(struct mii_dev *bus, int addr,
433 int devad, int regnum)
435 struct ls2080a_qds_mdio *priv = bus->priv;
437 ls2080a_qds_mux_mdio(priv->muxval);
439 return priv->realbus->read(priv->realbus, addr, devad, regnum);
442 static int ls2080a_qds_mdio_write(struct mii_dev *bus, int addr, int devad,
443 int regnum, u16 value)
445 struct ls2080a_qds_mdio *priv = bus->priv;
447 ls2080a_qds_mux_mdio(priv->muxval);
449 return priv->realbus->write(priv->realbus, addr, devad, regnum, value);
452 static int ls2080a_qds_mdio_reset(struct mii_dev *bus)
454 struct ls2080a_qds_mdio *priv = bus->priv;
456 return priv->realbus->reset(priv->realbus);
459 static int ls2080a_qds_mdio_init(char *realbusname, u8 muxval)
461 struct ls2080a_qds_mdio *pmdio;
462 struct mii_dev *bus = mdio_alloc();
465 printf("Failed to allocate ls2080a_qds MDIO bus\n");
469 pmdio = malloc(sizeof(*pmdio));
471 printf("Failed to allocate ls2080a_qds private data\n");
476 bus->read = ls2080a_qds_mdio_read;
477 bus->write = ls2080a_qds_mdio_write;
478 bus->reset = ls2080a_qds_mdio_reset;
479 strcpy(bus->name, ls2080a_qds_mdio_name_for_muxval(muxval));
481 pmdio->realbus = miiphy_get_dev_by_name(realbusname);
483 if (!pmdio->realbus) {
484 printf("No bus with name %s\n", realbusname);
490 pmdio->muxval = muxval;
493 return mdio_register(bus);
497 * Initialize the dpmac_info array.
500 static void initialize_dpmac_to_slot(void)
502 struct ccsr_gur __iomem *gur = (void *)CONFIG_SYS_FSL_GUTS_ADDR;
503 int serdes1_prtcl = (in_le32(&gur->rcwsr[28]) &
504 FSL_CHASSIS3_RCWSR28_SRDS1_PRTCL_MASK)
505 >> FSL_CHASSIS3_RCWSR28_SRDS1_PRTCL_SHIFT;
506 int serdes2_prtcl = (in_le32(&gur->rcwsr[28]) &
507 FSL_CHASSIS3_RCWSR28_SRDS2_PRTCL_MASK)
508 >> FSL_CHASSIS3_RCWSR28_SRDS2_PRTCL_SHIFT;
511 env_hwconfig = env_get("hwconfig");
513 switch (serdes1_prtcl) {
517 printf("qds: WRIOP: Supported SerDes1 Protocol 0x%02x\n",
519 lane_to_slot_fsm1[0] = EMI1_SLOT1;
520 lane_to_slot_fsm1[1] = EMI1_SLOT1;
521 lane_to_slot_fsm1[2] = EMI1_SLOT1;
522 lane_to_slot_fsm1[3] = EMI1_SLOT1;
523 if (hwconfig_f("xqsgmii", env_hwconfig)) {
524 lane_to_slot_fsm1[4] = EMI1_SLOT1;
525 lane_to_slot_fsm1[5] = EMI1_SLOT1;
526 lane_to_slot_fsm1[6] = EMI1_SLOT1;
527 lane_to_slot_fsm1[7] = EMI1_SLOT1;
529 lane_to_slot_fsm1[4] = EMI1_SLOT2;
530 lane_to_slot_fsm1[5] = EMI1_SLOT2;
531 lane_to_slot_fsm1[6] = EMI1_SLOT2;
532 lane_to_slot_fsm1[7] = EMI1_SLOT2;
537 printf("qds: WRIOP: Supported SerDes1 Protocol 0x%02x\n",
539 if (hwconfig_f("xqsgmii", env_hwconfig)) {
540 lane_to_slot_fsm1[0] = EMI1_SLOT3;
541 lane_to_slot_fsm1[1] = EMI1_SLOT3;
542 lane_to_slot_fsm1[2] = EMI1_SLOT3;
543 lane_to_slot_fsm1[3] = EMI_NONE;
545 lane_to_slot_fsm1[0] = EMI_NONE;
546 lane_to_slot_fsm1[1] = EMI_NONE;
547 lane_to_slot_fsm1[2] = EMI_NONE;
548 lane_to_slot_fsm1[3] = EMI_NONE;
550 lane_to_slot_fsm1[4] = EMI1_SLOT3;
551 lane_to_slot_fsm1[5] = EMI1_SLOT3;
552 lane_to_slot_fsm1[6] = EMI1_SLOT3;
553 lane_to_slot_fsm1[7] = EMI_NONE;
557 printf("qds: WRIOP: Supported SerDes1 Protocol 0x%02x\n",
559 if (hwconfig_f("xqsgmii", env_hwconfig)) {
560 lane_to_slot_fsm1[0] = EMI1_SLOT3;
561 lane_to_slot_fsm1[1] = EMI1_SLOT3;
562 lane_to_slot_fsm1[2] = EMI_NONE;
563 lane_to_slot_fsm1[3] = EMI_NONE;
565 lane_to_slot_fsm1[0] = EMI_NONE;
566 lane_to_slot_fsm1[1] = EMI_NONE;
567 lane_to_slot_fsm1[2] = EMI_NONE;
568 lane_to_slot_fsm1[3] = EMI_NONE;
570 lane_to_slot_fsm1[4] = EMI1_SLOT3;
571 lane_to_slot_fsm1[5] = EMI1_SLOT3;
572 lane_to_slot_fsm1[6] = EMI_NONE;
573 lane_to_slot_fsm1[7] = EMI_NONE;
579 printf("qds: WRIOP: Supported SerDes1 Protocol 0x%02x\n",
583 printf("%s qds: WRIOP: Unsupported SerDes1 Protocol 0x%02x\n",
584 __func__, serdes1_prtcl);
588 switch (serdes2_prtcl) {
593 printf("qds: WRIOP: Supported SerDes2 Protocol 0x%02x\n",
595 lane_to_slot_fsm2[0] = EMI1_SLOT4;
596 lane_to_slot_fsm2[1] = EMI1_SLOT4;
597 lane_to_slot_fsm2[2] = EMI1_SLOT4;
598 lane_to_slot_fsm2[3] = EMI1_SLOT4;
600 if (hwconfig_f("xqsgmii", env_hwconfig)) {
601 lane_to_slot_fsm2[4] = EMI1_SLOT4;
602 lane_to_slot_fsm2[5] = EMI1_SLOT4;
603 lane_to_slot_fsm2[6] = EMI1_SLOT4;
604 lane_to_slot_fsm2[7] = EMI1_SLOT4;
606 /* No MDIO physical connection */
607 lane_to_slot_fsm2[4] = EMI1_SLOT6;
608 lane_to_slot_fsm2[5] = EMI1_SLOT6;
609 lane_to_slot_fsm2[6] = EMI1_SLOT6;
610 lane_to_slot_fsm2[7] = EMI1_SLOT6;
615 printf("qds: WRIOP: Supported SerDes2 Protocol 0x%02x\n",
617 lane_to_slot_fsm2[0] = EMI_NONE;
618 lane_to_slot_fsm2[1] = EMI1_SLOT5;
619 lane_to_slot_fsm2[2] = EMI1_SLOT5;
620 lane_to_slot_fsm2[3] = EMI1_SLOT5;
622 if (hwconfig_f("xqsgmii", env_hwconfig)) {
623 lane_to_slot_fsm2[4] = EMI_NONE;
624 lane_to_slot_fsm2[5] = EMI1_SLOT5;
625 lane_to_slot_fsm2[6] = EMI1_SLOT5;
626 lane_to_slot_fsm2[7] = EMI1_SLOT5;
631 printf("qds: WRIOP: Supported SerDes2 Protocol 0x%02x\n",
633 if (hwconfig_f("xqsgmii", env_hwconfig)) {
634 lane_to_slot_fsm2[0] = EMI_NONE;
635 lane_to_slot_fsm2[1] = EMI_NONE;
636 lane_to_slot_fsm2[2] = EMI_NONE;
637 lane_to_slot_fsm2[3] = EMI_NONE;
639 lane_to_slot_fsm2[4] = EMI_NONE;
640 lane_to_slot_fsm2[5] = EMI_NONE;
641 lane_to_slot_fsm2[6] = EMI1_SLOT5;
642 lane_to_slot_fsm2[7] = EMI1_SLOT5;
646 printf(" %s qds: WRIOP: Unsupported SerDes2 Protocol 0x%02x\n",
647 __func__ , serdes2_prtcl);
652 void ls2080a_handle_phy_interface_sgmii(int dpmac_id)
656 struct ccsr_gur __iomem *gur = (void *)CONFIG_SYS_FSL_GUTS_ADDR;
657 int serdes1_prtcl = (in_le32(&gur->rcwsr[28]) &
658 FSL_CHASSIS3_RCWSR28_SRDS1_PRTCL_MASK)
659 >> FSL_CHASSIS3_RCWSR28_SRDS1_PRTCL_SHIFT;
660 int serdes2_prtcl = (in_le32(&gur->rcwsr[28]) &
661 FSL_CHASSIS3_RCWSR28_SRDS2_PRTCL_MASK)
662 >> FSL_CHASSIS3_RCWSR28_SRDS2_PRTCL_SHIFT;
665 char *env_hwconfig = env_get("hwconfig");
667 if (hwconfig_f("xqsgmii", env_hwconfig))
668 riser_phy_addr = &xqsgii_riser_phy_addr[0];
670 riser_phy_addr = &sgmii_riser_phy_addr[0];
672 if (dpmac_id > WRIOP1_DPMAC9)
675 switch (serdes1_prtcl) {
679 lane = serdes_get_first_lane(FSL_SRDS_1, SGMII1 + dpmac_id - 1);
681 slot = lane_to_slot_fsm1[lane];
685 /* Slot housing a SGMII riser card? */
686 wriop_set_phy_address(dpmac_id, 0,
687 riser_phy_addr[dpmac_id - 1]);
688 dpmac_info[dpmac_id].board_mux = EMI1_SLOT1;
689 bus = mii_dev_for_muxval(EMI1_SLOT1);
690 wriop_set_mdio(dpmac_id, bus);
693 /* Slot housing a SGMII riser card? */
694 wriop_set_phy_address(dpmac_id, 0,
695 riser_phy_addr[dpmac_id - 1]);
696 dpmac_info[dpmac_id].board_mux = EMI1_SLOT2;
697 bus = mii_dev_for_muxval(EMI1_SLOT2);
698 wriop_set_mdio(dpmac_id, bus);
701 if (slot == EMI_NONE)
703 if (serdes1_prtcl == 0x39) {
704 wriop_set_phy_address(dpmac_id, 0,
705 riser_phy_addr[dpmac_id - 2]);
706 if (dpmac_id >= 6 && hwconfig_f("xqsgmii",
708 wriop_set_phy_address(dpmac_id, 0,
709 riser_phy_addr[dpmac_id - 3]);
711 wriop_set_phy_address(dpmac_id, 0,
712 riser_phy_addr[dpmac_id - 2]);
713 if (dpmac_id >= 7 && hwconfig_f("xqsgmii",
715 wriop_set_phy_address(dpmac_id, 0,
716 riser_phy_addr[dpmac_id - 3]);
718 dpmac_info[dpmac_id].board_mux = EMI1_SLOT3;
719 bus = mii_dev_for_muxval(EMI1_SLOT3);
720 wriop_set_mdio(dpmac_id, bus);
731 printf("%s qds: WRIOP: Unsupported SerDes1 Protocol 0x%02x\n",
732 __func__ , serdes1_prtcl);
737 switch (serdes2_prtcl) {
743 lane = serdes_get_first_lane(FSL_SRDS_2, SGMII9 +
745 slot = lane_to_slot_fsm2[lane];
753 /* Slot housing a SGMII riser card? */
754 wriop_set_phy_address(dpmac_id, 0,
755 riser_phy_addr[dpmac_id - 9]);
756 dpmac_info[dpmac_id].board_mux = EMI1_SLOT4;
757 bus = mii_dev_for_muxval(EMI1_SLOT4);
758 wriop_set_mdio(dpmac_id, bus);
761 if (slot == EMI_NONE)
763 if (serdes2_prtcl == 0x47) {
764 wriop_set_phy_address(dpmac_id, 0,
765 riser_phy_addr[dpmac_id - 10]);
766 if (dpmac_id >= 14 && hwconfig_f("xqsgmii",
768 wriop_set_phy_address(dpmac_id, 0,
769 riser_phy_addr[dpmac_id - 11]);
771 wriop_set_phy_address(dpmac_id, 0,
772 riser_phy_addr[dpmac_id - 11]);
774 dpmac_info[dpmac_id].board_mux = EMI1_SLOT5;
775 bus = mii_dev_for_muxval(EMI1_SLOT5);
776 wriop_set_mdio(dpmac_id, bus);
779 /* Slot housing a SGMII riser card? */
780 wriop_set_phy_address(dpmac_id, 0,
781 riser_phy_addr[dpmac_id - 13]);
782 dpmac_info[dpmac_id].board_mux = EMI1_SLOT6;
783 bus = mii_dev_for_muxval(EMI1_SLOT6);
784 wriop_set_mdio(dpmac_id, bus);
789 printf("%s qds: WRIOP: Unsupported SerDes2 Protocol 0x%02x\n",
790 __func__, serdes2_prtcl);
795 void ls2080a_handle_phy_interface_qsgmii(int dpmac_id)
799 struct ccsr_gur __iomem *gur = (void *)CONFIG_SYS_FSL_GUTS_ADDR;
800 int serdes1_prtcl = (in_le32(&gur->rcwsr[28]) &
801 FSL_CHASSIS3_RCWSR28_SRDS1_PRTCL_MASK)
802 >> FSL_CHASSIS3_RCWSR28_SRDS1_PRTCL_SHIFT;
804 switch (serdes1_prtcl) {
811 lane = serdes_get_first_lane(FSL_SRDS_1, QSGMII_A);
817 lane = serdes_get_first_lane(FSL_SRDS_1, QSGMII_B);
823 lane = serdes_get_first_lane(FSL_SRDS_1, QSGMII_C);
829 lane = serdes_get_first_lane(FSL_SRDS_1, QSGMII_D);
833 slot = lane_to_slot_fsm1[lane];
837 /* Slot housing a QSGMII riser card? */
838 wriop_set_phy_address(dpmac_id, 0, dpmac_id - 1);
839 dpmac_info[dpmac_id].board_mux = EMI1_SLOT1;
840 bus = mii_dev_for_muxval(EMI1_SLOT1);
841 wriop_set_mdio(dpmac_id, bus);
854 printf("qds: WRIOP: Unsupported SerDes Protocol 0x%02x\n",
859 qsgmii_configure_repeater(dpmac_id);
862 void ls2080a_handle_phy_interface_xsgmii(int i)
864 struct ccsr_gur __iomem *gur = (void *)CONFIG_SYS_FSL_GUTS_ADDR;
865 int serdes1_prtcl = (in_le32(&gur->rcwsr[28]) &
866 FSL_CHASSIS3_RCWSR28_SRDS1_PRTCL_MASK)
867 >> FSL_CHASSIS3_RCWSR28_SRDS1_PRTCL_SHIFT;
869 switch (serdes1_prtcl) {
874 * XFI does not need a PHY to work, but to avoid U-Boot use
875 * default PHY address which is zero to a MAC when it found
876 * a MAC has no PHY address, we give a PHY address to XFI
877 * MAC, and should not use a real XAUI PHY address, since
878 * MDIO can access it successfully, and then MDIO thinks
879 * the XAUI card is used for the XFI MAC, which will cause
882 wriop_set_phy_address(i, 0, i + 4);
883 ls2080a_qds_enable_SFP_TX(SFP_TX);
887 printf("qds: WRIOP: Unsupported SerDes Protocol 0x%02x\n",
894 int board_eth_init(bd_t *bis)
897 #if defined(CONFIG_FSL_MC_ENET) && !defined(CONFIG_SPL_BUILD)
898 struct ccsr_gur __iomem *gur = (void *)CONFIG_SYS_FSL_GUTS_ADDR;
899 int serdes1_prtcl = (in_le32(&gur->rcwsr[28]) &
900 FSL_CHASSIS3_RCWSR28_SRDS1_PRTCL_MASK)
901 >> FSL_CHASSIS3_RCWSR28_SRDS1_PRTCL_SHIFT;
902 int serdes2_prtcl = (in_le32(&gur->rcwsr[28]) &
903 FSL_CHASSIS3_RCWSR28_SRDS2_PRTCL_MASK)
904 >> FSL_CHASSIS3_RCWSR28_SRDS2_PRTCL_SHIFT;
906 struct memac_mdio_info *memac_mdio0_info;
907 struct memac_mdio_info *memac_mdio1_info;
911 env_hwconfig = env_get("hwconfig");
913 initialize_dpmac_to_slot();
915 memac_mdio0_info = (struct memac_mdio_info *)malloc(
916 sizeof(struct memac_mdio_info));
917 memac_mdio0_info->regs =
918 (struct memac_mdio_controller *)
919 CONFIG_SYS_FSL_WRIOP1_MDIO1;
920 memac_mdio0_info->name = DEFAULT_WRIOP_MDIO1_NAME;
922 /* Register the real MDIO1 bus */
923 fm_memac_mdio_init(bis, memac_mdio0_info);
925 memac_mdio1_info = (struct memac_mdio_info *)malloc(
926 sizeof(struct memac_mdio_info));
927 memac_mdio1_info->regs =
928 (struct memac_mdio_controller *)
929 CONFIG_SYS_FSL_WRIOP1_MDIO2;
930 memac_mdio1_info->name = DEFAULT_WRIOP_MDIO2_NAME;
932 /* Register the real MDIO2 bus */
933 fm_memac_mdio_init(bis, memac_mdio1_info);
935 /* Register the muxing front-ends to the MDIO buses */
936 ls2080a_qds_mdio_init(DEFAULT_WRIOP_MDIO1_NAME, EMI1_SLOT1);
937 ls2080a_qds_mdio_init(DEFAULT_WRIOP_MDIO1_NAME, EMI1_SLOT2);
938 ls2080a_qds_mdio_init(DEFAULT_WRIOP_MDIO1_NAME, EMI1_SLOT3);
939 ls2080a_qds_mdio_init(DEFAULT_WRIOP_MDIO1_NAME, EMI1_SLOT4);
940 ls2080a_qds_mdio_init(DEFAULT_WRIOP_MDIO1_NAME, EMI1_SLOT5);
941 ls2080a_qds_mdio_init(DEFAULT_WRIOP_MDIO1_NAME, EMI1_SLOT6);
943 ls2080a_qds_mdio_init(DEFAULT_WRIOP_MDIO2_NAME, EMI2);
945 for (i = WRIOP1_DPMAC1; i < NUM_WRIOP_PORTS; i++) {
946 switch (wriop_get_enet_if(i)) {
947 case PHY_INTERFACE_MODE_QSGMII:
948 ls2080a_handle_phy_interface_qsgmii(i);
950 case PHY_INTERFACE_MODE_SGMII:
951 ls2080a_handle_phy_interface_sgmii(i);
953 case PHY_INTERFACE_MODE_XGMII:
954 ls2080a_handle_phy_interface_xsgmii(i);
964 error = cpu_eth_init(bis);
966 if (hwconfig_f("xqsgmii", env_hwconfig)) {
967 if (serdes1_prtcl == 0x7)
968 sgmii_configure_repeater(1);
969 if (serdes2_prtcl == 0x7 || serdes2_prtcl == 0x8 ||
970 serdes2_prtcl == 0x49)
971 sgmii_configure_repeater(2);
974 error = pci_eth_init(bis);
978 #if defined(CONFIG_RESET_PHY_R)
983 #endif /* CONFIG_RESET_PHY_R */