board/freescale/ls2080aqds/eth.c

   1 // SPDX-License-Identifier: GPL-2.0+
   2 /*
   3  * Copyright 2015 Freescale Semiconductor, Inc.
   4  */
   5
   6 #include <common.h>
   7 #include <env.h>
   8 #include <net.h>
   9 #include <netdev.h>
  10 #include <asm/io.h>
  11 #include <asm/arch/fsl_serdes.h>
  12 #include <hwconfig.h>
  13 #include <fsl_mdio.h>
  14 #include <malloc.h>
  15 #include <fm_eth.h>
  16 #include <i2c.h>
  17 #include <miiphy.h>
  18 #include <fsl-mc/fsl_mc.h>
  19 #include <fsl-mc/ldpaa_wriop.h>
  20
  21 #include "../common/qixis.h"
  22
  23 #include "ls2080aqds_qixis.h"
  24
  25 #define MC_BOOT_ENV_VAR "mcinitcmd"
  26
  27 #if defined(CONFIG_FSL_MC_ENET) && !defined(CONFIG_SPL_BUILD)
  28  /* - In LS2080A there are only 16 SERDES lanes, spread across 2 SERDES banks.
  29  *   Bank 1 -> Lanes A, B, C, D, E, F, G, H
  30  *   Bank 2 -> Lanes A,B, C, D, E, F, G, H
  31  */
  32
  33  /* Mapping of 16 SERDES lanes to LS2080A QDS board slots. A value of '0' here
  34   * means that the mapping must be determined dynamically, or that the lane
  35   * maps to something other than a board slot.
  36   */
  37
  38 static u8 lane_to_slot_fsm1[] = {
  39         0, 0, 0, 0, 0, 0, 0, 0
  40 };
  41
  42 static u8 lane_to_slot_fsm2[] = {
  43         0, 0, 0, 0, 0, 0, 0, 0
  44 };
  45
  46 /* On the Vitesse VSC8234XHG SGMII riser card there are 4 SGMII PHYs
  47  * housed.
  48  */
  49
  50 static int xqsgii_riser_phy_addr[] = {
  51         XQSGMII_CARD_PHY1_PORT0_ADDR,
  52         XQSGMII_CARD_PHY2_PORT0_ADDR,
  53         XQSGMII_CARD_PHY3_PORT0_ADDR,
  54         XQSGMII_CARD_PHY4_PORT0_ADDR,
  55         XQSGMII_CARD_PHY3_PORT2_ADDR,
  56         XQSGMII_CARD_PHY1_PORT2_ADDR,
  57         XQSGMII_CARD_PHY4_PORT2_ADDR,
  58         XQSGMII_CARD_PHY2_PORT2_ADDR,
  59 };
  60
  61 static int sgmii_riser_phy_addr[] = {
  62         SGMII_CARD_PORT1_PHY_ADDR,
  63         SGMII_CARD_PORT2_PHY_ADDR,
  64         SGMII_CARD_PORT3_PHY_ADDR,
  65         SGMII_CARD_PORT4_PHY_ADDR,
  66 };
  67
  68 /* Slot2 does not have EMI connections */
  69 #define EMI_NONE        0xFF
  70 #define EMI1_SLOT1      0
  71 #define EMI1_SLOT2      1
  72 #define EMI1_SLOT3      2
  73 #define EMI1_SLOT4      3
  74 #define EMI1_SLOT5      4
  75 #define EMI1_SLOT6      5
  76 #define EMI2            6
  77 #define SFP_TX          0
  78
  79 static const char * const mdio_names[] = {
  80         "LS2080A_QDS_MDIO0",
  81         "LS2080A_QDS_MDIO1",
  82         "LS2080A_QDS_MDIO2",
  83         "LS2080A_QDS_MDIO3",
  84         "LS2080A_QDS_MDIO4",
  85         "LS2080A_QDS_MDIO5",
  86         DEFAULT_WRIOP_MDIO2_NAME,
  87 };
  88
  89 struct ls2080a_qds_mdio {
  90         u8 muxval;
  91         struct mii_dev *realbus;
  92 };
  93
  94 struct reg_pair {
  95         uint addr;
  96         u8 *val;
  97 };
  98
  99 static void sgmii_configure_repeater(int serdes_port)
 100 {
 101         struct mii_dev *bus;
 102         uint8_t a = 0xf;
 103         int i, j, k, ret;
 104         int dpmac_id = 0, dpmac, mii_bus = 0;
 105         unsigned short value;
 106         char dev[2][20] = {"LS2080A_QDS_MDIO0", "LS2080A_QDS_MDIO3"};
 107         uint8_t i2c_addr[] = {0x58, 0x59, 0x5a, 0x5b, 0x5c, 0x5d, 0x5f, 0x60};
 108
 109         uint8_t ch_a_eq[] = {0x1, 0x2, 0x3, 0x7};
 110         uint8_t ch_a_ctl2[] = {0x81, 0x82, 0x83, 0x84};
 111         uint8_t ch_b_eq[] = {0x1, 0x2, 0x3, 0x7};
 112         uint8_t ch_b_ctl2[] = {0x81, 0x82, 0x83, 0x84};
 113
 114         u8 reg_val[6] = {0x18, 0x38, 0x4, 0x14, 0xb5, 0x20};
 115         struct reg_pair reg_pair[10] = {
 116                         {6, &reg_val[0]}, {4, &reg_val[1]},
 117                         {8, &reg_val[2]}, {0xf, NULL},
 118                         {0x11, NULL}, {0x16, NULL},
 119                         {0x18, NULL}, {0x23, &reg_val[3]},
 120                         {0x2d, &reg_val[4]}, {4, &reg_val[5]},
 121         };
 122
 123         int *riser_phy_addr = &xqsgii_riser_phy_addr[0];
 124 #ifdef CONFIG_DM_I2C
 125         struct udevice *udev;
 126 #endif
 127
 128         /* Set I2c to Slot 1 */
 129 #ifndef CONFIG_DM_I2C
 130         ret = i2c_write(0x77, 0, 0, &a, 1);
 131 #else
 132         ret = i2c_get_chip_for_busnum(0, 0x77, 1, &udev);
 133         if (!ret)
 134                 ret = dm_i2c_write(udev, 0, &a, 1);
 135 #endif
 136         if (ret)
 137                 goto error;
 138
 139         for (dpmac = 0; dpmac < 8; dpmac++) {
 140                 /* Check the PHY status */
 141                 switch (serdes_port) {
 142                 case 1:
 143                         mii_bus = 0;
 144                         dpmac_id = dpmac + 1;
 145                         break;
 146                 case 2:
 147                         mii_bus = 1;
 148                         dpmac_id = dpmac + 9;
 149                         a = 0xb;
 150 #ifndef CONFIG_DM_I2C
 151                         ret = i2c_write(0x76, 0, 0, &a, 1);
 152 #else
 153                         ret = i2c_get_chip_for_busnum(0, 0x76, 1, &udev);
 154                         if (!ret)
 155                                 ret = dm_i2c_write(udev, 0, &a, 1);
 156 #endif
 157                         if (ret)
 158                                 goto error;
 159                         break;
 160                 }
 161
 162                 ret = miiphy_set_current_dev(dev[mii_bus]);
 163                 if (ret > 0)
 164                         goto error;
 165
 166                 bus = mdio_get_current_dev();
 167                 debug("Reading from bus %s\n", bus->name);
 168
 169                 ret = miiphy_write(dev[mii_bus], riser_phy_addr[dpmac], 0x1f,
 170                                    3);
 171                 if (ret > 0)
 172                         goto error;
 173
 174                 mdelay(10);
 175                 ret = miiphy_read(dev[mii_bus], riser_phy_addr[dpmac], 0x11,
 176                                   &value);
 177                 if (ret > 0)
 178                         goto error;
 179
 180                 mdelay(10);
 181
 182                 if ((value & 0xfff) == 0x401) {
 183                         printf("DPMAC %d:PHY is ..... Configured\n", dpmac_id);
 184                         miiphy_write(dev[mii_bus], riser_phy_addr[dpmac],
 185                                      0x1f, 0);
 186                         continue;
 187                 }
 188
 189                 for (i = 0; i < 4; i++) {
 190                         for (j = 0; j < 4; j++) {
 191                                 reg_pair[3].val = &ch_a_eq[i];
 192                                 reg_pair[4].val = &ch_a_ctl2[j];
 193                                 reg_pair[5].val = &ch_b_eq[i];
 194                                 reg_pair[6].val = &ch_b_ctl2[j];
 195
 196                                 for (k = 0; k < 10; k++) {
 197 #ifndef CONFIG_DM_I2C
 198                                         ret = i2c_write(i2c_addr[dpmac],
 199                                                         reg_pair[k].addr,
 200                                                         1, reg_pair[k].val, 1);
 201 #else
 202                                         ret = i2c_get_chip_for_busnum(0,
 203                                                             i2c_addr[dpmac],
 204                                                             1, &udev);
 205                                         if (!ret)
 206                                                 ret = dm_i2c_write(udev,
 207                                                           reg_pair[k].addr,
 208                                                           reg_pair[k].val, 1);
 209 #endif
 210                                         if (ret)
 211                                                 goto error;
 212                                 }
 213
 214                                 mdelay(100);
 215                                 ret = miiphy_read(dev[mii_bus],
 216                                                   riser_phy_addr[dpmac],
 217                                                   0x11, &value);
 218                                 if (ret > 0)
 219                                         goto error;
 220
 221                                 mdelay(100);
 222                                 ret = miiphy_read(dev[mii_bus],
 223                                                   riser_phy_addr[dpmac],
 224                                                   0x11, &value);
 225                                 if (ret > 0)
 226                                         goto error;
 227
 228                                 if ((value & 0xfff) == 0x401) {
 229                                         printf("DPMAC %d :PHY is configured ",
 230                                                dpmac_id);
 231                                         printf("after setting repeater 0x%x\n",
 232                                                value);
 233                                         i = 5;
 234                                         j = 5;
 235                                 } else {
 236                                         printf("DPMAC %d :PHY is failed to ",
 237                                                dpmac_id);
 238                                         printf("configure the repeater 0x%x\n",
 239                                                value);
 240                                 }
 241                         }
 242                 }
 243                 miiphy_write(dev[mii_bus], riser_phy_addr[dpmac], 0x1f, 0);
 244         }
 245 error:
 246         if (ret)
 247                 printf("DPMAC %d ..... FAILED to configure PHY\n", dpmac_id);
 248         return;
 249 }
 250
 251 static void qsgmii_configure_repeater(int dpmac)
 252 {
 253         uint8_t a = 0xf;
 254         int i, j, k;
 255         int i2c_phy_addr = 0;
 256         int phy_addr = 0;
 257         int i2c_addr[] = {0x58, 0x59, 0x5a, 0x5b};
 258
 259         uint8_t ch_a_eq[] = {0x1, 0x2, 0x3, 0x7};
 260         uint8_t ch_a_ctl2[] = {0x81, 0x82, 0x83, 0x84};
 261         uint8_t ch_b_eq[] = {0x1, 0x2, 0x3, 0x7};
 262         uint8_t ch_b_ctl2[] = {0x81, 0x82, 0x83, 0x84};
 263
 264         u8 reg_val[6] = {0x18, 0x38, 0x4, 0x14, 0xb5, 0x20};
 265         struct reg_pair reg_pair[10] = {
 266                 {6, &reg_val[0]}, {4, &reg_val[1]},
 267                 {8, &reg_val[2]}, {0xf, NULL},
 268                 {0x11, NULL}, {0x16, NULL},
 269                 {0x18, NULL}, {0x23, &reg_val[3]},
 270                 {0x2d, &reg_val[4]}, {4, &reg_val[5]},
 271         };
 272
 273         const char *dev = "LS2080A_QDS_MDIO0";
 274         int ret = 0;
 275         unsigned short value;
 276 #ifdef CONFIG_DM_I2C
 277         struct udevice *udev;
 278 #endif
 279
 280         /* Set I2c to Slot 1 */
 281 #ifndef CONFIG_DM_I2C
 282         ret = i2c_write(0x77, 0, 0, &a, 1);
 283 #else
 284         ret = i2c_get_chip_for_busnum(0, 0x77, 1, &udev);
 285         if (!ret)
 286                 ret = dm_i2c_write(udev, 0, &a, 1);
 287 #endif
 288         if (ret)
 289                 goto error;
 290
 291         switch (dpmac) {
 292         case 1:
 293         case 2:
 294         case 3:
 295         case 4:
 296                 i2c_phy_addr = i2c_addr[0];
 297                 phy_addr = 0;
 298                 break;
 299
 300         case 5:
 301         case 6:
 302         case 7:
 303         case 8:
 304                 i2c_phy_addr = i2c_addr[1];
 305                 phy_addr = 4;
 306                 break;
 307
 308         case 9:
 309         case 10:
 310         case 11:
 311         case 12:
 312                 i2c_phy_addr = i2c_addr[2];
 313                 phy_addr = 8;
 314                 break;
 315
 316         case 13:
 317         case 14:
 318         case 15:
 319         case 16:
 320                 i2c_phy_addr = i2c_addr[3];
 321                 phy_addr = 0xc;
 322                 break;
 323         }
 324
 325         /* Check the PHY status */
 326         ret = miiphy_set_current_dev(dev);
 327         ret = miiphy_write(dev, phy_addr, 0x1f, 3);
 328         mdelay(10);
 329         ret = miiphy_read(dev, phy_addr, 0x11, &value);
 330         mdelay(10);
 331         ret = miiphy_read(dev, phy_addr, 0x11, &value);
 332         mdelay(10);
 333         if ((value & 0xf) == 0xf) {
 334                 printf("DPMAC %d :PHY is ..... Configured\n", dpmac);
 335                 return;
 336         }
 337
 338         for (i = 0; i < 4; i++) {
 339                 for (j = 0; j < 4; j++) {
 340                         reg_pair[3].val = &ch_a_eq[i];
 341                         reg_pair[4].val = &ch_a_ctl2[j];
 342                         reg_pair[5].val = &ch_b_eq[i];
 343                         reg_pair[6].val = &ch_b_ctl2[j];
 344
 345                         for (k = 0; k < 10; k++) {
 346 #ifndef CONFIG_DM_I2C
 347                                 ret = i2c_write(i2c_phy_addr,
 348                                                 reg_pair[k].addr,
 349                                                 1, reg_pair[k].val, 1);
 350 #else
 351                                 ret = i2c_get_chip_for_busnum(0,
 352                                                               i2c_phy_addr,
 353                                                               1, &udev);
 354                                 if (!ret)
 355                                         ret = dm_i2c_write(udev,
 356                                                            reg_pair[k].addr,
 357                                                            reg_pair[k].val, 1);
 358 #endif
 359                                 if (ret)
 360                                         goto error;
 361                         }
 362
 363                         mdelay(100);
 364                         ret = miiphy_read(dev, phy_addr, 0x11, &value);
 365                         if (ret > 0)
 366                                 goto error;
 367                         mdelay(1);
 368                         ret = miiphy_read(dev, phy_addr, 0x11, &value);
 369                         if (ret > 0)
 370                                 goto error;
 371                         mdelay(10);
 372                         if ((value & 0xf) == 0xf) {
 373                                 printf("DPMAC %d :PHY is ..... Configured\n",
 374                                        dpmac);
 375                                 return;
 376                         }
 377                 }
 378         }
 379 error:
 380         printf("DPMAC %d :PHY ..... FAILED to configure PHY\n", dpmac);
 381         return;
 382 }
 383
 384 static const char *ls2080a_qds_mdio_name_for_muxval(u8 muxval)
 385 {
 386         return mdio_names[muxval];
 387 }
 388
 389 struct mii_dev *mii_dev_for_muxval(u8 muxval)
 390 {
 391         struct mii_dev *bus;
 392         const char *name = ls2080a_qds_mdio_name_for_muxval(muxval);
 393
 394         if (!name) {
 395                 printf("No bus for muxval %x\n", muxval);
 396                 return NULL;
 397         }
 398
 399         bus = miiphy_get_dev_by_name(name);
 400
 401         if (!bus) {
 402                 printf("No bus by name %s\n", name);
 403                 return NULL;
 404         }
 405
 406         return bus;
 407 }
 408
 409 static void ls2080a_qds_enable_SFP_TX(u8 muxval)
 410 {
 411         u8 brdcfg9;
 412
 413         brdcfg9 = QIXIS_READ(brdcfg[9]);
 414         brdcfg9 &= ~BRDCFG9_SFPTX_MASK;
 415         brdcfg9 |= (muxval << BRDCFG9_SFPTX_SHIFT);
 416         QIXIS_WRITE(brdcfg[9], brdcfg9);
 417 }
 418
 419 static void ls2080a_qds_mux_mdio(u8 muxval)
 420 {
 421         u8 brdcfg4;
 422
 423         if (muxval <= 5) {
 424                 brdcfg4 = QIXIS_READ(brdcfg[4]);
 425                 brdcfg4 &= ~BRDCFG4_EMISEL_MASK;
 426                 brdcfg4 |= (muxval << BRDCFG4_EMISEL_SHIFT);
 427                 QIXIS_WRITE(brdcfg[4], brdcfg4);
 428         }
 429 }
 430
 431 static int ls2080a_qds_mdio_read(struct mii_dev *bus, int addr,
 432                                  int devad, int regnum)
 433 {
 434         struct ls2080a_qds_mdio *priv = bus->priv;
 435
 436         ls2080a_qds_mux_mdio(priv->muxval);
 437
 438         return priv->realbus->read(priv->realbus, addr, devad, regnum);
 439 }
 440
 441 static int ls2080a_qds_mdio_write(struct mii_dev *bus, int addr, int devad,
 442                                   int regnum, u16 value)
 443 {
 444         struct ls2080a_qds_mdio *priv = bus->priv;
 445
 446         ls2080a_qds_mux_mdio(priv->muxval);
 447
 448         return priv->realbus->write(priv->realbus, addr, devad, regnum, value);
 449 }
 450
 451 static int ls2080a_qds_mdio_reset(struct mii_dev *bus)
 452 {
 453         struct ls2080a_qds_mdio *priv = bus->priv;
 454
 455         return priv->realbus->reset(priv->realbus);
 456 }
 457
 458 static int ls2080a_qds_mdio_init(char *realbusname, u8 muxval)
 459 {
 460         struct ls2080a_qds_mdio *pmdio;
 461         struct mii_dev *bus = mdio_alloc();
 462
 463         if (!bus) {
 464                 printf("Failed to allocate ls2080a_qds MDIO bus\n");
 465                 return -1;
 466         }
 467
 468         pmdio = malloc(sizeof(*pmdio));
 469         if (!pmdio) {
 470                 printf("Failed to allocate ls2080a_qds private data\n");
 471                 free(bus);
 472                 return -1;
 473         }
 474
 475         bus->read = ls2080a_qds_mdio_read;
 476         bus->write = ls2080a_qds_mdio_write;
 477         bus->reset = ls2080a_qds_mdio_reset;
 478         strcpy(bus->name, ls2080a_qds_mdio_name_for_muxval(muxval));
 479
 480         pmdio->realbus = miiphy_get_dev_by_name(realbusname);
 481
 482         if (!pmdio->realbus) {
 483                 printf("No bus with name %s\n", realbusname);
 484                 free(bus);
 485                 free(pmdio);
 486                 return -1;
 487         }
 488
 489         pmdio->muxval = muxval;
 490         bus->priv = pmdio;
 491
 492         return mdio_register(bus);
 493 }
 494
 495 /*
 496  * Initialize the dpmac_info array.
 497  *
 498  */
 499 static void initialize_dpmac_to_slot(void)
 500 {
 501         struct ccsr_gur __iomem *gur = (void *)CONFIG_SYS_FSL_GUTS_ADDR;
 502         int serdes1_prtcl = (in_le32(&gur->rcwsr[28]) &
 503                                 FSL_CHASSIS3_RCWSR28_SRDS1_PRTCL_MASK)
 504                 >> FSL_CHASSIS3_RCWSR28_SRDS1_PRTCL_SHIFT;
 505         int serdes2_prtcl = (in_le32(&gur->rcwsr[28]) &
 506                                 FSL_CHASSIS3_RCWSR28_SRDS2_PRTCL_MASK)
 507                 >> FSL_CHASSIS3_RCWSR28_SRDS2_PRTCL_SHIFT;
 508
 509         char *env_hwconfig;
 510         env_hwconfig = env_get("hwconfig");
 511
 512         switch (serdes1_prtcl) {
 513         case 0x07:
 514         case 0x09:
 515         case 0x33:
 516                 printf("qds: WRIOP: Supported SerDes1 Protocol 0x%02x\n",
 517                        serdes1_prtcl);
 518                 lane_to_slot_fsm1[0] = EMI1_SLOT1;
 519                 lane_to_slot_fsm1[1] = EMI1_SLOT1;
 520                 lane_to_slot_fsm1[2] = EMI1_SLOT1;
 521                 lane_to_slot_fsm1[3] = EMI1_SLOT1;
 522                 if (hwconfig_f("xqsgmii", env_hwconfig)) {
 523                         lane_to_slot_fsm1[4] = EMI1_SLOT1;
 524                         lane_to_slot_fsm1[5] = EMI1_SLOT1;
 525                         lane_to_slot_fsm1[6] = EMI1_SLOT1;
 526                         lane_to_slot_fsm1[7] = EMI1_SLOT1;
 527                 } else {
 528                         lane_to_slot_fsm1[4] = EMI1_SLOT2;
 529                         lane_to_slot_fsm1[5] = EMI1_SLOT2;
 530                         lane_to_slot_fsm1[6] = EMI1_SLOT2;
 531                         lane_to_slot_fsm1[7] = EMI1_SLOT2;
 532                 }
 533                 break;
 534
 535         case 0x39:
 536                 printf("qds: WRIOP: Supported SerDes1 Protocol 0x%02x\n",
 537                        serdes1_prtcl);
 538                 if (hwconfig_f("xqsgmii", env_hwconfig)) {
 539                         lane_to_slot_fsm1[0] = EMI1_SLOT3;
 540                         lane_to_slot_fsm1[1] = EMI1_SLOT3;
 541                         lane_to_slot_fsm1[2] = EMI1_SLOT3;
 542                         lane_to_slot_fsm1[3] = EMI_NONE;
 543                 } else {
 544                         lane_to_slot_fsm1[0] = EMI_NONE;
 545                         lane_to_slot_fsm1[1] = EMI_NONE;
 546                         lane_to_slot_fsm1[2] = EMI_NONE;
 547                         lane_to_slot_fsm1[3] = EMI_NONE;
 548                 }
 549                 lane_to_slot_fsm1[4] = EMI1_SLOT3;
 550                 lane_to_slot_fsm1[5] = EMI1_SLOT3;
 551                 lane_to_slot_fsm1[6] = EMI1_SLOT3;
 552                 lane_to_slot_fsm1[7] = EMI_NONE;
 553                 break;
 554
 555         case 0x4D:
 556                 printf("qds: WRIOP: Supported SerDes1 Protocol 0x%02x\n",
 557                        serdes1_prtcl);
 558                 if (hwconfig_f("xqsgmii", env_hwconfig)) {
 559                         lane_to_slot_fsm1[0] = EMI1_SLOT3;
 560                         lane_to_slot_fsm1[1] = EMI1_SLOT3;
 561                         lane_to_slot_fsm1[2] = EMI_NONE;
 562                         lane_to_slot_fsm1[3] = EMI_NONE;
 563                 } else {
 564                         lane_to_slot_fsm1[0] = EMI_NONE;
 565                         lane_to_slot_fsm1[1] = EMI_NONE;
 566                         lane_to_slot_fsm1[2] = EMI_NONE;
 567                         lane_to_slot_fsm1[3] = EMI_NONE;
 568                 }
 569                 lane_to_slot_fsm1[4] = EMI1_SLOT3;
 570                 lane_to_slot_fsm1[5] = EMI1_SLOT3;
 571                 lane_to_slot_fsm1[6] = EMI_NONE;
 572                 lane_to_slot_fsm1[7] = EMI_NONE;
 573                 break;
 574
 575         case 0x2A:
 576         case 0x4B:
 577         case 0x4C:
 578                 printf("qds: WRIOP: Supported SerDes1 Protocol 0x%02x\n",
 579                        serdes1_prtcl);
 580                 break;
 581         default:
 582                 printf("%s qds: WRIOP: Unsupported SerDes1 Protocol 0x%02x\n",
 583                        __func__, serdes1_prtcl);
 584                 break;
 585         }
 586
 587         switch (serdes2_prtcl) {
 588         case 0x07:
 589         case 0x08:
 590         case 0x09:
 591         case 0x49:
 592                 printf("qds: WRIOP: Supported SerDes2 Protocol 0x%02x\n",
 593                        serdes2_prtcl);
 594                 lane_to_slot_fsm2[0] = EMI1_SLOT4;
 595                 lane_to_slot_fsm2[1] = EMI1_SLOT4;
 596                 lane_to_slot_fsm2[2] = EMI1_SLOT4;
 597                 lane_to_slot_fsm2[3] = EMI1_SLOT4;
 598
 599                 if (hwconfig_f("xqsgmii", env_hwconfig)) {
 600                         lane_to_slot_fsm2[4] = EMI1_SLOT4;
 601                         lane_to_slot_fsm2[5] = EMI1_SLOT4;
 602                         lane_to_slot_fsm2[6] = EMI1_SLOT4;
 603                         lane_to_slot_fsm2[7] = EMI1_SLOT4;
 604                 } else {
 605                         /* No MDIO physical connection */
 606                         lane_to_slot_fsm2[4] = EMI1_SLOT6;
 607                         lane_to_slot_fsm2[5] = EMI1_SLOT6;
 608                         lane_to_slot_fsm2[6] = EMI1_SLOT6;
 609                         lane_to_slot_fsm2[7] = EMI1_SLOT6;
 610                 }
 611                 break;
 612
 613         case 0x47:
 614                 printf("qds: WRIOP: Supported SerDes2 Protocol 0x%02x\n",
 615                        serdes2_prtcl);
 616                 lane_to_slot_fsm2[0] = EMI_NONE;
 617                 lane_to_slot_fsm2[1] = EMI1_SLOT5;
 618                 lane_to_slot_fsm2[2] = EMI1_SLOT5;
 619                 lane_to_slot_fsm2[3] = EMI1_SLOT5;
 620
 621                 if (hwconfig_f("xqsgmii", env_hwconfig)) {
 622                         lane_to_slot_fsm2[4] = EMI_NONE;
 623                         lane_to_slot_fsm2[5] = EMI1_SLOT5;
 624                         lane_to_slot_fsm2[6] = EMI1_SLOT5;
 625                         lane_to_slot_fsm2[7] = EMI1_SLOT5;
 626                 }
 627                 break;
 628
 629         case 0x57:
 630                 printf("qds: WRIOP: Supported SerDes2 Protocol 0x%02x\n",
 631                        serdes2_prtcl);
 632                 if (hwconfig_f("xqsgmii", env_hwconfig)) {
 633                         lane_to_slot_fsm2[0] = EMI_NONE;
 634                         lane_to_slot_fsm2[1] = EMI_NONE;
 635                         lane_to_slot_fsm2[2] = EMI_NONE;
 636                         lane_to_slot_fsm2[3] = EMI_NONE;
 637                 }
 638                 lane_to_slot_fsm2[4] = EMI_NONE;
 639                 lane_to_slot_fsm2[5] = EMI_NONE;
 640                 lane_to_slot_fsm2[6] = EMI1_SLOT5;
 641                 lane_to_slot_fsm2[7] = EMI1_SLOT5;
 642                 break;
 643
 644         default:
 645                 printf(" %s qds: WRIOP: Unsupported SerDes2 Protocol 0x%02x\n",
 646                        __func__ , serdes2_prtcl);
 647                 break;
 648         }
 649 }
 650
 651 void ls2080a_handle_phy_interface_sgmii(int dpmac_id)
 652 {
 653         int lane, slot;
 654         struct mii_dev *bus;
 655         struct ccsr_gur __iomem *gur = (void *)CONFIG_SYS_FSL_GUTS_ADDR;
 656         int serdes1_prtcl = (in_le32(&gur->rcwsr[28]) &
 657                                 FSL_CHASSIS3_RCWSR28_SRDS1_PRTCL_MASK)
 658                 >> FSL_CHASSIS3_RCWSR28_SRDS1_PRTCL_SHIFT;
 659         int serdes2_prtcl = (in_le32(&gur->rcwsr[28]) &
 660                                 FSL_CHASSIS3_RCWSR28_SRDS2_PRTCL_MASK)
 661                 >> FSL_CHASSIS3_RCWSR28_SRDS2_PRTCL_SHIFT;
 662
 663         int *riser_phy_addr;
 664         char *env_hwconfig = env_get("hwconfig");
 665
 666         if (hwconfig_f("xqsgmii", env_hwconfig))
 667                 riser_phy_addr = &xqsgii_riser_phy_addr[0];
 668         else
 669                 riser_phy_addr = &sgmii_riser_phy_addr[0];
 670
 671         if (dpmac_id > WRIOP1_DPMAC9)
 672                 goto serdes2;
 673
 674         switch (serdes1_prtcl) {
 675         case 0x07:
 676         case 0x39:
 677         case 0x4D:
 678                 lane = serdes_get_first_lane(FSL_SRDS_1, SGMII1 + dpmac_id - 1);
 679
 680                 slot = lane_to_slot_fsm1[lane];
 681
 682                 switch (++slot) {
 683                 case 1:
 684                         /* Slot housing a SGMII riser card? */
 685                         wriop_set_phy_address(dpmac_id, 0,
 686                                               riser_phy_addr[dpmac_id - 1]);
 687                         dpmac_info[dpmac_id].board_mux = EMI1_SLOT1;
 688                         bus = mii_dev_for_muxval(EMI1_SLOT1);
 689                         wriop_set_mdio(dpmac_id, bus);
 690                         break;
 691                 case 2:
 692                         /* Slot housing a SGMII riser card? */
 693                         wriop_set_phy_address(dpmac_id, 0,
 694                                               riser_phy_addr[dpmac_id - 1]);
 695                         dpmac_info[dpmac_id].board_mux = EMI1_SLOT2;
 696                         bus = mii_dev_for_muxval(EMI1_SLOT2);
 697                         wriop_set_mdio(dpmac_id, bus);
 698                         break;
 699                 case 3:
 700                         if (slot == EMI_NONE)
 701                                 return;
 702                         if (serdes1_prtcl == 0x39) {
 703                                 wriop_set_phy_address(dpmac_id, 0,
 704                                         riser_phy_addr[dpmac_id - 2]);
 705                                 if (dpmac_id >= 6 && hwconfig_f("xqsgmii",
 706                                                                 env_hwconfig))
 707                                         wriop_set_phy_address(dpmac_id, 0,
 708                                                 riser_phy_addr[dpmac_id - 3]);
 709                         } else {
 710                                 wriop_set_phy_address(dpmac_id, 0,
 711                                         riser_phy_addr[dpmac_id - 2]);
 712                                 if (dpmac_id >= 7 && hwconfig_f("xqsgmii",
 713                                                                 env_hwconfig))
 714                                         wriop_set_phy_address(dpmac_id, 0,
 715                                                 riser_phy_addr[dpmac_id - 3]);
 716                         }
 717                         dpmac_info[dpmac_id].board_mux = EMI1_SLOT3;
 718                         bus = mii_dev_for_muxval(EMI1_SLOT3);
 719                         wriop_set_mdio(dpmac_id, bus);
 720                         break;
 721                 case 4:
 722                         break;
 723                 case 5:
 724                         break;
 725                 case 6:
 726                         break;
 727                 }
 728         break;
 729         default:
 730                 printf("%s qds: WRIOP: Unsupported SerDes1 Protocol 0x%02x\n",
 731                        __func__ , serdes1_prtcl);
 732         break;
 733         }
 734
 735 serdes2:
 736         switch (serdes2_prtcl) {
 737         case 0x07:
 738         case 0x08:
 739         case 0x49:
 740         case 0x47:
 741         case 0x57:
 742                 lane = serdes_get_first_lane(FSL_SRDS_2, SGMII9 +
 743                                                         (dpmac_id - 9));
 744                 slot = lane_to_slot_fsm2[lane];
 745
 746                 switch (++slot) {
 747                 case 1:
 748                         break;
 749                 case 3:
 750                         break;
 751                 case 4:
 752                         /* Slot housing a SGMII riser card? */
 753                         wriop_set_phy_address(dpmac_id, 0,
 754                                               riser_phy_addr[dpmac_id - 9]);
 755                         dpmac_info[dpmac_id].board_mux = EMI1_SLOT4;
 756                         bus = mii_dev_for_muxval(EMI1_SLOT4);
 757                         wriop_set_mdio(dpmac_id, bus);
 758                 break;
 759                 case 5:
 760                         if (slot == EMI_NONE)
 761                                 return;
 762                         if (serdes2_prtcl == 0x47) {
 763                                 wriop_set_phy_address(dpmac_id, 0,
 764                                               riser_phy_addr[dpmac_id - 10]);
 765                                 if (dpmac_id >= 14 && hwconfig_f("xqsgmii",
 766                                                                  env_hwconfig))
 767                                         wriop_set_phy_address(dpmac_id, 0,
 768                                                 riser_phy_addr[dpmac_id - 11]);
 769                         } else {
 770                                 wriop_set_phy_address(dpmac_id, 0,
 771                                         riser_phy_addr[dpmac_id - 11]);
 772                         }
 773                         dpmac_info[dpmac_id].board_mux = EMI1_SLOT5;
 774                         bus = mii_dev_for_muxval(EMI1_SLOT5);
 775                         wriop_set_mdio(dpmac_id, bus);
 776                         break;
 777                 case 6:
 778                         /* Slot housing a SGMII riser card? */
 779                         wriop_set_phy_address(dpmac_id, 0,
 780                                               riser_phy_addr[dpmac_id - 13]);
 781                         dpmac_info[dpmac_id].board_mux = EMI1_SLOT6;
 782                         bus = mii_dev_for_muxval(EMI1_SLOT6);
 783                         wriop_set_mdio(dpmac_id, bus);
 784                 break;
 785         }
 786         break;
 787         default:
 788                 printf("%s qds: WRIOP: Unsupported SerDes2 Protocol 0x%02x\n",
 789                        __func__, serdes2_prtcl);
 790         break;
 791         }
 792 }
 793
 794 void ls2080a_handle_phy_interface_qsgmii(int dpmac_id)
 795 {
 796         int lane = 0, slot;
 797         struct mii_dev *bus;
 798         struct ccsr_gur __iomem *gur = (void *)CONFIG_SYS_FSL_GUTS_ADDR;
 799         int serdes1_prtcl = (in_le32(&gur->rcwsr[28]) &
 800                                 FSL_CHASSIS3_RCWSR28_SRDS1_PRTCL_MASK)
 801                 >> FSL_CHASSIS3_RCWSR28_SRDS1_PRTCL_SHIFT;
 802
 803         switch (serdes1_prtcl) {
 804         case 0x33:
 805                 switch (dpmac_id) {
 806                 case 1:
 807                 case 2:
 808                 case 3:
 809                 case 4:
 810                         lane = serdes_get_first_lane(FSL_SRDS_1, QSGMII_A);
 811                 break;
 812                 case 5:
 813                 case 6:
 814                 case 7:
 815                 case 8:
 816                         lane = serdes_get_first_lane(FSL_SRDS_1, QSGMII_B);
 817                 break;
 818                 case 9:
 819                 case 10:
 820                 case 11:
 821                 case 12:
 822                         lane = serdes_get_first_lane(FSL_SRDS_1, QSGMII_C);
 823                 break;
 824                 case 13:
 825                 case 14:
 826                 case 15:
 827                 case 16:
 828                         lane = serdes_get_first_lane(FSL_SRDS_1, QSGMII_D);
 829                 break;
 830         }
 831
 832                 slot = lane_to_slot_fsm1[lane];
 833
 834                 switch (++slot) {
 835                 case 1:
 836                         /* Slot housing a QSGMII riser card? */
 837                         wriop_set_phy_address(dpmac_id, 0, dpmac_id - 1);
 838                         dpmac_info[dpmac_id].board_mux = EMI1_SLOT1;
 839                         bus = mii_dev_for_muxval(EMI1_SLOT1);
 840                         wriop_set_mdio(dpmac_id, bus);
 841                         break;
 842                 case 3:
 843                         break;
 844                 case 4:
 845                         break;
 846                 case 5:
 847                 break;
 848                 case 6:
 849                         break;
 850         }
 851         break;
 852         default:
 853                 printf("qds: WRIOP: Unsupported SerDes Protocol 0x%02x\n",
 854                        serdes1_prtcl);
 855         break;
 856         }
 857
 858         qsgmii_configure_repeater(dpmac_id);
 859 }
 860
 861 void ls2080a_handle_phy_interface_xsgmii(int i)
 862 {
 863         struct ccsr_gur __iomem *gur = (void *)CONFIG_SYS_FSL_GUTS_ADDR;
 864         int serdes1_prtcl = (in_le32(&gur->rcwsr[28]) &
 865                                 FSL_CHASSIS3_RCWSR28_SRDS1_PRTCL_MASK)
 866                 >> FSL_CHASSIS3_RCWSR28_SRDS1_PRTCL_SHIFT;
 867
 868         switch (serdes1_prtcl) {
 869         case 0x2A:
 870         case 0x4B:
 871         case 0x4C:
 872                 /*
 873                  * XFI does not need a PHY to work, but to avoid U-Boot use
 874                  * default PHY address which is zero to a MAC when it found
 875                  * a MAC has no PHY address, we give a PHY address to XFI
 876                  * MAC, and should not use a real XAUI PHY address, since
 877                  * MDIO can access it successfully, and then MDIO thinks
 878                  * the XAUI card is used for the XFI MAC, which will cause
 879                  * error.
 880                  */
 881                 wriop_set_phy_address(i, 0, i + 4);
 882                 ls2080a_qds_enable_SFP_TX(SFP_TX);
 883
 884                 break;
 885         default:
 886                 printf("qds: WRIOP: Unsupported SerDes Protocol 0x%02x\n",
 887                        serdes1_prtcl);
 888                 break;
 889         }
 890 }
 891 #endif
 892
 893 int board_eth_init(bd_t *bis)
 894 {
 895         int error;
 896 #if defined(CONFIG_FSL_MC_ENET) && !defined(CONFIG_SPL_BUILD)
 897         struct ccsr_gur __iomem *gur = (void *)CONFIG_SYS_FSL_GUTS_ADDR;
 898         int serdes1_prtcl = (in_le32(&gur->rcwsr[28]) &
 899                                 FSL_CHASSIS3_RCWSR28_SRDS1_PRTCL_MASK)
 900                 >> FSL_CHASSIS3_RCWSR28_SRDS1_PRTCL_SHIFT;
 901         int serdes2_prtcl = (in_le32(&gur->rcwsr[28]) &
 902                                 FSL_CHASSIS3_RCWSR28_SRDS2_PRTCL_MASK)
 903                 >> FSL_CHASSIS3_RCWSR28_SRDS2_PRTCL_SHIFT;
 904
 905         struct memac_mdio_info *memac_mdio0_info;
 906         struct memac_mdio_info *memac_mdio1_info;
 907         unsigned int i;
 908         char *env_hwconfig;
 909
 910         env_hwconfig = env_get("hwconfig");
 911
 912         initialize_dpmac_to_slot();
 913
 914         memac_mdio0_info = (struct memac_mdio_info *)malloc(
 915                                         sizeof(struct memac_mdio_info));
 916         memac_mdio0_info->regs =
 917                 (struct memac_mdio_controller *)
 918                                         CONFIG_SYS_FSL_WRIOP1_MDIO1;
 919         memac_mdio0_info->name = DEFAULT_WRIOP_MDIO1_NAME;
 920
 921         /* Register the real MDIO1 bus */
 922         fm_memac_mdio_init(bis, memac_mdio0_info);
 923
 924         memac_mdio1_info = (struct memac_mdio_info *)malloc(
 925                                         sizeof(struct memac_mdio_info));
 926         memac_mdio1_info->regs =
 927                 (struct memac_mdio_controller *)
 928                                         CONFIG_SYS_FSL_WRIOP1_MDIO2;
 929         memac_mdio1_info->name = DEFAULT_WRIOP_MDIO2_NAME;
 930
 931         /* Register the real MDIO2 bus */
 932         fm_memac_mdio_init(bis, memac_mdio1_info);
 933
 934         /* Register the muxing front-ends to the MDIO buses */
 935         ls2080a_qds_mdio_init(DEFAULT_WRIOP_MDIO1_NAME, EMI1_SLOT1);
 936         ls2080a_qds_mdio_init(DEFAULT_WRIOP_MDIO1_NAME, EMI1_SLOT2);
 937         ls2080a_qds_mdio_init(DEFAULT_WRIOP_MDIO1_NAME, EMI1_SLOT3);
 938         ls2080a_qds_mdio_init(DEFAULT_WRIOP_MDIO1_NAME, EMI1_SLOT4);
 939         ls2080a_qds_mdio_init(DEFAULT_WRIOP_MDIO1_NAME, EMI1_SLOT5);
 940         ls2080a_qds_mdio_init(DEFAULT_WRIOP_MDIO1_NAME, EMI1_SLOT6);
 941
 942         ls2080a_qds_mdio_init(DEFAULT_WRIOP_MDIO2_NAME, EMI2);
 943
 944         for (i = WRIOP1_DPMAC1; i < NUM_WRIOP_PORTS; i++) {
 945                 switch (wriop_get_enet_if(i)) {
 946                 case PHY_INTERFACE_MODE_QSGMII:
 947                         ls2080a_handle_phy_interface_qsgmii(i);
 948                         break;
 949                 case PHY_INTERFACE_MODE_SGMII:
 950                         ls2080a_handle_phy_interface_sgmii(i);
 951                         break;
 952                 case PHY_INTERFACE_MODE_XGMII:
 953                         ls2080a_handle_phy_interface_xsgmii(i);
 954                         break;
 955                 default:
 956                         break;
 957
 958                 if (i == 16)
 959                         i = NUM_WRIOP_PORTS;
 960                 }
 961         }
 962
 963         error = cpu_eth_init(bis);
 964
 965         if (hwconfig_f("xqsgmii", env_hwconfig)) {
 966                 if (serdes1_prtcl == 0x7)
 967                         sgmii_configure_repeater(1);
 968                 if (serdes2_prtcl == 0x7 || serdes2_prtcl == 0x8 ||
 969                     serdes2_prtcl == 0x49)
 970                         sgmii_configure_repeater(2);
 971         }
 972 #endif
 973         error = pci_eth_init(bis);
 974         return error;
 975 }
 976
 977 #if defined(CONFIG_RESET_PHY_R)
 978 void reset_phy(void)
 979 {
 980         mc_env_boot();
 981 }
 982 #endif /* CONFIG_RESET_PHY_R */