1 // SPDX-License-Identifier: GPL-2.0+
3 * Copyright 2015 Freescale Semiconductor, Inc.
11 #include <asm/arch/fsl_serdes.h>
18 #include <fsl-mc/fsl_mc.h>
19 #include <fsl-mc/ldpaa_wriop.h>
21 #include "../common/qixis.h"
23 #include "ls2080aqds_qixis.h"
25 #define MC_BOOT_ENV_VAR "mcinitcmd"
27 #if defined(CONFIG_FSL_MC_ENET) && !defined(CONFIG_SPL_BUILD)
28 /* - In LS2080A there are only 16 SERDES lanes, spread across 2 SERDES banks.
29 * Bank 1 -> Lanes A, B, C, D, E, F, G, H
30 * Bank 2 -> Lanes A,B, C, D, E, F, G, H
33 /* Mapping of 16 SERDES lanes to LS2080A QDS board slots. A value of '0' here
34 * means that the mapping must be determined dynamically, or that the lane
35 * maps to something other than a board slot.
38 static u8 lane_to_slot_fsm1[] = {
39 0, 0, 0, 0, 0, 0, 0, 0
42 static u8 lane_to_slot_fsm2[] = {
43 0, 0, 0, 0, 0, 0, 0, 0
46 /* On the Vitesse VSC8234XHG SGMII riser card there are 4 SGMII PHYs
50 static int xqsgii_riser_phy_addr[] = {
51 XQSGMII_CARD_PHY1_PORT0_ADDR,
52 XQSGMII_CARD_PHY2_PORT0_ADDR,
53 XQSGMII_CARD_PHY3_PORT0_ADDR,
54 XQSGMII_CARD_PHY4_PORT0_ADDR,
55 XQSGMII_CARD_PHY3_PORT2_ADDR,
56 XQSGMII_CARD_PHY1_PORT2_ADDR,
57 XQSGMII_CARD_PHY4_PORT2_ADDR,
58 XQSGMII_CARD_PHY2_PORT2_ADDR,
61 static int sgmii_riser_phy_addr[] = {
62 SGMII_CARD_PORT1_PHY_ADDR,
63 SGMII_CARD_PORT2_PHY_ADDR,
64 SGMII_CARD_PORT3_PHY_ADDR,
65 SGMII_CARD_PORT4_PHY_ADDR,
68 /* Slot2 does not have EMI connections */
79 static const char * const mdio_names[] = {
86 DEFAULT_WRIOP_MDIO2_NAME,
89 struct ls2080a_qds_mdio {
91 struct mii_dev *realbus;
99 static void sgmii_configure_repeater(int serdes_port)
104 int dpmac_id = 0, dpmac, mii_bus = 0;
105 unsigned short value;
106 char dev[2][20] = {"LS2080A_QDS_MDIO0", "LS2080A_QDS_MDIO3"};
107 uint8_t i2c_addr[] = {0x58, 0x59, 0x5a, 0x5b, 0x5c, 0x5d, 0x5f, 0x60};
109 uint8_t ch_a_eq[] = {0x1, 0x2, 0x3, 0x7};
110 uint8_t ch_a_ctl2[] = {0x81, 0x82, 0x83, 0x84};
111 uint8_t ch_b_eq[] = {0x1, 0x2, 0x3, 0x7};
112 uint8_t ch_b_ctl2[] = {0x81, 0x82, 0x83, 0x84};
114 u8 reg_val[6] = {0x18, 0x38, 0x4, 0x14, 0xb5, 0x20};
115 struct reg_pair reg_pair[10] = {
116 {6, ®_val[0]}, {4, ®_val[1]},
117 {8, ®_val[2]}, {0xf, NULL},
118 {0x11, NULL}, {0x16, NULL},
119 {0x18, NULL}, {0x23, ®_val[3]},
120 {0x2d, ®_val[4]}, {4, ®_val[5]},
123 int *riser_phy_addr = &xqsgii_riser_phy_addr[0];
125 struct udevice *udev;
128 /* Set I2c to Slot 1 */
129 #ifndef CONFIG_DM_I2C
130 ret = i2c_write(0x77, 0, 0, &a, 1);
132 ret = i2c_get_chip_for_busnum(0, 0x77, 1, &udev);
134 ret = dm_i2c_write(udev, 0, &a, 1);
139 for (dpmac = 0; dpmac < 8; dpmac++) {
140 /* Check the PHY status */
141 switch (serdes_port) {
144 dpmac_id = dpmac + 1;
148 dpmac_id = dpmac + 9;
150 #ifndef CONFIG_DM_I2C
151 ret = i2c_write(0x76, 0, 0, &a, 1);
153 ret = i2c_get_chip_for_busnum(0, 0x76, 1, &udev);
155 ret = dm_i2c_write(udev, 0, &a, 1);
162 ret = miiphy_set_current_dev(dev[mii_bus]);
166 bus = mdio_get_current_dev();
167 debug("Reading from bus %s\n", bus->name);
169 ret = miiphy_write(dev[mii_bus], riser_phy_addr[dpmac], 0x1f,
175 ret = miiphy_read(dev[mii_bus], riser_phy_addr[dpmac], 0x11,
182 if ((value & 0xfff) == 0x401) {
183 printf("DPMAC %d:PHY is ..... Configured\n", dpmac_id);
184 miiphy_write(dev[mii_bus], riser_phy_addr[dpmac],
189 for (i = 0; i < 4; i++) {
190 for (j = 0; j < 4; j++) {
191 reg_pair[3].val = &ch_a_eq[i];
192 reg_pair[4].val = &ch_a_ctl2[j];
193 reg_pair[5].val = &ch_b_eq[i];
194 reg_pair[6].val = &ch_b_ctl2[j];
196 for (k = 0; k < 10; k++) {
197 #ifndef CONFIG_DM_I2C
198 ret = i2c_write(i2c_addr[dpmac],
200 1, reg_pair[k].val, 1);
202 ret = i2c_get_chip_for_busnum(0,
206 ret = dm_i2c_write(udev,
215 ret = miiphy_read(dev[mii_bus],
216 riser_phy_addr[dpmac],
222 ret = miiphy_read(dev[mii_bus],
223 riser_phy_addr[dpmac],
228 if ((value & 0xfff) == 0x401) {
229 printf("DPMAC %d :PHY is configured ",
231 printf("after setting repeater 0x%x\n",
236 printf("DPMAC %d :PHY is failed to ",
238 printf("configure the repeater 0x%x\n",
243 miiphy_write(dev[mii_bus], riser_phy_addr[dpmac], 0x1f, 0);
247 printf("DPMAC %d ..... FAILED to configure PHY\n", dpmac_id);
251 static void qsgmii_configure_repeater(int dpmac)
255 int i2c_phy_addr = 0;
257 int i2c_addr[] = {0x58, 0x59, 0x5a, 0x5b};
259 uint8_t ch_a_eq[] = {0x1, 0x2, 0x3, 0x7};
260 uint8_t ch_a_ctl2[] = {0x81, 0x82, 0x83, 0x84};
261 uint8_t ch_b_eq[] = {0x1, 0x2, 0x3, 0x7};
262 uint8_t ch_b_ctl2[] = {0x81, 0x82, 0x83, 0x84};
264 u8 reg_val[6] = {0x18, 0x38, 0x4, 0x14, 0xb5, 0x20};
265 struct reg_pair reg_pair[10] = {
266 {6, ®_val[0]}, {4, ®_val[1]},
267 {8, ®_val[2]}, {0xf, NULL},
268 {0x11, NULL}, {0x16, NULL},
269 {0x18, NULL}, {0x23, ®_val[3]},
270 {0x2d, ®_val[4]}, {4, ®_val[5]},
273 const char *dev = "LS2080A_QDS_MDIO0";
275 unsigned short value;
277 struct udevice *udev;
280 /* Set I2c to Slot 1 */
281 #ifndef CONFIG_DM_I2C
282 ret = i2c_write(0x77, 0, 0, &a, 1);
284 ret = i2c_get_chip_for_busnum(0, 0x77, 1, &udev);
286 ret = dm_i2c_write(udev, 0, &a, 1);
296 i2c_phy_addr = i2c_addr[0];
304 i2c_phy_addr = i2c_addr[1];
312 i2c_phy_addr = i2c_addr[2];
320 i2c_phy_addr = i2c_addr[3];
325 /* Check the PHY status */
326 ret = miiphy_set_current_dev(dev);
327 ret = miiphy_write(dev, phy_addr, 0x1f, 3);
329 ret = miiphy_read(dev, phy_addr, 0x11, &value);
331 ret = miiphy_read(dev, phy_addr, 0x11, &value);
333 if ((value & 0xf) == 0xf) {
334 printf("DPMAC %d :PHY is ..... Configured\n", dpmac);
338 for (i = 0; i < 4; i++) {
339 for (j = 0; j < 4; j++) {
340 reg_pair[3].val = &ch_a_eq[i];
341 reg_pair[4].val = &ch_a_ctl2[j];
342 reg_pair[5].val = &ch_b_eq[i];
343 reg_pair[6].val = &ch_b_ctl2[j];
345 for (k = 0; k < 10; k++) {
346 #ifndef CONFIG_DM_I2C
347 ret = i2c_write(i2c_phy_addr,
349 1, reg_pair[k].val, 1);
351 ret = i2c_get_chip_for_busnum(0,
355 ret = dm_i2c_write(udev,
364 ret = miiphy_read(dev, phy_addr, 0x11, &value);
368 ret = miiphy_read(dev, phy_addr, 0x11, &value);
372 if ((value & 0xf) == 0xf) {
373 printf("DPMAC %d :PHY is ..... Configured\n",
380 printf("DPMAC %d :PHY ..... FAILED to configure PHY\n", dpmac);
384 static const char *ls2080a_qds_mdio_name_for_muxval(u8 muxval)
386 return mdio_names[muxval];
389 struct mii_dev *mii_dev_for_muxval(u8 muxval)
392 const char *name = ls2080a_qds_mdio_name_for_muxval(muxval);
395 printf("No bus for muxval %x\n", muxval);
399 bus = miiphy_get_dev_by_name(name);
402 printf("No bus by name %s\n", name);
409 static void ls2080a_qds_enable_SFP_TX(u8 muxval)
413 brdcfg9 = QIXIS_READ(brdcfg[9]);
414 brdcfg9 &= ~BRDCFG9_SFPTX_MASK;
415 brdcfg9 |= (muxval << BRDCFG9_SFPTX_SHIFT);
416 QIXIS_WRITE(brdcfg[9], brdcfg9);
419 static void ls2080a_qds_mux_mdio(u8 muxval)
424 brdcfg4 = QIXIS_READ(brdcfg[4]);
425 brdcfg4 &= ~BRDCFG4_EMISEL_MASK;
426 brdcfg4 |= (muxval << BRDCFG4_EMISEL_SHIFT);
427 QIXIS_WRITE(brdcfg[4], brdcfg4);
431 static int ls2080a_qds_mdio_read(struct mii_dev *bus, int addr,
432 int devad, int regnum)
434 struct ls2080a_qds_mdio *priv = bus->priv;
436 ls2080a_qds_mux_mdio(priv->muxval);
438 return priv->realbus->read(priv->realbus, addr, devad, regnum);
441 static int ls2080a_qds_mdio_write(struct mii_dev *bus, int addr, int devad,
442 int regnum, u16 value)
444 struct ls2080a_qds_mdio *priv = bus->priv;
446 ls2080a_qds_mux_mdio(priv->muxval);
448 return priv->realbus->write(priv->realbus, addr, devad, regnum, value);
451 static int ls2080a_qds_mdio_reset(struct mii_dev *bus)
453 struct ls2080a_qds_mdio *priv = bus->priv;
455 return priv->realbus->reset(priv->realbus);
458 static int ls2080a_qds_mdio_init(char *realbusname, u8 muxval)
460 struct ls2080a_qds_mdio *pmdio;
461 struct mii_dev *bus = mdio_alloc();
464 printf("Failed to allocate ls2080a_qds MDIO bus\n");
468 pmdio = malloc(sizeof(*pmdio));
470 printf("Failed to allocate ls2080a_qds private data\n");
475 bus->read = ls2080a_qds_mdio_read;
476 bus->write = ls2080a_qds_mdio_write;
477 bus->reset = ls2080a_qds_mdio_reset;
478 strcpy(bus->name, ls2080a_qds_mdio_name_for_muxval(muxval));
480 pmdio->realbus = miiphy_get_dev_by_name(realbusname);
482 if (!pmdio->realbus) {
483 printf("No bus with name %s\n", realbusname);
489 pmdio->muxval = muxval;
492 return mdio_register(bus);
496 * Initialize the dpmac_info array.
499 static void initialize_dpmac_to_slot(void)
501 struct ccsr_gur __iomem *gur = (void *)CONFIG_SYS_FSL_GUTS_ADDR;
502 int serdes1_prtcl = (in_le32(&gur->rcwsr[28]) &
503 FSL_CHASSIS3_RCWSR28_SRDS1_PRTCL_MASK)
504 >> FSL_CHASSIS3_RCWSR28_SRDS1_PRTCL_SHIFT;
505 int serdes2_prtcl = (in_le32(&gur->rcwsr[28]) &
506 FSL_CHASSIS3_RCWSR28_SRDS2_PRTCL_MASK)
507 >> FSL_CHASSIS3_RCWSR28_SRDS2_PRTCL_SHIFT;
510 env_hwconfig = env_get("hwconfig");
512 switch (serdes1_prtcl) {
516 printf("qds: WRIOP: Supported SerDes1 Protocol 0x%02x\n",
518 lane_to_slot_fsm1[0] = EMI1_SLOT1;
519 lane_to_slot_fsm1[1] = EMI1_SLOT1;
520 lane_to_slot_fsm1[2] = EMI1_SLOT1;
521 lane_to_slot_fsm1[3] = EMI1_SLOT1;
522 if (hwconfig_f("xqsgmii", env_hwconfig)) {
523 lane_to_slot_fsm1[4] = EMI1_SLOT1;
524 lane_to_slot_fsm1[5] = EMI1_SLOT1;
525 lane_to_slot_fsm1[6] = EMI1_SLOT1;
526 lane_to_slot_fsm1[7] = EMI1_SLOT1;
528 lane_to_slot_fsm1[4] = EMI1_SLOT2;
529 lane_to_slot_fsm1[5] = EMI1_SLOT2;
530 lane_to_slot_fsm1[6] = EMI1_SLOT2;
531 lane_to_slot_fsm1[7] = EMI1_SLOT2;
536 printf("qds: WRIOP: Supported SerDes1 Protocol 0x%02x\n",
538 if (hwconfig_f("xqsgmii", env_hwconfig)) {
539 lane_to_slot_fsm1[0] = EMI1_SLOT3;
540 lane_to_slot_fsm1[1] = EMI1_SLOT3;
541 lane_to_slot_fsm1[2] = EMI1_SLOT3;
542 lane_to_slot_fsm1[3] = EMI_NONE;
544 lane_to_slot_fsm1[0] = EMI_NONE;
545 lane_to_slot_fsm1[1] = EMI_NONE;
546 lane_to_slot_fsm1[2] = EMI_NONE;
547 lane_to_slot_fsm1[3] = EMI_NONE;
549 lane_to_slot_fsm1[4] = EMI1_SLOT3;
550 lane_to_slot_fsm1[5] = EMI1_SLOT3;
551 lane_to_slot_fsm1[6] = EMI1_SLOT3;
552 lane_to_slot_fsm1[7] = EMI_NONE;
556 printf("qds: WRIOP: Supported SerDes1 Protocol 0x%02x\n",
558 if (hwconfig_f("xqsgmii", env_hwconfig)) {
559 lane_to_slot_fsm1[0] = EMI1_SLOT3;
560 lane_to_slot_fsm1[1] = EMI1_SLOT3;
561 lane_to_slot_fsm1[2] = EMI_NONE;
562 lane_to_slot_fsm1[3] = EMI_NONE;
564 lane_to_slot_fsm1[0] = EMI_NONE;
565 lane_to_slot_fsm1[1] = EMI_NONE;
566 lane_to_slot_fsm1[2] = EMI_NONE;
567 lane_to_slot_fsm1[3] = EMI_NONE;
569 lane_to_slot_fsm1[4] = EMI1_SLOT3;
570 lane_to_slot_fsm1[5] = EMI1_SLOT3;
571 lane_to_slot_fsm1[6] = EMI_NONE;
572 lane_to_slot_fsm1[7] = EMI_NONE;
578 printf("qds: WRIOP: Supported SerDes1 Protocol 0x%02x\n",
582 printf("%s qds: WRIOP: Unsupported SerDes1 Protocol 0x%02x\n",
583 __func__, serdes1_prtcl);
587 switch (serdes2_prtcl) {
592 printf("qds: WRIOP: Supported SerDes2 Protocol 0x%02x\n",
594 lane_to_slot_fsm2[0] = EMI1_SLOT4;
595 lane_to_slot_fsm2[1] = EMI1_SLOT4;
596 lane_to_slot_fsm2[2] = EMI1_SLOT4;
597 lane_to_slot_fsm2[3] = EMI1_SLOT4;
599 if (hwconfig_f("xqsgmii", env_hwconfig)) {
600 lane_to_slot_fsm2[4] = EMI1_SLOT4;
601 lane_to_slot_fsm2[5] = EMI1_SLOT4;
602 lane_to_slot_fsm2[6] = EMI1_SLOT4;
603 lane_to_slot_fsm2[7] = EMI1_SLOT4;
605 /* No MDIO physical connection */
606 lane_to_slot_fsm2[4] = EMI1_SLOT6;
607 lane_to_slot_fsm2[5] = EMI1_SLOT6;
608 lane_to_slot_fsm2[6] = EMI1_SLOT6;
609 lane_to_slot_fsm2[7] = EMI1_SLOT6;
614 printf("qds: WRIOP: Supported SerDes2 Protocol 0x%02x\n",
616 lane_to_slot_fsm2[0] = EMI_NONE;
617 lane_to_slot_fsm2[1] = EMI1_SLOT5;
618 lane_to_slot_fsm2[2] = EMI1_SLOT5;
619 lane_to_slot_fsm2[3] = EMI1_SLOT5;
621 if (hwconfig_f("xqsgmii", env_hwconfig)) {
622 lane_to_slot_fsm2[4] = EMI_NONE;
623 lane_to_slot_fsm2[5] = EMI1_SLOT5;
624 lane_to_slot_fsm2[6] = EMI1_SLOT5;
625 lane_to_slot_fsm2[7] = EMI1_SLOT5;
630 printf("qds: WRIOP: Supported SerDes2 Protocol 0x%02x\n",
632 if (hwconfig_f("xqsgmii", env_hwconfig)) {
633 lane_to_slot_fsm2[0] = EMI_NONE;
634 lane_to_slot_fsm2[1] = EMI_NONE;
635 lane_to_slot_fsm2[2] = EMI_NONE;
636 lane_to_slot_fsm2[3] = EMI_NONE;
638 lane_to_slot_fsm2[4] = EMI_NONE;
639 lane_to_slot_fsm2[5] = EMI_NONE;
640 lane_to_slot_fsm2[6] = EMI1_SLOT5;
641 lane_to_slot_fsm2[7] = EMI1_SLOT5;
645 printf(" %s qds: WRIOP: Unsupported SerDes2 Protocol 0x%02x\n",
646 __func__ , serdes2_prtcl);
651 void ls2080a_handle_phy_interface_sgmii(int dpmac_id)
655 struct ccsr_gur __iomem *gur = (void *)CONFIG_SYS_FSL_GUTS_ADDR;
656 int serdes1_prtcl = (in_le32(&gur->rcwsr[28]) &
657 FSL_CHASSIS3_RCWSR28_SRDS1_PRTCL_MASK)
658 >> FSL_CHASSIS3_RCWSR28_SRDS1_PRTCL_SHIFT;
659 int serdes2_prtcl = (in_le32(&gur->rcwsr[28]) &
660 FSL_CHASSIS3_RCWSR28_SRDS2_PRTCL_MASK)
661 >> FSL_CHASSIS3_RCWSR28_SRDS2_PRTCL_SHIFT;
664 char *env_hwconfig = env_get("hwconfig");
666 if (hwconfig_f("xqsgmii", env_hwconfig))
667 riser_phy_addr = &xqsgii_riser_phy_addr[0];
669 riser_phy_addr = &sgmii_riser_phy_addr[0];
671 if (dpmac_id > WRIOP1_DPMAC9)
674 switch (serdes1_prtcl) {
678 lane = serdes_get_first_lane(FSL_SRDS_1, SGMII1 + dpmac_id - 1);
680 slot = lane_to_slot_fsm1[lane];
684 /* Slot housing a SGMII riser card? */
685 wriop_set_phy_address(dpmac_id, 0,
686 riser_phy_addr[dpmac_id - 1]);
687 dpmac_info[dpmac_id].board_mux = EMI1_SLOT1;
688 bus = mii_dev_for_muxval(EMI1_SLOT1);
689 wriop_set_mdio(dpmac_id, bus);
692 /* Slot housing a SGMII riser card? */
693 wriop_set_phy_address(dpmac_id, 0,
694 riser_phy_addr[dpmac_id - 1]);
695 dpmac_info[dpmac_id].board_mux = EMI1_SLOT2;
696 bus = mii_dev_for_muxval(EMI1_SLOT2);
697 wriop_set_mdio(dpmac_id, bus);
700 if (slot == EMI_NONE)
702 if (serdes1_prtcl == 0x39) {
703 wriop_set_phy_address(dpmac_id, 0,
704 riser_phy_addr[dpmac_id - 2]);
705 if (dpmac_id >= 6 && hwconfig_f("xqsgmii",
707 wriop_set_phy_address(dpmac_id, 0,
708 riser_phy_addr[dpmac_id - 3]);
710 wriop_set_phy_address(dpmac_id, 0,
711 riser_phy_addr[dpmac_id - 2]);
712 if (dpmac_id >= 7 && hwconfig_f("xqsgmii",
714 wriop_set_phy_address(dpmac_id, 0,
715 riser_phy_addr[dpmac_id - 3]);
717 dpmac_info[dpmac_id].board_mux = EMI1_SLOT3;
718 bus = mii_dev_for_muxval(EMI1_SLOT3);
719 wriop_set_mdio(dpmac_id, bus);
730 printf("%s qds: WRIOP: Unsupported SerDes1 Protocol 0x%02x\n",
731 __func__ , serdes1_prtcl);
736 switch (serdes2_prtcl) {
742 lane = serdes_get_first_lane(FSL_SRDS_2, SGMII9 +
744 slot = lane_to_slot_fsm2[lane];
752 /* Slot housing a SGMII riser card? */
753 wriop_set_phy_address(dpmac_id, 0,
754 riser_phy_addr[dpmac_id - 9]);
755 dpmac_info[dpmac_id].board_mux = EMI1_SLOT4;
756 bus = mii_dev_for_muxval(EMI1_SLOT4);
757 wriop_set_mdio(dpmac_id, bus);
760 if (slot == EMI_NONE)
762 if (serdes2_prtcl == 0x47) {
763 wriop_set_phy_address(dpmac_id, 0,
764 riser_phy_addr[dpmac_id - 10]);
765 if (dpmac_id >= 14 && hwconfig_f("xqsgmii",
767 wriop_set_phy_address(dpmac_id, 0,
768 riser_phy_addr[dpmac_id - 11]);
770 wriop_set_phy_address(dpmac_id, 0,
771 riser_phy_addr[dpmac_id - 11]);
773 dpmac_info[dpmac_id].board_mux = EMI1_SLOT5;
774 bus = mii_dev_for_muxval(EMI1_SLOT5);
775 wriop_set_mdio(dpmac_id, bus);
778 /* Slot housing a SGMII riser card? */
779 wriop_set_phy_address(dpmac_id, 0,
780 riser_phy_addr[dpmac_id - 13]);
781 dpmac_info[dpmac_id].board_mux = EMI1_SLOT6;
782 bus = mii_dev_for_muxval(EMI1_SLOT6);
783 wriop_set_mdio(dpmac_id, bus);
788 printf("%s qds: WRIOP: Unsupported SerDes2 Protocol 0x%02x\n",
789 __func__, serdes2_prtcl);
794 void ls2080a_handle_phy_interface_qsgmii(int dpmac_id)
798 struct ccsr_gur __iomem *gur = (void *)CONFIG_SYS_FSL_GUTS_ADDR;
799 int serdes1_prtcl = (in_le32(&gur->rcwsr[28]) &
800 FSL_CHASSIS3_RCWSR28_SRDS1_PRTCL_MASK)
801 >> FSL_CHASSIS3_RCWSR28_SRDS1_PRTCL_SHIFT;
803 switch (serdes1_prtcl) {
810 lane = serdes_get_first_lane(FSL_SRDS_1, QSGMII_A);
816 lane = serdes_get_first_lane(FSL_SRDS_1, QSGMII_B);
822 lane = serdes_get_first_lane(FSL_SRDS_1, QSGMII_C);
828 lane = serdes_get_first_lane(FSL_SRDS_1, QSGMII_D);
832 slot = lane_to_slot_fsm1[lane];
836 /* Slot housing a QSGMII riser card? */
837 wriop_set_phy_address(dpmac_id, 0, dpmac_id - 1);
838 dpmac_info[dpmac_id].board_mux = EMI1_SLOT1;
839 bus = mii_dev_for_muxval(EMI1_SLOT1);
840 wriop_set_mdio(dpmac_id, bus);
853 printf("qds: WRIOP: Unsupported SerDes Protocol 0x%02x\n",
858 qsgmii_configure_repeater(dpmac_id);
861 void ls2080a_handle_phy_interface_xsgmii(int i)
863 struct ccsr_gur __iomem *gur = (void *)CONFIG_SYS_FSL_GUTS_ADDR;
864 int serdes1_prtcl = (in_le32(&gur->rcwsr[28]) &
865 FSL_CHASSIS3_RCWSR28_SRDS1_PRTCL_MASK)
866 >> FSL_CHASSIS3_RCWSR28_SRDS1_PRTCL_SHIFT;
868 switch (serdes1_prtcl) {
873 * XFI does not need a PHY to work, but to avoid U-Boot use
874 * default PHY address which is zero to a MAC when it found
875 * a MAC has no PHY address, we give a PHY address to XFI
876 * MAC, and should not use a real XAUI PHY address, since
877 * MDIO can access it successfully, and then MDIO thinks
878 * the XAUI card is used for the XFI MAC, which will cause
881 wriop_set_phy_address(i, 0, i + 4);
882 ls2080a_qds_enable_SFP_TX(SFP_TX);
886 printf("qds: WRIOP: Unsupported SerDes Protocol 0x%02x\n",
893 int board_eth_init(bd_t *bis)
896 #if defined(CONFIG_FSL_MC_ENET) && !defined(CONFIG_SPL_BUILD)
897 struct ccsr_gur __iomem *gur = (void *)CONFIG_SYS_FSL_GUTS_ADDR;
898 int serdes1_prtcl = (in_le32(&gur->rcwsr[28]) &
899 FSL_CHASSIS3_RCWSR28_SRDS1_PRTCL_MASK)
900 >> FSL_CHASSIS3_RCWSR28_SRDS1_PRTCL_SHIFT;
901 int serdes2_prtcl = (in_le32(&gur->rcwsr[28]) &
902 FSL_CHASSIS3_RCWSR28_SRDS2_PRTCL_MASK)
903 >> FSL_CHASSIS3_RCWSR28_SRDS2_PRTCL_SHIFT;
905 struct memac_mdio_info *memac_mdio0_info;
906 struct memac_mdio_info *memac_mdio1_info;
910 env_hwconfig = env_get("hwconfig");
912 initialize_dpmac_to_slot();
914 memac_mdio0_info = (struct memac_mdio_info *)malloc(
915 sizeof(struct memac_mdio_info));
916 memac_mdio0_info->regs =
917 (struct memac_mdio_controller *)
918 CONFIG_SYS_FSL_WRIOP1_MDIO1;
919 memac_mdio0_info->name = DEFAULT_WRIOP_MDIO1_NAME;
921 /* Register the real MDIO1 bus */
922 fm_memac_mdio_init(bis, memac_mdio0_info);
924 memac_mdio1_info = (struct memac_mdio_info *)malloc(
925 sizeof(struct memac_mdio_info));
926 memac_mdio1_info->regs =
927 (struct memac_mdio_controller *)
928 CONFIG_SYS_FSL_WRIOP1_MDIO2;
929 memac_mdio1_info->name = DEFAULT_WRIOP_MDIO2_NAME;
931 /* Register the real MDIO2 bus */
932 fm_memac_mdio_init(bis, memac_mdio1_info);
934 /* Register the muxing front-ends to the MDIO buses */
935 ls2080a_qds_mdio_init(DEFAULT_WRIOP_MDIO1_NAME, EMI1_SLOT1);
936 ls2080a_qds_mdio_init(DEFAULT_WRIOP_MDIO1_NAME, EMI1_SLOT2);
937 ls2080a_qds_mdio_init(DEFAULT_WRIOP_MDIO1_NAME, EMI1_SLOT3);
938 ls2080a_qds_mdio_init(DEFAULT_WRIOP_MDIO1_NAME, EMI1_SLOT4);
939 ls2080a_qds_mdio_init(DEFAULT_WRIOP_MDIO1_NAME, EMI1_SLOT5);
940 ls2080a_qds_mdio_init(DEFAULT_WRIOP_MDIO1_NAME, EMI1_SLOT6);
942 ls2080a_qds_mdio_init(DEFAULT_WRIOP_MDIO2_NAME, EMI2);
944 for (i = WRIOP1_DPMAC1; i < NUM_WRIOP_PORTS; i++) {
945 switch (wriop_get_enet_if(i)) {
946 case PHY_INTERFACE_MODE_QSGMII:
947 ls2080a_handle_phy_interface_qsgmii(i);
949 case PHY_INTERFACE_MODE_SGMII:
950 ls2080a_handle_phy_interface_sgmii(i);
952 case PHY_INTERFACE_MODE_XGMII:
953 ls2080a_handle_phy_interface_xsgmii(i);
963 error = cpu_eth_init(bis);
965 if (hwconfig_f("xqsgmii", env_hwconfig)) {
966 if (serdes1_prtcl == 0x7)
967 sgmii_configure_repeater(1);
968 if (serdes2_prtcl == 0x7 || serdes2_prtcl == 0x8 ||
969 serdes2_prtcl == 0x49)
970 sgmii_configure_repeater(2);
973 error = pci_eth_init(bis);
977 #if defined(CONFIG_RESET_PHY_R)
982 #endif /* CONFIG_RESET_PHY_R */