1 // SPDX-License-Identifier: GPL-2.0+
3 * Copyright 2015 Freescale Semiconductor, Inc.
11 #include <asm/arch/fsl_serdes.h>
18 #include <fsl-mc/fsl_mc.h>
19 #include <fsl-mc/ldpaa_wriop.h>
21 #include "../common/qixis.h"
23 #include "ls2080aqds_qixis.h"
25 #define MC_BOOT_ENV_VAR "mcinitcmd"
29 #if defined(CONFIG_FSL_MC_ENET) && !defined(CONFIG_SPL_BUILD)
30 /* - In LS2080A there are only 16 SERDES lanes, spread across 2 SERDES banks.
31 * Bank 1 -> Lanes A, B, C, D, E, F, G, H
32 * Bank 2 -> Lanes A,B, C, D, E, F, G, H
35 /* Mapping of 16 SERDES lanes to LS2080A QDS board slots. A value of '0' here
36 * means that the mapping must be determined dynamically, or that the lane
37 * maps to something other than a board slot.
40 static u8 lane_to_slot_fsm1[] = {
41 0, 0, 0, 0, 0, 0, 0, 0
44 static u8 lane_to_slot_fsm2[] = {
45 0, 0, 0, 0, 0, 0, 0, 0
48 /* On the Vitesse VSC8234XHG SGMII riser card there are 4 SGMII PHYs
52 static int xqsgii_riser_phy_addr[] = {
53 XQSGMII_CARD_PHY1_PORT0_ADDR,
54 XQSGMII_CARD_PHY2_PORT0_ADDR,
55 XQSGMII_CARD_PHY3_PORT0_ADDR,
56 XQSGMII_CARD_PHY4_PORT0_ADDR,
57 XQSGMII_CARD_PHY3_PORT2_ADDR,
58 XQSGMII_CARD_PHY1_PORT2_ADDR,
59 XQSGMII_CARD_PHY4_PORT2_ADDR,
60 XQSGMII_CARD_PHY2_PORT2_ADDR,
63 static int sgmii_riser_phy_addr[] = {
64 SGMII_CARD_PORT1_PHY_ADDR,
65 SGMII_CARD_PORT2_PHY_ADDR,
66 SGMII_CARD_PORT3_PHY_ADDR,
67 SGMII_CARD_PORT4_PHY_ADDR,
70 /* Slot2 does not have EMI connections */
81 static const char * const mdio_names[] = {
88 DEFAULT_WRIOP_MDIO2_NAME,
91 struct ls2080a_qds_mdio {
93 struct mii_dev *realbus;
101 static void sgmii_configure_repeater(int serdes_port)
106 int dpmac_id = 0, dpmac, mii_bus = 0;
107 unsigned short value;
108 char dev[2][20] = {"LS2080A_QDS_MDIO0", "LS2080A_QDS_MDIO3"};
109 uint8_t i2c_addr[] = {0x58, 0x59, 0x5a, 0x5b, 0x5c, 0x5d, 0x5f, 0x60};
111 uint8_t ch_a_eq[] = {0x1, 0x2, 0x3, 0x7};
112 uint8_t ch_a_ctl2[] = {0x81, 0x82, 0x83, 0x84};
113 uint8_t ch_b_eq[] = {0x1, 0x2, 0x3, 0x7};
114 uint8_t ch_b_ctl2[] = {0x81, 0x82, 0x83, 0x84};
116 u8 reg_val[6] = {0x18, 0x38, 0x4, 0x14, 0xb5, 0x20};
117 struct reg_pair reg_pair[10] = {
118 {6, ®_val[0]}, {4, ®_val[1]},
119 {8, ®_val[2]}, {0xf, NULL},
120 {0x11, NULL}, {0x16, NULL},
121 {0x18, NULL}, {0x23, ®_val[3]},
122 {0x2d, ®_val[4]}, {4, ®_val[5]},
125 int *riser_phy_addr = &xqsgii_riser_phy_addr[0];
127 struct udevice *udev;
130 /* Set I2c to Slot 1 */
131 #ifndef CONFIG_DM_I2C
132 ret = i2c_write(0x77, 0, 0, &a, 1);
134 ret = i2c_get_chip_for_busnum(0, 0x77, 1, &udev);
136 ret = dm_i2c_write(udev, 0, &a, 1);
141 for (dpmac = 0; dpmac < 8; dpmac++) {
142 /* Check the PHY status */
143 switch (serdes_port) {
146 dpmac_id = dpmac + 1;
150 dpmac_id = dpmac + 9;
152 #ifndef CONFIG_DM_I2C
153 ret = i2c_write(0x76, 0, 0, &a, 1);
155 ret = i2c_get_chip_for_busnum(0, 0x76, 1, &udev);
157 ret = dm_i2c_write(udev, 0, &a, 1);
164 ret = miiphy_set_current_dev(dev[mii_bus]);
168 bus = mdio_get_current_dev();
169 debug("Reading from bus %s\n", bus->name);
171 ret = miiphy_write(dev[mii_bus], riser_phy_addr[dpmac], 0x1f,
177 ret = miiphy_read(dev[mii_bus], riser_phy_addr[dpmac], 0x11,
184 if ((value & 0xfff) == 0x401) {
185 printf("DPMAC %d:PHY is ..... Configured\n", dpmac_id);
186 miiphy_write(dev[mii_bus], riser_phy_addr[dpmac],
191 for (i = 0; i < 4; i++) {
192 for (j = 0; j < 4; j++) {
193 reg_pair[3].val = &ch_a_eq[i];
194 reg_pair[4].val = &ch_a_ctl2[j];
195 reg_pair[5].val = &ch_b_eq[i];
196 reg_pair[6].val = &ch_b_ctl2[j];
198 for (k = 0; k < 10; k++) {
199 #ifndef CONFIG_DM_I2C
200 ret = i2c_write(i2c_addr[dpmac],
202 1, reg_pair[k].val, 1);
204 ret = i2c_get_chip_for_busnum(0,
208 ret = dm_i2c_write(udev,
217 ret = miiphy_read(dev[mii_bus],
218 riser_phy_addr[dpmac],
224 ret = miiphy_read(dev[mii_bus],
225 riser_phy_addr[dpmac],
230 if ((value & 0xfff) == 0x401) {
231 printf("DPMAC %d :PHY is configured ",
233 printf("after setting repeater 0x%x\n",
238 printf("DPMAC %d :PHY is failed to ",
240 printf("configure the repeater 0x%x\n",
245 miiphy_write(dev[mii_bus], riser_phy_addr[dpmac], 0x1f, 0);
249 printf("DPMAC %d ..... FAILED to configure PHY\n", dpmac_id);
253 static void qsgmii_configure_repeater(int dpmac)
257 int i2c_phy_addr = 0;
259 int i2c_addr[] = {0x58, 0x59, 0x5a, 0x5b};
261 uint8_t ch_a_eq[] = {0x1, 0x2, 0x3, 0x7};
262 uint8_t ch_a_ctl2[] = {0x81, 0x82, 0x83, 0x84};
263 uint8_t ch_b_eq[] = {0x1, 0x2, 0x3, 0x7};
264 uint8_t ch_b_ctl2[] = {0x81, 0x82, 0x83, 0x84};
266 u8 reg_val[6] = {0x18, 0x38, 0x4, 0x14, 0xb5, 0x20};
267 struct reg_pair reg_pair[10] = {
268 {6, ®_val[0]}, {4, ®_val[1]},
269 {8, ®_val[2]}, {0xf, NULL},
270 {0x11, NULL}, {0x16, NULL},
271 {0x18, NULL}, {0x23, ®_val[3]},
272 {0x2d, ®_val[4]}, {4, ®_val[5]},
275 const char *dev = "LS2080A_QDS_MDIO0";
277 unsigned short value;
279 struct udevice *udev;
282 /* Set I2c to Slot 1 */
283 #ifndef CONFIG_DM_I2C
284 ret = i2c_write(0x77, 0, 0, &a, 1);
286 ret = i2c_get_chip_for_busnum(0, 0x77, 1, &udev);
288 ret = dm_i2c_write(udev, 0, &a, 1);
298 i2c_phy_addr = i2c_addr[0];
306 i2c_phy_addr = i2c_addr[1];
314 i2c_phy_addr = i2c_addr[2];
322 i2c_phy_addr = i2c_addr[3];
327 /* Check the PHY status */
328 ret = miiphy_set_current_dev(dev);
329 ret = miiphy_write(dev, phy_addr, 0x1f, 3);
331 ret = miiphy_read(dev, phy_addr, 0x11, &value);
333 ret = miiphy_read(dev, phy_addr, 0x11, &value);
335 if ((value & 0xf) == 0xf) {
336 printf("DPMAC %d :PHY is ..... Configured\n", dpmac);
340 for (i = 0; i < 4; i++) {
341 for (j = 0; j < 4; j++) {
342 reg_pair[3].val = &ch_a_eq[i];
343 reg_pair[4].val = &ch_a_ctl2[j];
344 reg_pair[5].val = &ch_b_eq[i];
345 reg_pair[6].val = &ch_b_ctl2[j];
347 for (k = 0; k < 10; k++) {
348 #ifndef CONFIG_DM_I2C
349 ret = i2c_write(i2c_phy_addr,
351 1, reg_pair[k].val, 1);
353 ret = i2c_get_chip_for_busnum(0,
357 ret = dm_i2c_write(udev,
366 ret = miiphy_read(dev, phy_addr, 0x11, &value);
370 ret = miiphy_read(dev, phy_addr, 0x11, &value);
374 if ((value & 0xf) == 0xf) {
375 printf("DPMAC %d :PHY is ..... Configured\n",
382 printf("DPMAC %d :PHY ..... FAILED to configure PHY\n", dpmac);
386 static const char *ls2080a_qds_mdio_name_for_muxval(u8 muxval)
388 return mdio_names[muxval];
391 struct mii_dev *mii_dev_for_muxval(u8 muxval)
394 const char *name = ls2080a_qds_mdio_name_for_muxval(muxval);
397 printf("No bus for muxval %x\n", muxval);
401 bus = miiphy_get_dev_by_name(name);
404 printf("No bus by name %s\n", name);
411 static void ls2080a_qds_enable_SFP_TX(u8 muxval)
415 brdcfg9 = QIXIS_READ(brdcfg[9]);
416 brdcfg9 &= ~BRDCFG9_SFPTX_MASK;
417 brdcfg9 |= (muxval << BRDCFG9_SFPTX_SHIFT);
418 QIXIS_WRITE(brdcfg[9], brdcfg9);
421 static void ls2080a_qds_mux_mdio(u8 muxval)
426 brdcfg4 = QIXIS_READ(brdcfg[4]);
427 brdcfg4 &= ~BRDCFG4_EMISEL_MASK;
428 brdcfg4 |= (muxval << BRDCFG4_EMISEL_SHIFT);
429 QIXIS_WRITE(brdcfg[4], brdcfg4);
433 static int ls2080a_qds_mdio_read(struct mii_dev *bus, int addr,
434 int devad, int regnum)
436 struct ls2080a_qds_mdio *priv = bus->priv;
438 ls2080a_qds_mux_mdio(priv->muxval);
440 return priv->realbus->read(priv->realbus, addr, devad, regnum);
443 static int ls2080a_qds_mdio_write(struct mii_dev *bus, int addr, int devad,
444 int regnum, u16 value)
446 struct ls2080a_qds_mdio *priv = bus->priv;
448 ls2080a_qds_mux_mdio(priv->muxval);
450 return priv->realbus->write(priv->realbus, addr, devad, regnum, value);
453 static int ls2080a_qds_mdio_reset(struct mii_dev *bus)
455 struct ls2080a_qds_mdio *priv = bus->priv;
457 return priv->realbus->reset(priv->realbus);
460 static int ls2080a_qds_mdio_init(char *realbusname, u8 muxval)
462 struct ls2080a_qds_mdio *pmdio;
463 struct mii_dev *bus = mdio_alloc();
466 printf("Failed to allocate ls2080a_qds MDIO bus\n");
470 pmdio = malloc(sizeof(*pmdio));
472 printf("Failed to allocate ls2080a_qds private data\n");
477 bus->read = ls2080a_qds_mdio_read;
478 bus->write = ls2080a_qds_mdio_write;
479 bus->reset = ls2080a_qds_mdio_reset;
480 strcpy(bus->name, ls2080a_qds_mdio_name_for_muxval(muxval));
482 pmdio->realbus = miiphy_get_dev_by_name(realbusname);
484 if (!pmdio->realbus) {
485 printf("No bus with name %s\n", realbusname);
491 pmdio->muxval = muxval;
494 return mdio_register(bus);
498 * Initialize the dpmac_info array.
501 static void initialize_dpmac_to_slot(void)
503 struct ccsr_gur __iomem *gur = (void *)CONFIG_SYS_FSL_GUTS_ADDR;
504 int serdes1_prtcl = (in_le32(&gur->rcwsr[28]) &
505 FSL_CHASSIS3_RCWSR28_SRDS1_PRTCL_MASK)
506 >> FSL_CHASSIS3_RCWSR28_SRDS1_PRTCL_SHIFT;
507 int serdes2_prtcl = (in_le32(&gur->rcwsr[28]) &
508 FSL_CHASSIS3_RCWSR28_SRDS2_PRTCL_MASK)
509 >> FSL_CHASSIS3_RCWSR28_SRDS2_PRTCL_SHIFT;
512 env_hwconfig = env_get("hwconfig");
514 switch (serdes1_prtcl) {
518 printf("qds: WRIOP: Supported SerDes1 Protocol 0x%02x\n",
520 lane_to_slot_fsm1[0] = EMI1_SLOT1;
521 lane_to_slot_fsm1[1] = EMI1_SLOT1;
522 lane_to_slot_fsm1[2] = EMI1_SLOT1;
523 lane_to_slot_fsm1[3] = EMI1_SLOT1;
524 if (hwconfig_f("xqsgmii", env_hwconfig)) {
525 lane_to_slot_fsm1[4] = EMI1_SLOT1;
526 lane_to_slot_fsm1[5] = EMI1_SLOT1;
527 lane_to_slot_fsm1[6] = EMI1_SLOT1;
528 lane_to_slot_fsm1[7] = EMI1_SLOT1;
530 lane_to_slot_fsm1[4] = EMI1_SLOT2;
531 lane_to_slot_fsm1[5] = EMI1_SLOT2;
532 lane_to_slot_fsm1[6] = EMI1_SLOT2;
533 lane_to_slot_fsm1[7] = EMI1_SLOT2;
538 printf("qds: WRIOP: Supported SerDes1 Protocol 0x%02x\n",
540 if (hwconfig_f("xqsgmii", env_hwconfig)) {
541 lane_to_slot_fsm1[0] = EMI1_SLOT3;
542 lane_to_slot_fsm1[1] = EMI1_SLOT3;
543 lane_to_slot_fsm1[2] = EMI1_SLOT3;
544 lane_to_slot_fsm1[3] = EMI_NONE;
546 lane_to_slot_fsm1[0] = EMI_NONE;
547 lane_to_slot_fsm1[1] = EMI_NONE;
548 lane_to_slot_fsm1[2] = EMI_NONE;
549 lane_to_slot_fsm1[3] = EMI_NONE;
551 lane_to_slot_fsm1[4] = EMI1_SLOT3;
552 lane_to_slot_fsm1[5] = EMI1_SLOT3;
553 lane_to_slot_fsm1[6] = EMI1_SLOT3;
554 lane_to_slot_fsm1[7] = EMI_NONE;
558 printf("qds: WRIOP: Supported SerDes1 Protocol 0x%02x\n",
560 if (hwconfig_f("xqsgmii", env_hwconfig)) {
561 lane_to_slot_fsm1[0] = EMI1_SLOT3;
562 lane_to_slot_fsm1[1] = EMI1_SLOT3;
563 lane_to_slot_fsm1[2] = EMI_NONE;
564 lane_to_slot_fsm1[3] = EMI_NONE;
566 lane_to_slot_fsm1[0] = EMI_NONE;
567 lane_to_slot_fsm1[1] = EMI_NONE;
568 lane_to_slot_fsm1[2] = EMI_NONE;
569 lane_to_slot_fsm1[3] = EMI_NONE;
571 lane_to_slot_fsm1[4] = EMI1_SLOT3;
572 lane_to_slot_fsm1[5] = EMI1_SLOT3;
573 lane_to_slot_fsm1[6] = EMI_NONE;
574 lane_to_slot_fsm1[7] = EMI_NONE;
580 printf("qds: WRIOP: Supported SerDes1 Protocol 0x%02x\n",
584 printf("%s qds: WRIOP: Unsupported SerDes1 Protocol 0x%02x\n",
585 __func__, serdes1_prtcl);
589 switch (serdes2_prtcl) {
594 printf("qds: WRIOP: Supported SerDes2 Protocol 0x%02x\n",
596 lane_to_slot_fsm2[0] = EMI1_SLOT4;
597 lane_to_slot_fsm2[1] = EMI1_SLOT4;
598 lane_to_slot_fsm2[2] = EMI1_SLOT4;
599 lane_to_slot_fsm2[3] = EMI1_SLOT4;
601 if (hwconfig_f("xqsgmii", env_hwconfig)) {
602 lane_to_slot_fsm2[4] = EMI1_SLOT4;
603 lane_to_slot_fsm2[5] = EMI1_SLOT4;
604 lane_to_slot_fsm2[6] = EMI1_SLOT4;
605 lane_to_slot_fsm2[7] = EMI1_SLOT4;
607 /* No MDIO physical connection */
608 lane_to_slot_fsm2[4] = EMI1_SLOT6;
609 lane_to_slot_fsm2[5] = EMI1_SLOT6;
610 lane_to_slot_fsm2[6] = EMI1_SLOT6;
611 lane_to_slot_fsm2[7] = EMI1_SLOT6;
616 printf("qds: WRIOP: Supported SerDes2 Protocol 0x%02x\n",
618 lane_to_slot_fsm2[0] = EMI_NONE;
619 lane_to_slot_fsm2[1] = EMI1_SLOT5;
620 lane_to_slot_fsm2[2] = EMI1_SLOT5;
621 lane_to_slot_fsm2[3] = EMI1_SLOT5;
623 if (hwconfig_f("xqsgmii", env_hwconfig)) {
624 lane_to_slot_fsm2[4] = EMI_NONE;
625 lane_to_slot_fsm2[5] = EMI1_SLOT5;
626 lane_to_slot_fsm2[6] = EMI1_SLOT5;
627 lane_to_slot_fsm2[7] = EMI1_SLOT5;
632 printf("qds: WRIOP: Supported SerDes2 Protocol 0x%02x\n",
634 if (hwconfig_f("xqsgmii", env_hwconfig)) {
635 lane_to_slot_fsm2[0] = EMI_NONE;
636 lane_to_slot_fsm2[1] = EMI_NONE;
637 lane_to_slot_fsm2[2] = EMI_NONE;
638 lane_to_slot_fsm2[3] = EMI_NONE;
640 lane_to_slot_fsm2[4] = EMI_NONE;
641 lane_to_slot_fsm2[5] = EMI_NONE;
642 lane_to_slot_fsm2[6] = EMI1_SLOT5;
643 lane_to_slot_fsm2[7] = EMI1_SLOT5;
647 printf(" %s qds: WRIOP: Unsupported SerDes2 Protocol 0x%02x\n",
648 __func__ , serdes2_prtcl);
653 void ls2080a_handle_phy_interface_sgmii(int dpmac_id)
657 struct ccsr_gur __iomem *gur = (void *)CONFIG_SYS_FSL_GUTS_ADDR;
658 int serdes1_prtcl = (in_le32(&gur->rcwsr[28]) &
659 FSL_CHASSIS3_RCWSR28_SRDS1_PRTCL_MASK)
660 >> FSL_CHASSIS3_RCWSR28_SRDS1_PRTCL_SHIFT;
661 int serdes2_prtcl = (in_le32(&gur->rcwsr[28]) &
662 FSL_CHASSIS3_RCWSR28_SRDS2_PRTCL_MASK)
663 >> FSL_CHASSIS3_RCWSR28_SRDS2_PRTCL_SHIFT;
666 char *env_hwconfig = env_get("hwconfig");
668 if (hwconfig_f("xqsgmii", env_hwconfig))
669 riser_phy_addr = &xqsgii_riser_phy_addr[0];
671 riser_phy_addr = &sgmii_riser_phy_addr[0];
673 if (dpmac_id > WRIOP1_DPMAC9)
676 switch (serdes1_prtcl) {
680 lane = serdes_get_first_lane(FSL_SRDS_1, SGMII1 + dpmac_id - 1);
682 slot = lane_to_slot_fsm1[lane];
686 /* Slot housing a SGMII riser card? */
687 wriop_set_phy_address(dpmac_id, 0,
688 riser_phy_addr[dpmac_id - 1]);
689 dpmac_info[dpmac_id].board_mux = EMI1_SLOT1;
690 bus = mii_dev_for_muxval(EMI1_SLOT1);
691 wriop_set_mdio(dpmac_id, bus);
694 /* Slot housing a SGMII riser card? */
695 wriop_set_phy_address(dpmac_id, 0,
696 riser_phy_addr[dpmac_id - 1]);
697 dpmac_info[dpmac_id].board_mux = EMI1_SLOT2;
698 bus = mii_dev_for_muxval(EMI1_SLOT2);
699 wriop_set_mdio(dpmac_id, bus);
702 if (slot == EMI_NONE)
704 if (serdes1_prtcl == 0x39) {
705 wriop_set_phy_address(dpmac_id, 0,
706 riser_phy_addr[dpmac_id - 2]);
707 if (dpmac_id >= 6 && hwconfig_f("xqsgmii",
709 wriop_set_phy_address(dpmac_id, 0,
710 riser_phy_addr[dpmac_id - 3]);
712 wriop_set_phy_address(dpmac_id, 0,
713 riser_phy_addr[dpmac_id - 2]);
714 if (dpmac_id >= 7 && hwconfig_f("xqsgmii",
716 wriop_set_phy_address(dpmac_id, 0,
717 riser_phy_addr[dpmac_id - 3]);
719 dpmac_info[dpmac_id].board_mux = EMI1_SLOT3;
720 bus = mii_dev_for_muxval(EMI1_SLOT3);
721 wriop_set_mdio(dpmac_id, bus);
732 printf("%s qds: WRIOP: Unsupported SerDes1 Protocol 0x%02x\n",
733 __func__ , serdes1_prtcl);
738 switch (serdes2_prtcl) {
744 lane = serdes_get_first_lane(FSL_SRDS_2, SGMII9 +
746 slot = lane_to_slot_fsm2[lane];
754 /* Slot housing a SGMII riser card? */
755 wriop_set_phy_address(dpmac_id, 0,
756 riser_phy_addr[dpmac_id - 9]);
757 dpmac_info[dpmac_id].board_mux = EMI1_SLOT4;
758 bus = mii_dev_for_muxval(EMI1_SLOT4);
759 wriop_set_mdio(dpmac_id, bus);
762 if (slot == EMI_NONE)
764 if (serdes2_prtcl == 0x47) {
765 wriop_set_phy_address(dpmac_id, 0,
766 riser_phy_addr[dpmac_id - 10]);
767 if (dpmac_id >= 14 && hwconfig_f("xqsgmii",
769 wriop_set_phy_address(dpmac_id, 0,
770 riser_phy_addr[dpmac_id - 11]);
772 wriop_set_phy_address(dpmac_id, 0,
773 riser_phy_addr[dpmac_id - 11]);
775 dpmac_info[dpmac_id].board_mux = EMI1_SLOT5;
776 bus = mii_dev_for_muxval(EMI1_SLOT5);
777 wriop_set_mdio(dpmac_id, bus);
780 /* Slot housing a SGMII riser card? */
781 wriop_set_phy_address(dpmac_id, 0,
782 riser_phy_addr[dpmac_id - 13]);
783 dpmac_info[dpmac_id].board_mux = EMI1_SLOT6;
784 bus = mii_dev_for_muxval(EMI1_SLOT6);
785 wriop_set_mdio(dpmac_id, bus);
790 printf("%s qds: WRIOP: Unsupported SerDes2 Protocol 0x%02x\n",
791 __func__, serdes2_prtcl);
796 void ls2080a_handle_phy_interface_qsgmii(int dpmac_id)
800 struct ccsr_gur __iomem *gur = (void *)CONFIG_SYS_FSL_GUTS_ADDR;
801 int serdes1_prtcl = (in_le32(&gur->rcwsr[28]) &
802 FSL_CHASSIS3_RCWSR28_SRDS1_PRTCL_MASK)
803 >> FSL_CHASSIS3_RCWSR28_SRDS1_PRTCL_SHIFT;
805 switch (serdes1_prtcl) {
812 lane = serdes_get_first_lane(FSL_SRDS_1, QSGMII_A);
818 lane = serdes_get_first_lane(FSL_SRDS_1, QSGMII_B);
824 lane = serdes_get_first_lane(FSL_SRDS_1, QSGMII_C);
830 lane = serdes_get_first_lane(FSL_SRDS_1, QSGMII_D);
834 slot = lane_to_slot_fsm1[lane];
838 /* Slot housing a QSGMII riser card? */
839 wriop_set_phy_address(dpmac_id, 0, dpmac_id - 1);
840 dpmac_info[dpmac_id].board_mux = EMI1_SLOT1;
841 bus = mii_dev_for_muxval(EMI1_SLOT1);
842 wriop_set_mdio(dpmac_id, bus);
855 printf("qds: WRIOP: Unsupported SerDes Protocol 0x%02x\n",
860 qsgmii_configure_repeater(dpmac_id);
863 void ls2080a_handle_phy_interface_xsgmii(int i)
865 struct ccsr_gur __iomem *gur = (void *)CONFIG_SYS_FSL_GUTS_ADDR;
866 int serdes1_prtcl = (in_le32(&gur->rcwsr[28]) &
867 FSL_CHASSIS3_RCWSR28_SRDS1_PRTCL_MASK)
868 >> FSL_CHASSIS3_RCWSR28_SRDS1_PRTCL_SHIFT;
870 switch (serdes1_prtcl) {
875 * XFI does not need a PHY to work, but to avoid U-Boot use
876 * default PHY address which is zero to a MAC when it found
877 * a MAC has no PHY address, we give a PHY address to XFI
878 * MAC, and should not use a real XAUI PHY address, since
879 * MDIO can access it successfully, and then MDIO thinks
880 * the XAUI card is used for the XFI MAC, which will cause
883 wriop_set_phy_address(i, 0, i + 4);
884 ls2080a_qds_enable_SFP_TX(SFP_TX);
888 printf("qds: WRIOP: Unsupported SerDes Protocol 0x%02x\n",
894 #endif // !CONFIG_DM_ETH
896 int board_eth_init(bd_t *bis)
898 #ifndef CONFIG_DM_ETH
899 #if defined(CONFIG_FSL_MC_ENET) && !defined(CONFIG_SPL_BUILD)
900 struct ccsr_gur __iomem *gur = (void *)CONFIG_SYS_FSL_GUTS_ADDR;
901 int serdes1_prtcl = (in_le32(&gur->rcwsr[28]) &
902 FSL_CHASSIS3_RCWSR28_SRDS1_PRTCL_MASK)
903 >> FSL_CHASSIS3_RCWSR28_SRDS1_PRTCL_SHIFT;
904 int serdes2_prtcl = (in_le32(&gur->rcwsr[28]) &
905 FSL_CHASSIS3_RCWSR28_SRDS2_PRTCL_MASK)
906 >> FSL_CHASSIS3_RCWSR28_SRDS2_PRTCL_SHIFT;
908 struct memac_mdio_info *memac_mdio0_info;
909 struct memac_mdio_info *memac_mdio1_info;
914 env_hwconfig = env_get("hwconfig");
916 initialize_dpmac_to_slot();
918 memac_mdio0_info = (struct memac_mdio_info *)malloc(
919 sizeof(struct memac_mdio_info));
920 memac_mdio0_info->regs =
921 (struct memac_mdio_controller *)
922 CONFIG_SYS_FSL_WRIOP1_MDIO1;
923 memac_mdio0_info->name = DEFAULT_WRIOP_MDIO1_NAME;
925 /* Register the real MDIO1 bus */
926 fm_memac_mdio_init(bis, memac_mdio0_info);
928 memac_mdio1_info = (struct memac_mdio_info *)malloc(
929 sizeof(struct memac_mdio_info));
930 memac_mdio1_info->regs =
931 (struct memac_mdio_controller *)
932 CONFIG_SYS_FSL_WRIOP1_MDIO2;
933 memac_mdio1_info->name = DEFAULT_WRIOP_MDIO2_NAME;
935 /* Register the real MDIO2 bus */
936 fm_memac_mdio_init(bis, memac_mdio1_info);
938 /* Register the muxing front-ends to the MDIO buses */
939 ls2080a_qds_mdio_init(DEFAULT_WRIOP_MDIO1_NAME, EMI1_SLOT1);
940 ls2080a_qds_mdio_init(DEFAULT_WRIOP_MDIO1_NAME, EMI1_SLOT2);
941 ls2080a_qds_mdio_init(DEFAULT_WRIOP_MDIO1_NAME, EMI1_SLOT3);
942 ls2080a_qds_mdio_init(DEFAULT_WRIOP_MDIO1_NAME, EMI1_SLOT4);
943 ls2080a_qds_mdio_init(DEFAULT_WRIOP_MDIO1_NAME, EMI1_SLOT5);
944 ls2080a_qds_mdio_init(DEFAULT_WRIOP_MDIO1_NAME, EMI1_SLOT6);
946 ls2080a_qds_mdio_init(DEFAULT_WRIOP_MDIO2_NAME, EMI2);
948 for (i = WRIOP1_DPMAC1; i < NUM_WRIOP_PORTS; i++) {
949 switch (wriop_get_enet_if(i)) {
950 case PHY_INTERFACE_MODE_QSGMII:
951 ls2080a_handle_phy_interface_qsgmii(i);
953 case PHY_INTERFACE_MODE_SGMII:
954 ls2080a_handle_phy_interface_sgmii(i);
956 case PHY_INTERFACE_MODE_XGMII:
957 ls2080a_handle_phy_interface_xsgmii(i);
967 error = cpu_eth_init(bis);
969 if (hwconfig_f("xqsgmii", env_hwconfig)) {
970 if (serdes1_prtcl == 0x7)
971 sgmii_configure_repeater(1);
972 if (serdes2_prtcl == 0x7 || serdes2_prtcl == 0x8 ||
973 serdes2_prtcl == 0x49)
974 sgmii_configure_repeater(2);
977 #endif // !CONFIG_DM_ETH
982 return pci_eth_init(bis);
986 #if defined(CONFIG_RESET_PHY_R)
991 #endif /* CONFIG_RESET_PHY_R */
993 #if defined(CONFIG_DM_ETH) && defined(CONFIG_MULTI_DTB_FIT)
995 /* Structure to hold SERDES protocols supported in case of
996 * CONFIG_DM_ETH enabled (network interfaces are described in the DTS).
998 * @serdes_block: the index of the SERDES block
999 * @serdes_protocol: the decimal value of the protocol supported
1000 * @dts_needed: DTS notes describing the current configuration are needed
1002 * When dts_needed is true, the board_fit_config_name_match() function
1003 * will try to exactly match the current configuration of the block with a DTS
1006 static struct serdes_configuration {
1008 u32 serdes_protocol;
1010 } supported_protocols[] = {
1011 /* Serdes block #1 */
1014 /* Serdes block #2 */
1018 #define SUPPORTED_SERDES_PROTOCOLS ARRAY_SIZE(supported_protocols)
1020 static bool protocol_supported(u8 serdes_block, u32 protocol)
1022 struct serdes_configuration serdes_conf;
1025 for (i = 0; i < SUPPORTED_SERDES_PROTOCOLS; i++) {
1026 serdes_conf = supported_protocols[i];
1027 if (serdes_conf.serdes_block == serdes_block &&
1028 serdes_conf.serdes_protocol == protocol)
1035 static void get_str_protocol(u8 serdes_block, u32 protocol, char *str)
1037 struct serdes_configuration serdes_conf;
1040 for (i = 0; i < SUPPORTED_SERDES_PROTOCOLS; i++) {
1041 serdes_conf = supported_protocols[i];
1042 if (serdes_conf.serdes_block == serdes_block &&
1043 serdes_conf.serdes_protocol == protocol) {
1044 if (serdes_conf.dts_needed == true)
1045 sprintf(str, "%u", protocol);
1053 int board_fit_config_name_match(const char *name)
1055 struct ccsr_gur *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR);
1056 u32 rcw_status = in_le32(&gur->rcwsr[28]);
1057 char srds_s1_str[2], srds_s2_str[2];
1058 u32 srds_s1, srds_s2;
1059 char expected_dts[100];
1061 srds_s1 = rcw_status & FSL_CHASSIS3_RCWSR28_SRDS1_PRTCL_MASK;
1062 srds_s1 >>= FSL_CHASSIS3_RCWSR28_SRDS1_PRTCL_SHIFT;
1064 srds_s2 = rcw_status & FSL_CHASSIS3_RCWSR28_SRDS2_PRTCL_MASK;
1065 srds_s2 >>= FSL_CHASSIS3_RCWSR28_SRDS2_PRTCL_SHIFT;
1067 /* Check for supported protocols. The default DTS will be used
1070 if (!protocol_supported(1, srds_s1) ||
1071 !protocol_supported(2, srds_s2))
1074 get_str_protocol(1, srds_s1, srds_s1_str);
1075 get_str_protocol(2, srds_s2, srds_s2_str);
1077 printf("expected_dts %s\n", expected_dts);
1078 sprintf(expected_dts, "fsl-ls2080a-qds-%s-%s",
1079 srds_s1_str, srds_s2_str);
1081 if (!strcmp(name, expected_dts))
1084 printf("this is not!\n");