1 // SPDX-License-Identifier: GPL-2.0+
3 * Copyright 2015 Freescale Semiconductor, Inc.
9 #include <asm/arch/fsl_serdes.h>
16 #include <fsl-mc/fsl_mc.h>
17 #include <fsl-mc/ldpaa_wriop.h>
19 #include "../common/qixis.h"
21 #include "ls2080aqds_qixis.h"
23 #define MC_BOOT_ENV_VAR "mcinitcmd"
25 #if defined(CONFIG_FSL_MC_ENET) && !defined(CONFIG_SPL_BUILD)
26 /* - In LS2080A there are only 16 SERDES lanes, spread across 2 SERDES banks.
27 * Bank 1 -> Lanes A, B, C, D, E, F, G, H
28 * Bank 2 -> Lanes A,B, C, D, E, F, G, H
31 /* Mapping of 16 SERDES lanes to LS2080A QDS board slots. A value of '0' here
32 * means that the mapping must be determined dynamically, or that the lane
33 * maps to something other than a board slot.
36 static u8 lane_to_slot_fsm1[] = {
37 0, 0, 0, 0, 0, 0, 0, 0
40 static u8 lane_to_slot_fsm2[] = {
41 0, 0, 0, 0, 0, 0, 0, 0
44 /* On the Vitesse VSC8234XHG SGMII riser card there are 4 SGMII PHYs
48 static int xqsgii_riser_phy_addr[] = {
49 XQSGMII_CARD_PHY1_PORT0_ADDR,
50 XQSGMII_CARD_PHY2_PORT0_ADDR,
51 XQSGMII_CARD_PHY3_PORT0_ADDR,
52 XQSGMII_CARD_PHY4_PORT0_ADDR,
53 XQSGMII_CARD_PHY3_PORT2_ADDR,
54 XQSGMII_CARD_PHY1_PORT2_ADDR,
55 XQSGMII_CARD_PHY4_PORT2_ADDR,
56 XQSGMII_CARD_PHY2_PORT2_ADDR,
59 static int sgmii_riser_phy_addr[] = {
60 SGMII_CARD_PORT1_PHY_ADDR,
61 SGMII_CARD_PORT2_PHY_ADDR,
62 SGMII_CARD_PORT3_PHY_ADDR,
63 SGMII_CARD_PORT4_PHY_ADDR,
66 /* Slot2 does not have EMI connections */
77 static const char * const mdio_names[] = {
84 DEFAULT_WRIOP_MDIO2_NAME,
87 struct ls2080a_qds_mdio {
89 struct mii_dev *realbus;
92 static void sgmii_configure_repeater(int serdes_port)
97 int dpmac_id = 0, dpmac, mii_bus = 0;
99 char dev[2][20] = {"LS2080A_QDS_MDIO0", "LS2080A_QDS_MDIO3"};
100 uint8_t i2c_addr[] = {0x58, 0x59, 0x5a, 0x5b, 0x5c, 0x5d, 0x5f, 0x60};
102 uint8_t ch_a_eq[] = {0x1, 0x2, 0x3, 0x7};
103 uint8_t ch_a_ctl2[] = {0x81, 0x82, 0x83, 0x84};
104 uint8_t ch_b_eq[] = {0x1, 0x2, 0x3, 0x7};
105 uint8_t ch_b_ctl2[] = {0x81, 0x82, 0x83, 0x84};
107 int *riser_phy_addr = &xqsgii_riser_phy_addr[0];
109 /* Set I2c to Slot 1 */
110 i2c_write(0x77, 0, 0, &a, 1);
112 for (dpmac = 0; dpmac < 8; dpmac++) {
113 /* Check the PHY status */
114 switch (serdes_port) {
117 dpmac_id = dpmac + 1;
121 dpmac_id = dpmac + 9;
123 i2c_write(0x76, 0, 0, &a, 1);
127 ret = miiphy_set_current_dev(dev[mii_bus]);
131 bus = mdio_get_current_dev();
132 debug("Reading from bus %s\n", bus->name);
134 ret = miiphy_write(dev[mii_bus], riser_phy_addr[dpmac], 0x1f,
140 ret = miiphy_read(dev[mii_bus], riser_phy_addr[dpmac], 0x11,
147 if ((value & 0xfff) == 0x401) {
148 printf("DPMAC %d:PHY is ..... Configured\n", dpmac_id);
149 miiphy_write(dev[mii_bus], riser_phy_addr[dpmac],
154 for (i = 0; i < 4; i++) {
155 for (j = 0; j < 4; j++) {
157 i2c_write(i2c_addr[dpmac], 6, 1, &a, 1);
159 i2c_write(i2c_addr[dpmac], 4, 1, &a, 1);
161 i2c_write(i2c_addr[dpmac], 8, 1, &a, 1);
163 i2c_write(i2c_addr[dpmac], 0xf, 1,
165 i2c_write(i2c_addr[dpmac], 0x11, 1,
168 i2c_write(i2c_addr[dpmac], 0x16, 1,
170 i2c_write(i2c_addr[dpmac], 0x18, 1,
174 i2c_write(i2c_addr[dpmac], 0x23, 1, &a, 1);
176 i2c_write(i2c_addr[dpmac], 0x2d, 1, &a, 1);
178 i2c_write(i2c_addr[dpmac], 4, 1, &a, 1);
180 ret = miiphy_read(dev[mii_bus],
181 riser_phy_addr[dpmac],
187 ret = miiphy_read(dev[mii_bus],
188 riser_phy_addr[dpmac],
193 if ((value & 0xfff) == 0x401) {
194 printf("DPMAC %d :PHY is configured ",
196 printf("after setting repeater 0x%x\n",
201 printf("DPMAC %d :PHY is failed to ",
203 printf("configure the repeater 0x%x\n",
208 miiphy_write(dev[mii_bus], riser_phy_addr[dpmac], 0x1f, 0);
212 printf("DPMAC %d ..... FAILED to configure PHY\n", dpmac_id);
216 static void qsgmii_configure_repeater(int dpmac)
220 int i2c_phy_addr = 0;
222 int i2c_addr[] = {0x58, 0x59, 0x5a, 0x5b};
224 uint8_t ch_a_eq[] = {0x1, 0x2, 0x3, 0x7};
225 uint8_t ch_a_ctl2[] = {0x81, 0x82, 0x83, 0x84};
226 uint8_t ch_b_eq[] = {0x1, 0x2, 0x3, 0x7};
227 uint8_t ch_b_ctl2[] = {0x81, 0x82, 0x83, 0x84};
229 const char *dev = "LS2080A_QDS_MDIO0";
231 unsigned short value;
233 /* Set I2c to Slot 1 */
234 i2c_write(0x77, 0, 0, &a, 1);
241 i2c_phy_addr = i2c_addr[0];
249 i2c_phy_addr = i2c_addr[1];
257 i2c_phy_addr = i2c_addr[2];
265 i2c_phy_addr = i2c_addr[3];
270 /* Check the PHY status */
271 ret = miiphy_set_current_dev(dev);
272 ret = miiphy_write(dev, phy_addr, 0x1f, 3);
274 ret = miiphy_read(dev, phy_addr, 0x11, &value);
276 ret = miiphy_read(dev, phy_addr, 0x11, &value);
278 if ((value & 0xf) == 0xf) {
279 printf("DPMAC %d :PHY is ..... Configured\n", dpmac);
283 for (i = 0; i < 4; i++) {
284 for (j = 0; j < 4; j++) {
286 i2c_write(i2c_phy_addr, 6, 1, &a, 1);
288 i2c_write(i2c_phy_addr, 4, 1, &a, 1);
290 i2c_write(i2c_phy_addr, 8, 1, &a, 1);
292 i2c_write(i2c_phy_addr, 0xf, 1, &ch_a_eq[i], 1);
293 i2c_write(i2c_phy_addr, 0x11, 1, &ch_a_ctl2[j], 1);
295 i2c_write(i2c_phy_addr, 0x16, 1, &ch_b_eq[i], 1);
296 i2c_write(i2c_phy_addr, 0x18, 1, &ch_b_ctl2[j], 1);
299 i2c_write(i2c_phy_addr, 0x23, 1, &a, 1);
301 i2c_write(i2c_phy_addr, 0x2d, 1, &a, 1);
303 i2c_write(i2c_phy_addr, 4, 1, &a, 1);
305 ret = miiphy_read(dev, phy_addr, 0x11, &value);
309 ret = miiphy_read(dev, phy_addr, 0x11, &value);
313 if ((value & 0xf) == 0xf) {
314 printf("DPMAC %d :PHY is ..... Configured\n",
321 printf("DPMAC %d :PHY ..... FAILED to configure PHY\n", dpmac);
325 static const char *ls2080a_qds_mdio_name_for_muxval(u8 muxval)
327 return mdio_names[muxval];
330 struct mii_dev *mii_dev_for_muxval(u8 muxval)
333 const char *name = ls2080a_qds_mdio_name_for_muxval(muxval);
336 printf("No bus for muxval %x\n", muxval);
340 bus = miiphy_get_dev_by_name(name);
343 printf("No bus by name %s\n", name);
350 static void ls2080a_qds_enable_SFP_TX(u8 muxval)
354 brdcfg9 = QIXIS_READ(brdcfg[9]);
355 brdcfg9 &= ~BRDCFG9_SFPTX_MASK;
356 brdcfg9 |= (muxval << BRDCFG9_SFPTX_SHIFT);
357 QIXIS_WRITE(brdcfg[9], brdcfg9);
360 static void ls2080a_qds_mux_mdio(u8 muxval)
365 brdcfg4 = QIXIS_READ(brdcfg[4]);
366 brdcfg4 &= ~BRDCFG4_EMISEL_MASK;
367 brdcfg4 |= (muxval << BRDCFG4_EMISEL_SHIFT);
368 QIXIS_WRITE(brdcfg[4], brdcfg4);
372 static int ls2080a_qds_mdio_read(struct mii_dev *bus, int addr,
373 int devad, int regnum)
375 struct ls2080a_qds_mdio *priv = bus->priv;
377 ls2080a_qds_mux_mdio(priv->muxval);
379 return priv->realbus->read(priv->realbus, addr, devad, regnum);
382 static int ls2080a_qds_mdio_write(struct mii_dev *bus, int addr, int devad,
383 int regnum, u16 value)
385 struct ls2080a_qds_mdio *priv = bus->priv;
387 ls2080a_qds_mux_mdio(priv->muxval);
389 return priv->realbus->write(priv->realbus, addr, devad, regnum, value);
392 static int ls2080a_qds_mdio_reset(struct mii_dev *bus)
394 struct ls2080a_qds_mdio *priv = bus->priv;
396 return priv->realbus->reset(priv->realbus);
399 static int ls2080a_qds_mdio_init(char *realbusname, u8 muxval)
401 struct ls2080a_qds_mdio *pmdio;
402 struct mii_dev *bus = mdio_alloc();
405 printf("Failed to allocate ls2080a_qds MDIO bus\n");
409 pmdio = malloc(sizeof(*pmdio));
411 printf("Failed to allocate ls2080a_qds private data\n");
416 bus->read = ls2080a_qds_mdio_read;
417 bus->write = ls2080a_qds_mdio_write;
418 bus->reset = ls2080a_qds_mdio_reset;
419 strcpy(bus->name, ls2080a_qds_mdio_name_for_muxval(muxval));
421 pmdio->realbus = miiphy_get_dev_by_name(realbusname);
423 if (!pmdio->realbus) {
424 printf("No bus with name %s\n", realbusname);
430 pmdio->muxval = muxval;
433 return mdio_register(bus);
437 * Initialize the dpmac_info array.
440 static void initialize_dpmac_to_slot(void)
442 struct ccsr_gur __iomem *gur = (void *)CONFIG_SYS_FSL_GUTS_ADDR;
443 int serdes1_prtcl = (in_le32(&gur->rcwsr[28]) &
444 FSL_CHASSIS3_RCWSR28_SRDS1_PRTCL_MASK)
445 >> FSL_CHASSIS3_RCWSR28_SRDS1_PRTCL_SHIFT;
446 int serdes2_prtcl = (in_le32(&gur->rcwsr[28]) &
447 FSL_CHASSIS3_RCWSR28_SRDS2_PRTCL_MASK)
448 >> FSL_CHASSIS3_RCWSR28_SRDS2_PRTCL_SHIFT;
451 env_hwconfig = env_get("hwconfig");
453 switch (serdes1_prtcl) {
457 printf("qds: WRIOP: Supported SerDes1 Protocol 0x%02x\n",
459 lane_to_slot_fsm1[0] = EMI1_SLOT1;
460 lane_to_slot_fsm1[1] = EMI1_SLOT1;
461 lane_to_slot_fsm1[2] = EMI1_SLOT1;
462 lane_to_slot_fsm1[3] = EMI1_SLOT1;
463 if (hwconfig_f("xqsgmii", env_hwconfig)) {
464 lane_to_slot_fsm1[4] = EMI1_SLOT1;
465 lane_to_slot_fsm1[5] = EMI1_SLOT1;
466 lane_to_slot_fsm1[6] = EMI1_SLOT1;
467 lane_to_slot_fsm1[7] = EMI1_SLOT1;
469 lane_to_slot_fsm1[4] = EMI1_SLOT2;
470 lane_to_slot_fsm1[5] = EMI1_SLOT2;
471 lane_to_slot_fsm1[6] = EMI1_SLOT2;
472 lane_to_slot_fsm1[7] = EMI1_SLOT2;
477 printf("qds: WRIOP: Supported SerDes1 Protocol 0x%02x\n",
479 if (hwconfig_f("xqsgmii", env_hwconfig)) {
480 lane_to_slot_fsm1[0] = EMI1_SLOT3;
481 lane_to_slot_fsm1[1] = EMI1_SLOT3;
482 lane_to_slot_fsm1[2] = EMI1_SLOT3;
483 lane_to_slot_fsm1[3] = EMI_NONE;
485 lane_to_slot_fsm1[0] = EMI_NONE;
486 lane_to_slot_fsm1[1] = EMI_NONE;
487 lane_to_slot_fsm1[2] = EMI_NONE;
488 lane_to_slot_fsm1[3] = EMI_NONE;
490 lane_to_slot_fsm1[4] = EMI1_SLOT3;
491 lane_to_slot_fsm1[5] = EMI1_SLOT3;
492 lane_to_slot_fsm1[6] = EMI1_SLOT3;
493 lane_to_slot_fsm1[7] = EMI_NONE;
497 printf("qds: WRIOP: Supported SerDes1 Protocol 0x%02x\n",
499 if (hwconfig_f("xqsgmii", env_hwconfig)) {
500 lane_to_slot_fsm1[0] = EMI1_SLOT3;
501 lane_to_slot_fsm1[1] = EMI1_SLOT3;
502 lane_to_slot_fsm1[2] = EMI_NONE;
503 lane_to_slot_fsm1[3] = EMI_NONE;
505 lane_to_slot_fsm1[0] = EMI_NONE;
506 lane_to_slot_fsm1[1] = EMI_NONE;
507 lane_to_slot_fsm1[2] = EMI_NONE;
508 lane_to_slot_fsm1[3] = EMI_NONE;
510 lane_to_slot_fsm1[4] = EMI1_SLOT3;
511 lane_to_slot_fsm1[5] = EMI1_SLOT3;
512 lane_to_slot_fsm1[6] = EMI_NONE;
513 lane_to_slot_fsm1[7] = EMI_NONE;
519 printf("qds: WRIOP: Supported SerDes1 Protocol 0x%02x\n",
523 printf("%s qds: WRIOP: Unsupported SerDes1 Protocol 0x%02x\n",
524 __func__, serdes1_prtcl);
528 switch (serdes2_prtcl) {
533 printf("qds: WRIOP: Supported SerDes2 Protocol 0x%02x\n",
535 lane_to_slot_fsm2[0] = EMI1_SLOT4;
536 lane_to_slot_fsm2[1] = EMI1_SLOT4;
537 lane_to_slot_fsm2[2] = EMI1_SLOT4;
538 lane_to_slot_fsm2[3] = EMI1_SLOT4;
540 if (hwconfig_f("xqsgmii", env_hwconfig)) {
541 lane_to_slot_fsm2[4] = EMI1_SLOT4;
542 lane_to_slot_fsm2[5] = EMI1_SLOT4;
543 lane_to_slot_fsm2[6] = EMI1_SLOT4;
544 lane_to_slot_fsm2[7] = EMI1_SLOT4;
546 /* No MDIO physical connection */
547 lane_to_slot_fsm2[4] = EMI1_SLOT6;
548 lane_to_slot_fsm2[5] = EMI1_SLOT6;
549 lane_to_slot_fsm2[6] = EMI1_SLOT6;
550 lane_to_slot_fsm2[7] = EMI1_SLOT6;
555 printf("qds: WRIOP: Supported SerDes2 Protocol 0x%02x\n",
557 lane_to_slot_fsm2[0] = EMI_NONE;
558 lane_to_slot_fsm2[1] = EMI1_SLOT5;
559 lane_to_slot_fsm2[2] = EMI1_SLOT5;
560 lane_to_slot_fsm2[3] = EMI1_SLOT5;
562 if (hwconfig_f("xqsgmii", env_hwconfig)) {
563 lane_to_slot_fsm2[4] = EMI_NONE;
564 lane_to_slot_fsm2[5] = EMI1_SLOT5;
565 lane_to_slot_fsm2[6] = EMI1_SLOT5;
566 lane_to_slot_fsm2[7] = EMI1_SLOT5;
571 printf("qds: WRIOP: Supported SerDes2 Protocol 0x%02x\n",
573 if (hwconfig_f("xqsgmii", env_hwconfig)) {
574 lane_to_slot_fsm2[0] = EMI_NONE;
575 lane_to_slot_fsm2[1] = EMI_NONE;
576 lane_to_slot_fsm2[2] = EMI_NONE;
577 lane_to_slot_fsm2[3] = EMI_NONE;
579 lane_to_slot_fsm2[4] = EMI_NONE;
580 lane_to_slot_fsm2[5] = EMI_NONE;
581 lane_to_slot_fsm2[6] = EMI1_SLOT5;
582 lane_to_slot_fsm2[7] = EMI1_SLOT5;
586 printf(" %s qds: WRIOP: Unsupported SerDes2 Protocol 0x%02x\n",
587 __func__ , serdes2_prtcl);
592 void ls2080a_handle_phy_interface_sgmii(int dpmac_id)
596 struct ccsr_gur __iomem *gur = (void *)CONFIG_SYS_FSL_GUTS_ADDR;
597 int serdes1_prtcl = (in_le32(&gur->rcwsr[28]) &
598 FSL_CHASSIS3_RCWSR28_SRDS1_PRTCL_MASK)
599 >> FSL_CHASSIS3_RCWSR28_SRDS1_PRTCL_SHIFT;
600 int serdes2_prtcl = (in_le32(&gur->rcwsr[28]) &
601 FSL_CHASSIS3_RCWSR28_SRDS2_PRTCL_MASK)
602 >> FSL_CHASSIS3_RCWSR28_SRDS2_PRTCL_SHIFT;
605 char *env_hwconfig = env_get("hwconfig");
607 if (hwconfig_f("xqsgmii", env_hwconfig))
608 riser_phy_addr = &xqsgii_riser_phy_addr[0];
610 riser_phy_addr = &sgmii_riser_phy_addr[0];
612 if (dpmac_id > WRIOP1_DPMAC9)
615 switch (serdes1_prtcl) {
619 lane = serdes_get_first_lane(FSL_SRDS_1, SGMII1 + dpmac_id - 1);
621 slot = lane_to_slot_fsm1[lane];
625 /* Slot housing a SGMII riser card? */
626 wriop_set_phy_address(dpmac_id, 0,
627 riser_phy_addr[dpmac_id - 1]);
628 dpmac_info[dpmac_id].board_mux = EMI1_SLOT1;
629 bus = mii_dev_for_muxval(EMI1_SLOT1);
630 wriop_set_mdio(dpmac_id, bus);
633 /* Slot housing a SGMII riser card? */
634 wriop_set_phy_address(dpmac_id, 0,
635 riser_phy_addr[dpmac_id - 1]);
636 dpmac_info[dpmac_id].board_mux = EMI1_SLOT2;
637 bus = mii_dev_for_muxval(EMI1_SLOT2);
638 wriop_set_mdio(dpmac_id, bus);
641 if (slot == EMI_NONE)
643 if (serdes1_prtcl == 0x39) {
644 wriop_set_phy_address(dpmac_id, 0,
645 riser_phy_addr[dpmac_id - 2]);
646 if (dpmac_id >= 6 && hwconfig_f("xqsgmii",
648 wriop_set_phy_address(dpmac_id, 0,
649 riser_phy_addr[dpmac_id - 3]);
651 wriop_set_phy_address(dpmac_id, 0,
652 riser_phy_addr[dpmac_id - 2]);
653 if (dpmac_id >= 7 && hwconfig_f("xqsgmii",
655 wriop_set_phy_address(dpmac_id, 0,
656 riser_phy_addr[dpmac_id - 3]);
658 dpmac_info[dpmac_id].board_mux = EMI1_SLOT3;
659 bus = mii_dev_for_muxval(EMI1_SLOT3);
660 wriop_set_mdio(dpmac_id, bus);
671 printf("%s qds: WRIOP: Unsupported SerDes1 Protocol 0x%02x\n",
672 __func__ , serdes1_prtcl);
677 switch (serdes2_prtcl) {
683 lane = serdes_get_first_lane(FSL_SRDS_2, SGMII9 +
685 slot = lane_to_slot_fsm2[lane];
693 /* Slot housing a SGMII riser card? */
694 wriop_set_phy_address(dpmac_id, 0,
695 riser_phy_addr[dpmac_id - 9]);
696 dpmac_info[dpmac_id].board_mux = EMI1_SLOT4;
697 bus = mii_dev_for_muxval(EMI1_SLOT4);
698 wriop_set_mdio(dpmac_id, bus);
701 if (slot == EMI_NONE)
703 if (serdes2_prtcl == 0x47) {
704 wriop_set_phy_address(dpmac_id, 0,
705 riser_phy_addr[dpmac_id - 10]);
706 if (dpmac_id >= 14 && hwconfig_f("xqsgmii",
708 wriop_set_phy_address(dpmac_id, 0,
709 riser_phy_addr[dpmac_id - 11]);
711 wriop_set_phy_address(dpmac_id, 0,
712 riser_phy_addr[dpmac_id - 11]);
714 dpmac_info[dpmac_id].board_mux = EMI1_SLOT5;
715 bus = mii_dev_for_muxval(EMI1_SLOT5);
716 wriop_set_mdio(dpmac_id, bus);
719 /* Slot housing a SGMII riser card? */
720 wriop_set_phy_address(dpmac_id, 0,
721 riser_phy_addr[dpmac_id - 13]);
722 dpmac_info[dpmac_id].board_mux = EMI1_SLOT6;
723 bus = mii_dev_for_muxval(EMI1_SLOT6);
724 wriop_set_mdio(dpmac_id, bus);
729 printf("%s qds: WRIOP: Unsupported SerDes2 Protocol 0x%02x\n",
730 __func__, serdes2_prtcl);
735 void ls2080a_handle_phy_interface_qsgmii(int dpmac_id)
739 struct ccsr_gur __iomem *gur = (void *)CONFIG_SYS_FSL_GUTS_ADDR;
740 int serdes1_prtcl = (in_le32(&gur->rcwsr[28]) &
741 FSL_CHASSIS3_RCWSR28_SRDS1_PRTCL_MASK)
742 >> FSL_CHASSIS3_RCWSR28_SRDS1_PRTCL_SHIFT;
744 switch (serdes1_prtcl) {
751 lane = serdes_get_first_lane(FSL_SRDS_1, QSGMII_A);
757 lane = serdes_get_first_lane(FSL_SRDS_1, QSGMII_B);
763 lane = serdes_get_first_lane(FSL_SRDS_1, QSGMII_C);
769 lane = serdes_get_first_lane(FSL_SRDS_1, QSGMII_D);
773 slot = lane_to_slot_fsm1[lane];
777 /* Slot housing a QSGMII riser card? */
778 wriop_set_phy_address(dpmac_id, 0, dpmac_id - 1);
779 dpmac_info[dpmac_id].board_mux = EMI1_SLOT1;
780 bus = mii_dev_for_muxval(EMI1_SLOT1);
781 wriop_set_mdio(dpmac_id, bus);
794 printf("qds: WRIOP: Unsupported SerDes Protocol 0x%02x\n",
799 qsgmii_configure_repeater(dpmac_id);
802 void ls2080a_handle_phy_interface_xsgmii(int i)
804 struct ccsr_gur __iomem *gur = (void *)CONFIG_SYS_FSL_GUTS_ADDR;
805 int serdes1_prtcl = (in_le32(&gur->rcwsr[28]) &
806 FSL_CHASSIS3_RCWSR28_SRDS1_PRTCL_MASK)
807 >> FSL_CHASSIS3_RCWSR28_SRDS1_PRTCL_SHIFT;
809 switch (serdes1_prtcl) {
814 * XFI does not need a PHY to work, but to avoid U-Boot use
815 * default PHY address which is zero to a MAC when it found
816 * a MAC has no PHY address, we give a PHY address to XFI
817 * MAC, and should not use a real XAUI PHY address, since
818 * MDIO can access it successfully, and then MDIO thinks
819 * the XAUI card is used for the XFI MAC, which will cause
822 wriop_set_phy_address(i, 0, i + 4);
823 ls2080a_qds_enable_SFP_TX(SFP_TX);
827 printf("qds: WRIOP: Unsupported SerDes Protocol 0x%02x\n",
834 int board_eth_init(bd_t *bis)
837 #if defined(CONFIG_FSL_MC_ENET) && !defined(CONFIG_SPL_BUILD)
838 struct ccsr_gur __iomem *gur = (void *)CONFIG_SYS_FSL_GUTS_ADDR;
839 int serdes1_prtcl = (in_le32(&gur->rcwsr[28]) &
840 FSL_CHASSIS3_RCWSR28_SRDS1_PRTCL_MASK)
841 >> FSL_CHASSIS3_RCWSR28_SRDS1_PRTCL_SHIFT;
842 int serdes2_prtcl = (in_le32(&gur->rcwsr[28]) &
843 FSL_CHASSIS3_RCWSR28_SRDS2_PRTCL_MASK)
844 >> FSL_CHASSIS3_RCWSR28_SRDS2_PRTCL_SHIFT;
846 struct memac_mdio_info *memac_mdio0_info;
847 struct memac_mdio_info *memac_mdio1_info;
851 env_hwconfig = env_get("hwconfig");
853 initialize_dpmac_to_slot();
855 memac_mdio0_info = (struct memac_mdio_info *)malloc(
856 sizeof(struct memac_mdio_info));
857 memac_mdio0_info->regs =
858 (struct memac_mdio_controller *)
859 CONFIG_SYS_FSL_WRIOP1_MDIO1;
860 memac_mdio0_info->name = DEFAULT_WRIOP_MDIO1_NAME;
862 /* Register the real MDIO1 bus */
863 fm_memac_mdio_init(bis, memac_mdio0_info);
865 memac_mdio1_info = (struct memac_mdio_info *)malloc(
866 sizeof(struct memac_mdio_info));
867 memac_mdio1_info->regs =
868 (struct memac_mdio_controller *)
869 CONFIG_SYS_FSL_WRIOP1_MDIO2;
870 memac_mdio1_info->name = DEFAULT_WRIOP_MDIO2_NAME;
872 /* Register the real MDIO2 bus */
873 fm_memac_mdio_init(bis, memac_mdio1_info);
875 /* Register the muxing front-ends to the MDIO buses */
876 ls2080a_qds_mdio_init(DEFAULT_WRIOP_MDIO1_NAME, EMI1_SLOT1);
877 ls2080a_qds_mdio_init(DEFAULT_WRIOP_MDIO1_NAME, EMI1_SLOT2);
878 ls2080a_qds_mdio_init(DEFAULT_WRIOP_MDIO1_NAME, EMI1_SLOT3);
879 ls2080a_qds_mdio_init(DEFAULT_WRIOP_MDIO1_NAME, EMI1_SLOT4);
880 ls2080a_qds_mdio_init(DEFAULT_WRIOP_MDIO1_NAME, EMI1_SLOT5);
881 ls2080a_qds_mdio_init(DEFAULT_WRIOP_MDIO1_NAME, EMI1_SLOT6);
883 ls2080a_qds_mdio_init(DEFAULT_WRIOP_MDIO2_NAME, EMI2);
885 for (i = WRIOP1_DPMAC1; i < NUM_WRIOP_PORTS; i++) {
886 switch (wriop_get_enet_if(i)) {
887 case PHY_INTERFACE_MODE_QSGMII:
888 ls2080a_handle_phy_interface_qsgmii(i);
890 case PHY_INTERFACE_MODE_SGMII:
891 ls2080a_handle_phy_interface_sgmii(i);
893 case PHY_INTERFACE_MODE_XGMII:
894 ls2080a_handle_phy_interface_xsgmii(i);
904 error = cpu_eth_init(bis);
906 if (hwconfig_f("xqsgmii", env_hwconfig)) {
907 if (serdes1_prtcl == 0x7)
908 sgmii_configure_repeater(1);
909 if (serdes2_prtcl == 0x7 || serdes2_prtcl == 0x8 ||
910 serdes2_prtcl == 0x49)
911 sgmii_configure_repeater(2);
914 error = pci_eth_init(bis);
918 #if defined(CONFIG_RESET_PHY_R)
923 #endif /* CONFIG_RESET_PHY_R */