board/freescale/ls2080aqds/ddr.c

   1 // SPDX-License-Identifier: GPL-2.0+
   2 /*
   3  * Copyright 2015 Freescale Semiconductor, Inc.
   4  */
   5
   6 #include <common.h>
   7 #include <fsl_ddr_sdram.h>
   8 #include <fsl_ddr_dimm_params.h>
   9 #include <log.h>
  10 #include <asm/arch/soc.h>
  11 #include <asm/arch/clock.h>
  12 #include <asm/global_data.h>
  13 #include "ddr.h"
  14
  15 DECLARE_GLOBAL_DATA_PTR;
  16
  17 void fsl_ddr_board_options(memctl_options_t *popts,
  18                                 dimm_params_t *pdimm,
  19                                 unsigned int ctrl_num)
  20 {
  21 #ifdef CONFIG_SYS_FSL_HAS_DP_DDR
  22         u8 dq_mapping_0, dq_mapping_2, dq_mapping_3;
  23 #endif
  24         const struct board_specific_parameters *pbsp, *pbsp_highest = NULL;
  25         ulong ddr_freq;
  26         int slot;
  27
  28         if (ctrl_num > 2) {
  29                 printf("Not supported controller number %d\n", ctrl_num);
  30                 return;
  31         }
  32
  33         for (slot = 0; slot < CONFIG_DIMM_SLOTS_PER_CTLR; slot++) {
  34                 if (pdimm[slot].n_ranks)
  35                         break;
  36         }
  37
  38         if (slot >= CONFIG_DIMM_SLOTS_PER_CTLR)
  39                 return;
  40
  41         /*
  42          * we use identical timing for all slots. If needed, change the code
  43          * to  pbsp = rdimms[ctrl_num] or pbsp = udimms[ctrl_num];
  44          */
  45         if (popts->registered_dimm_en)
  46                 pbsp = rdimms[ctrl_num];
  47         else
  48                 pbsp = udimms[ctrl_num];
  49
  50
  51         /* Get clk_adjust, wrlvl_start, wrlvl_ctl, according to the board ddr
  52          * freqency and n_banks specified in board_specific_parameters table.
  53          */
  54         ddr_freq = get_ddr_freq(ctrl_num) / 1000000;
  55         while (pbsp->datarate_mhz_high) {
  56                 if (pbsp->n_ranks == pdimm[slot].n_ranks &&
  57                     (pdimm[slot].rank_density >> 30) >= pbsp->rank_gb) {
  58                         if (ddr_freq <= pbsp->datarate_mhz_high) {
  59                                 popts->clk_adjust = pbsp->clk_adjust;
  60                                 popts->wrlvl_start = pbsp->wrlvl_start;
  61                                 popts->wrlvl_ctl_2 = pbsp->wrlvl_ctl_2;
  62                                 popts->wrlvl_ctl_3 = pbsp->wrlvl_ctl_3;
  63                                 goto found;
  64                         }
  65                         pbsp_highest = pbsp;
  66                 }
  67                 pbsp++;
  68         }
  69
  70         if (pbsp_highest) {
  71                 printf("Error: board specific timing not found for data rate %lu MT/s\n"
  72                         "Trying to use the highest speed (%u) parameters\n",
  73                         ddr_freq, pbsp_highest->datarate_mhz_high);
  74                 popts->clk_adjust = pbsp_highest->clk_adjust;
  75                 popts->wrlvl_start = pbsp_highest->wrlvl_start;
  76                 popts->wrlvl_ctl_2 = pbsp->wrlvl_ctl_2;
  77                 popts->wrlvl_ctl_3 = pbsp->wrlvl_ctl_3;
  78         } else {
  79                 panic("DIMM is not supported by this board");
  80         }
  81 found:
  82         debug("Found timing match: n_ranks %d, data rate %d, rank_gb %d\n"
  83                 "\tclk_adjust %d, wrlvl_start %d, wrlvl_ctrl_2 0x%x, wrlvl_ctrl_3 0x%x\n",
  84                 pbsp->n_ranks, pbsp->datarate_mhz_high, pbsp->rank_gb,
  85                 pbsp->clk_adjust, pbsp->wrlvl_start, pbsp->wrlvl_ctl_2,
  86                 pbsp->wrlvl_ctl_3);
  87 #ifdef CONFIG_SYS_FSL_HAS_DP_DDR
  88         if (ctrl_num == CONFIG_DP_DDR_CTRL) {
  89                 /* force DDR bus width to 32 bits */
  90                 popts->data_bus_width = 1;
  91                 popts->otf_burst_chop_en = 0;
  92                 popts->burst_length = DDR_BL8;
  93                 popts->bstopre = 0;     /* enable auto precharge */
  94                 /*
  95                  * Layout optimization results byte mapping
  96                  * Byte 0 -> Byte ECC
  97                  * Byte 1 -> Byte 3
  98                  * Byte 2 -> Byte 2
  99                  * Byte 3 -> Byte 1
 100                  * Byte ECC -> Byte 0
 101                  */
 102                 dq_mapping_0 = pdimm[slot].dq_mapping[0];
 103                 dq_mapping_2 = pdimm[slot].dq_mapping[2];
 104                 dq_mapping_3 = pdimm[slot].dq_mapping[3];
 105                 pdimm[slot].dq_mapping[0] = pdimm[slot].dq_mapping[8];
 106                 pdimm[slot].dq_mapping[1] = pdimm[slot].dq_mapping[9];
 107                 pdimm[slot].dq_mapping[2] = pdimm[slot].dq_mapping[6];
 108                 pdimm[slot].dq_mapping[3] = pdimm[slot].dq_mapping[7];
 109                 pdimm[slot].dq_mapping[6] = dq_mapping_2;
 110                 pdimm[slot].dq_mapping[7] = dq_mapping_3;
 111                 pdimm[slot].dq_mapping[8] = dq_mapping_0;
 112                 pdimm[slot].dq_mapping[9] = 0;
 113                 pdimm[slot].dq_mapping[10] = 0;
 114                 pdimm[slot].dq_mapping[11] = 0;
 115                 pdimm[slot].dq_mapping[12] = 0;
 116                 pdimm[slot].dq_mapping[13] = 0;
 117                 pdimm[slot].dq_mapping[14] = 0;
 118                 pdimm[slot].dq_mapping[15] = 0;
 119                 pdimm[slot].dq_mapping[16] = 0;
 120                 pdimm[slot].dq_mapping[17] = 0;
 121         }
 122 #endif
 123         /* To work at higher than 1333MT/s */
 124         popts->half_strength_driver_enable = 0;
 125         /*
 126          * Write leveling override
 127          */
 128         popts->wrlvl_override = 1;
 129         popts->wrlvl_sample = 0x0;      /* 32 clocks */
 130
 131         /*
 132          * Rtt and Rtt_WR override
 133          */
 134         popts->rtt_override = 0;
 135
 136         /* Enable ZQ calibration */
 137         popts->zq_en = 1;
 138
 139         if (ddr_freq < 2350) {
 140                 if (pdimm[0].n_ranks == 2 && pdimm[1].n_ranks == 2) {
 141                         /* four chip-selects */
 142                         popts->ddr_cdr1 = DDR_CDR1_DHC_EN |
 143                                           DDR_CDR1_ODT(DDR_CDR_ODT_80ohm);
 144                         popts->ddr_cdr2 = DDR_CDR2_ODT(DDR_CDR_ODT_80ohm);
 145                         popts->twot_en = 1; /* enable 2T timing */
 146                 } else {
 147                         popts->ddr_cdr1 = DDR_CDR1_DHC_EN |
 148                                           DDR_CDR1_ODT(DDR_CDR_ODT_60ohm);
 149                         popts->ddr_cdr2 = DDR_CDR2_ODT(DDR_CDR_ODT_60ohm) |
 150                                           DDR_CDR2_VREF_RANGE_2;
 151                 }
 152         } else {
 153                 popts->ddr_cdr1 = DDR_CDR1_DHC_EN |
 154                                   DDR_CDR1_ODT(DDR_CDR_ODT_100ohm);
 155                 popts->ddr_cdr2 = DDR_CDR2_ODT(DDR_CDR_ODT_100ohm) |
 156                                   DDR_CDR2_VREF_RANGE_2;
 157         }
 158 }
 159
 160 #ifdef CONFIG_TFABOOT
 161 int fsl_initdram(void)
 162 {
 163         gd->ram_size = tfa_get_dram_size();
 164
 165         if (!gd->ram_size)
 166                 gd->ram_size = fsl_ddr_sdram_size();
 167
 168         return 0;
 169 }
 170 #else
 171 int fsl_initdram(void)
 172 {
 173 #if defined(CONFIG_SPL) && !defined(CONFIG_SPL_BUILD)
 174         gd->ram_size = fsl_ddr_sdram_size();
 175 #else
 176         puts("Initializing DDR....using SPD\n");
 177
 178         gd->ram_size = fsl_ddr_sdram();
 179 #endif
 180
 181         return 0;
 182 }
 183 #endif /* CONFIG_TFABOOT */