2 * Copyright 2014 Freescale Semiconductor, Inc.
4 * SPDX-License-Identifier: GPL-2.0+
8 #include <fsl_ddr_sdram.h>
9 #include <fsl_ddr_dimm_params.h>
10 #include <asm/arch/soc.h>
13 DECLARE_GLOBAL_DATA_PTR;
15 void fsl_ddr_board_options(memctl_options_t *popts,
17 unsigned int ctrl_num)
19 const struct board_specific_parameters *pbsp, *pbsp_highest = NULL;
23 printf("Not supported controller number %d\n", ctrl_num);
30 * we use identical timing for all slots. If needed, change the code
31 * to pbsp = rdimms[ctrl_num] or pbsp = udimms[ctrl_num];
33 if (popts->registered_dimm_en)
34 pbsp = rdimms[ctrl_num];
36 pbsp = udimms[ctrl_num];
39 /* Get clk_adjust, wrlvl_start, wrlvl_ctl, according to the board ddr
40 * freqency and n_banks specified in board_specific_parameters table.
42 ddr_freq = get_ddr_freq(0) / 1000000;
43 while (pbsp->datarate_mhz_high) {
44 if (pbsp->n_ranks == pdimm->n_ranks &&
45 (pdimm->rank_density >> 30) >= pbsp->rank_gb) {
46 if (ddr_freq <= pbsp->datarate_mhz_high) {
47 popts->clk_adjust = pbsp->clk_adjust;
48 popts->wrlvl_start = pbsp->wrlvl_start;
49 popts->wrlvl_ctl_2 = pbsp->wrlvl_ctl_2;
50 popts->wrlvl_ctl_3 = pbsp->wrlvl_ctl_3;
59 printf("Error: board specific timing not found for data rate %lu MT/s\n"
60 "Trying to use the highest speed (%u) parameters\n",
61 ddr_freq, pbsp_highest->datarate_mhz_high);
62 popts->clk_adjust = pbsp_highest->clk_adjust;
63 popts->wrlvl_start = pbsp_highest->wrlvl_start;
64 popts->wrlvl_ctl_2 = pbsp->wrlvl_ctl_2;
65 popts->wrlvl_ctl_3 = pbsp->wrlvl_ctl_3;
67 panic("DIMM is not supported by this board");
70 debug("Found timing match: n_ranks %d, data rate %d, rank_gb %d\n"
71 "\tclk_adjust %d, wrlvl_start %d, wrlvl_ctrl_2 0x%x, wrlvl_ctrl_3 0x%x\n",
72 pbsp->n_ranks, pbsp->datarate_mhz_high, pbsp->rank_gb,
73 pbsp->clk_adjust, pbsp->wrlvl_start, pbsp->wrlvl_ctl_2,
75 #ifdef CONFIG_SYS_FSL_HAS_DP_DDR
76 if (ctrl_num == CONFIG_DP_DDR_CTRL) {
77 /* force DDR bus width to 32 bits */
78 popts->data_bus_width = 1;
79 popts->otf_burst_chop_en = 0;
80 popts->burst_length = DDR_BL8;
81 popts->bstopre = 0; /* enable auto precharge */
85 * Factors to consider for half-strength driver enable:
86 * - number of DIMMs installed
88 popts->half_strength_driver_enable = 1;
90 * Write leveling override
92 popts->wrlvl_override = 1;
93 popts->wrlvl_sample = 0xf;
96 * Rtt and Rtt_WR override
98 popts->rtt_override = 0;
100 /* Enable ZQ calibration */
103 #ifdef CONFIG_SYS_FSL_DDR4
104 popts->ddr_cdr1 = DDR_CDR1_DHC_EN | DDR_CDR1_ODT(DDR_CDR_ODT_80ohm);
105 popts->ddr_cdr2 = DDR_CDR2_ODT(DDR_CDR_ODT_80ohm) |
106 DDR_CDR2_VREF_OVRD(70); /* Vref = 70% */
108 /* DHC_EN =1, ODT = 75 Ohm */
109 popts->ddr_cdr1 = DDR_CDR1_DHC_EN | DDR_CDR1_ODT(DDR_CDR_ODT_75ohm);
110 popts->ddr_cdr2 = DDR_CDR2_ODT(DDR_CDR_ODT_75ohm);
114 #ifdef CONFIG_SYS_DDR_RAW_TIMING
115 dimm_params_t ddr_raw_timing = {
117 .rank_density = 1073741824u,
118 .capacity = 2147483648,
119 .primary_sdram_width = 64,
121 .registered_dimm = 0,
125 .n_banks_per_sdram_device = 8,
127 .burst_lengths_bitmask = 0x0c,
130 .caslat_x = 0x6FC << 4, /* 14,13,11,10,9,8,7,6 */
141 .refresh_rate_ps = 7800000,
145 int fsl_ddr_get_dimm_params(dimm_params_t *pdimm,
146 unsigned int controller_number,
147 unsigned int dimm_number)
149 const char dimm_model[] = "Fixed DDR on board";
151 if (((controller_number == 0) && (dimm_number == 0)) ||
152 ((controller_number == 1) && (dimm_number == 0))) {
153 memcpy(pdimm, &ddr_raw_timing, sizeof(dimm_params_t));
154 memset(pdimm->mpart, 0, sizeof(pdimm->mpart));
155 memcpy(pdimm->mpart, dimm_model, sizeof(dimm_model) - 1);
161 phys_size_t initdram(int board_type)
163 phys_size_t dram_size;
165 puts("Initializing DDR....");
168 dram_size = fsl_ddr_sdram();
173 void dram_init_banksize(void)
175 #ifdef CONFIG_SYS_DP_DDR_BASE_PHY
176 phys_size_t dp_ddr_size;
180 * gd->secure_ram tracks the location of secure memory.
181 * It was set as if the memory starts from 0.
182 * The address needs to add the offset of its bank.
184 gd->bd->bi_dram[0].start = CONFIG_SYS_SDRAM_BASE;
185 if (gd->ram_size > CONFIG_SYS_LS2_DDR_BLOCK1_SIZE) {
186 gd->bd->bi_dram[0].size = CONFIG_SYS_LS2_DDR_BLOCK1_SIZE;
187 gd->bd->bi_dram[1].start = CONFIG_SYS_DDR_BLOCK2_BASE;
188 gd->bd->bi_dram[1].size = gd->ram_size -
189 CONFIG_SYS_LS2_DDR_BLOCK1_SIZE;
190 #ifdef CONFIG_SYS_MEM_RESERVE_SECURE
191 gd->secure_ram = gd->bd->bi_dram[1].start +
193 CONFIG_SYS_LS2_DDR_BLOCK1_SIZE;
194 gd->secure_ram |= MEM_RESERVE_SECURE_MAINTAINED;
197 gd->bd->bi_dram[0].size = gd->ram_size;
198 #ifdef CONFIG_SYS_MEM_RESERVE_SECURE
199 gd->secure_ram = gd->bd->bi_dram[0].start + gd->secure_ram;
200 gd->secure_ram |= MEM_RESERVE_SECURE_MAINTAINED;
204 #ifdef CONFIG_SYS_DP_DDR_BASE_PHY
205 if (soc_has_dp_ddr()) {
206 /* initialize DP-DDR here */
209 * DDR controller use 0 as the base address for binding.
210 * It is mapped to CONFIG_SYS_DP_DDR_BASE for core to access.
212 dp_ddr_size = fsl_other_ddr_sdram(CONFIG_SYS_DP_DDR_BASE_PHY,
214 CONFIG_DP_DDR_NUM_CTRLS,
215 CONFIG_DP_DDR_DIMM_SLOTS_PER_CTLR,
218 gd->bd->bi_dram[2].start = CONFIG_SYS_DP_DDR_BASE;
219 gd->bd->bi_dram[2].size = dp_ddr_size;
221 puts("Not detected");