1 // SPDX-License-Identifier: GPL-2.0+
3 * Copyright 2017-2018 NXP
15 #include <fdt_support.h>
16 #include <linux/libfdt.h>
17 #include <fsl-mc/fsl_mc.h>
18 #include <env_internal.h>
19 #include <asm/arch-fsl-layerscape/soc.h>
20 #include <asm/arch/ppa.h>
22 #include <asm/arch/fsl_serdes.h>
23 #include <asm/arch/soc.h>
25 #include "../common/qixis.h"
26 #include "ls1088a_qixis.h"
27 #include "../common/vid.h"
28 #include <fsl_immap.h>
30 DECLARE_GLOBAL_DATA_PTR;
32 #ifdef CONFIG_TARGET_LS1088AQDS
34 struct ifc_regs ifc_cfg_ifc_nor_boot[CONFIG_SYS_FSL_IFC_BANK_COUNT] = {
37 CONFIG_SYS_NOR0_CSPR_EARLY,
38 CONFIG_SYS_NOR0_CSPR_EXT,
53 CONFIG_SYS_NOR1_CSPR_EARLY,
54 CONFIG_SYS_NOR0_CSPR_EXT,
55 CONFIG_SYS_NOR_AMASK_EARLY,
70 CONFIG_SYS_NAND_CSPR_EXT,
71 CONFIG_SYS_NAND_AMASK,
74 CONFIG_SYS_NAND_FTIM0,
75 CONFIG_SYS_NAND_FTIM1,
76 CONFIG_SYS_NAND_FTIM2,
83 CONFIG_SYS_FPGA_CSPR_EXT,
98 struct ifc_regs ifc_cfg_qspi_nor_boot[CONFIG_SYS_FSL_IFC_BANK_COUNT] = {
101 CONFIG_SYS_NAND_CSPR,
102 CONFIG_SYS_NAND_CSPR_EXT,
103 CONFIG_SYS_NAND_AMASK,
104 CONFIG_SYS_NAND_CSOR,
106 CONFIG_SYS_NAND_FTIM0,
107 CONFIG_SYS_NAND_FTIM1,
108 CONFIG_SYS_NAND_FTIM2,
109 CONFIG_SYS_NAND_FTIM3
117 CONFIG_SYS_FPGA_CSPR,
118 CONFIG_SYS_FPGA_CSPR_EXT,
120 CONFIG_SYS_FPGA_CSOR,
133 void ifc_cfg_boot_info(struct ifc_regs_info *regs_info)
135 enum boot_src src = get_boot_src();
137 if (src == BOOT_SOURCE_QSPI_NOR)
138 regs_info->regs = ifc_cfg_qspi_nor_boot;
140 regs_info->regs = ifc_cfg_ifc_nor_boot;
142 regs_info->cs_size = CONFIG_SYS_FSL_IFC_BANK_COUNT;
144 #endif /* CONFIG_TFABOOT */
145 #endif /* CONFIG_TARGET_LS1088AQDS */
147 int board_early_init_f(void)
149 #if defined(CONFIG_SYS_I2C_EARLY_INIT) && defined(CONFIG_TARGET_LS1088AQDS)
152 fsl_lsch3_early_init_f();
156 #ifdef CONFIG_FSL_QIXIS
157 unsigned long long get_qixis_addr(void)
159 unsigned long long addr;
161 if (gd->flags & GD_FLG_RELOC)
162 addr = QIXIS_BASE_PHYS;
164 addr = QIXIS_BASE_PHYS_EARLY;
167 * IFC address under 256MB is mapped to 0x30000000, any address above
168 * is mapped to 0x5_10000000 up to 4GB.
170 addr = addr > 0x10000000 ? addr + 0x500000000ULL : addr + 0x30000000;
176 #if defined(CONFIG_VID)
177 int init_func_vid(void)
179 if (adjust_vdd(0) < 0)
180 printf("core voltage not adjusted\n");
186 int is_pb_board(void)
190 board_id = QIXIS_READ(id);
191 if (board_id == LS1088ARDB_PB_BOARD)
197 int fixup_ls1088ardb_pb_banner(void *fdt)
199 fdt_setprop_string(fdt, 0, "model", "LS1088ARDB-PB Board");
204 #if !defined(CONFIG_SPL_BUILD)
207 #ifdef CONFIG_TFABOOT
208 enum boot_src src = get_boot_src();
212 static const char *const freq[] = {"100", "125", "156.25",
213 "100 separate SSCG"};
216 #ifdef CONFIG_TARGET_LS1088AQDS
217 printf("Board: LS1088A-QDS, ");
220 printf("Board: LS1088ARDB-PB, ");
222 printf("Board: LS1088A-RDB, ");
225 sw = QIXIS_READ(arch);
226 printf("Board Arch: V%d, ", sw >> 4);
228 #ifdef CONFIG_TARGET_LS1088AQDS
229 printf("Board version: %c, boot from ", (sw & 0xf) + 'A' - 1);
231 printf("Board version: %c, boot from ", (sw & 0xf) + 'A');
234 memset((u8 *)buf, 0x00, ARRAY_SIZE(buf));
236 sw = QIXIS_READ(brdcfg[0]);
237 sw = (sw & QIXIS_LBMAP_MASK) >> QIXIS_LBMAP_SHIFT;
239 #ifdef CONFIG_TFABOOT
240 if (src == BOOT_SOURCE_SD_MMC)
243 #ifdef CONFIG_SD_BOOT
246 #endif /* CONFIG_TFABOOT */
248 #ifdef CONFIG_TARGET_LS1088AQDS
257 printf("vBank: %d\n", sw);
270 sw = QIXIS_READ(brdcfg[0]);
271 sw = (sw & QIXIS_QMAP_MASK) >> QIXIS_QMAP_SHIFT;
272 if (sw == 0 || sw == 4)
281 printf("invalid setting of SW%u\n", QIXIS_LBMAP_SWITCH);
285 #ifdef CONFIG_TARGET_LS1088AQDS
286 printf("FPGA: v%d (%s), build %d",
287 (int)QIXIS_READ(scver), qixis_read_tag(buf),
288 (int)qixis_read_minor());
289 /* the timestamp string contains "\n" at the end */
290 printf(" on %s", qixis_read_time(buf));
292 printf("CPLD: v%d.%d\n", QIXIS_READ(scver), QIXIS_READ(tagdata));
296 * Display the actual SERDES reference clocks as configured by the
297 * dip switches on the board. Note that the SWx registers could
298 * technically be set to force the reference clocks to match the
299 * values that the SERDES expects (or vice versa). For now, however,
300 * we just display both values and hope the user notices when they
303 puts("SERDES1 Reference : ");
304 sw = QIXIS_READ(brdcfg[2]);
305 clock = (sw >> 6) & 3;
306 printf("Clock1 = %sMHz ", freq[clock]);
307 clock = (sw >> 4) & 3;
308 printf("Clock2 = %sMHz", freq[clock]);
310 puts("\nSERDES2 Reference : ");
311 clock = (sw >> 2) & 3;
312 printf("Clock1 = %sMHz ", freq[clock]);
313 clock = (sw >> 0) & 3;
314 printf("Clock2 = %sMHz\n", freq[clock]);
320 bool if_board_diff_clk(void)
322 #ifdef CONFIG_TARGET_LS1088AQDS
323 u8 diff_conf = QIXIS_READ(brdcfg[11]);
324 return diff_conf & 0x40;
326 u8 diff_conf = QIXIS_READ(dutcfg[11]);
327 return diff_conf & 0x80;
331 unsigned long get_board_sys_clk(void)
333 u8 sysclk_conf = QIXIS_READ(brdcfg[1]);
335 switch (sysclk_conf & 0x0f) {
336 case QIXIS_SYSCLK_83:
338 case QIXIS_SYSCLK_100:
340 case QIXIS_SYSCLK_125:
342 case QIXIS_SYSCLK_133:
344 case QIXIS_SYSCLK_150:
346 case QIXIS_SYSCLK_160:
348 case QIXIS_SYSCLK_166:
355 unsigned long get_board_ddr_clk(void)
357 u8 ddrclk_conf = QIXIS_READ(brdcfg[1]);
359 if (if_board_diff_clk())
360 return get_board_sys_clk();
361 switch ((ddrclk_conf & 0x30) >> 4) {
362 case QIXIS_DDRCLK_100:
364 case QIXIS_DDRCLK_125:
366 case QIXIS_DDRCLK_133:
373 int select_i2c_ch_pca9547(u8 ch)
377 ret = i2c_write(I2C_MUX_PCA_ADDR_PRI, 0, 1, &ch, 1);
379 puts("PCA: failed to select proper channel\n");
386 #if !defined(CONFIG_SPL_BUILD)
387 void board_retimer_init(void)
391 /* Retimer is connected to I2C1_CH5 */
392 select_i2c_ch_pca9547(I2C_MUX_CH5);
394 /* Access to Control/Shared register */
396 i2c_write(I2C_RETIMER_ADDR, 0xff, 1, ®, 1);
398 /* Read device revision and ID */
399 i2c_read(I2C_RETIMER_ADDR, 1, 1, ®, 1);
400 debug("Retimer version id = 0x%x\n", reg);
402 /* Enable Broadcast. All writes target all channel register sets */
404 i2c_write(I2C_RETIMER_ADDR, 0xff, 1, ®, 1);
406 /* Reset Channel Registers */
407 i2c_read(I2C_RETIMER_ADDR, 0, 1, ®, 1);
409 i2c_write(I2C_RETIMER_ADDR, 0, 1, ®, 1);
411 /* Set data rate as 10.3125 Gbps */
413 i2c_write(I2C_RETIMER_ADDR, 0x60, 1, ®, 1);
415 i2c_write(I2C_RETIMER_ADDR, 0x61, 1, ®, 1);
417 i2c_write(I2C_RETIMER_ADDR, 0x62, 1, ®, 1);
419 i2c_write(I2C_RETIMER_ADDR, 0x63, 1, ®, 1);
421 i2c_write(I2C_RETIMER_ADDR, 0x64, 1, ®, 1);
423 /* Select VCO Divider to full rate (000) */
424 i2c_read(I2C_RETIMER_ADDR, 0x2F, 1, ®, 1);
427 i2c_write(I2C_RETIMER_ADDR, 0x2F, 1, ®, 1);
429 #ifdef CONFIG_TARGET_LS1088AQDS
430 /* Retimer is connected to I2C1_CH5 */
431 select_i2c_ch_pca9547(I2C_MUX_CH5);
433 /* Access to Control/Shared register */
435 i2c_write(I2C_RETIMER_ADDR2, 0xff, 1, ®, 1);
437 /* Read device revision and ID */
438 i2c_read(I2C_RETIMER_ADDR2, 1, 1, ®, 1);
439 debug("Retimer version id = 0x%x\n", reg);
441 /* Enable Broadcast. All writes target all channel register sets */
443 i2c_write(I2C_RETIMER_ADDR2, 0xff, 1, ®, 1);
445 /* Reset Channel Registers */
446 i2c_read(I2C_RETIMER_ADDR2, 0, 1, ®, 1);
448 i2c_write(I2C_RETIMER_ADDR2, 0, 1, ®, 1);
450 /* Set data rate as 10.3125 Gbps */
452 i2c_write(I2C_RETIMER_ADDR2, 0x60, 1, ®, 1);
454 i2c_write(I2C_RETIMER_ADDR2, 0x61, 1, ®, 1);
456 i2c_write(I2C_RETIMER_ADDR2, 0x62, 1, ®, 1);
458 i2c_write(I2C_RETIMER_ADDR2, 0x63, 1, ®, 1);
460 i2c_write(I2C_RETIMER_ADDR2, 0x64, 1, ®, 1);
462 /* Select VCO Divider to full rate (000) */
463 i2c_read(I2C_RETIMER_ADDR2, 0x2F, 1, ®, 1);
466 i2c_write(I2C_RETIMER_ADDR2, 0x2F, 1, ®, 1);
468 /*return the default channel*/
469 select_i2c_ch_pca9547(I2C_MUX_CH_DEFAULT);
472 #ifdef CONFIG_MISC_INIT_R
473 int misc_init_r(void)
475 #ifdef CONFIG_TARGET_LS1088ARDB
478 if (hwconfig("esdhc-force-sd")) {
479 brdcfg5 = QIXIS_READ(brdcfg[5]);
480 brdcfg5 &= ~BRDCFG5_SPISDHC_MASK;
481 brdcfg5 |= BRDCFG5_FORCE_SD;
482 QIXIS_WRITE(brdcfg[5], brdcfg5);
490 int i2c_multiplexer_select_vid_channel(u8 channel)
492 return select_i2c_ch_pca9547(channel);
495 #ifdef CONFIG_TARGET_LS1088AQDS
496 /* read the current value(SVDD) of the LTM Regulator Voltage */
497 int get_serdes_volt(void)
500 u8 chan = PWM_CHANNEL0;
502 /* Select the PAGE 0 using PMBus commands PAGE for VDD */
503 ret = i2c_write(I2C_SVDD_MONITOR_ADDR,
504 PMBUS_CMD_PAGE, 1, &chan, 1);
506 printf("VID: failed to select VDD Page 0\n");
510 /* Read the output voltage using PMBus command READ_VOUT */
511 ret = i2c_read(I2C_SVDD_MONITOR_ADDR,
512 PMBUS_CMD_READ_VOUT, 1, (void *)&vcode, 2);
514 printf("VID: failed to read the volatge\n");
521 int set_serdes_volt(int svdd)
524 u8 buff[5] = {0x04, PWM_CHANNEL0, PMBUS_CMD_VOUT_COMMAND,
525 svdd & 0xFF, (svdd & 0xFF00) >> 8};
527 /* Write the desired voltage code to the SVDD regulator */
528 ret = i2c_write(I2C_SVDD_MONITOR_ADDR,
529 PMBUS_CMD_PAGE_PLUS_WRITE, 1, (void *)&buff, 5);
531 printf("VID: I2C failed to write to the volatge regulator\n");
535 /* Wait for the volatge to get to the desired value */
537 vdd_last = get_serdes_volt();
539 printf("VID: Couldn't read sensor abort VID adjust\n");
542 } while (vdd_last != svdd);
547 int get_serdes_volt(void)
552 int set_serdes_volt(int svdd)
557 printf("SVDD changing of RDB\n");
559 /* Read the BRDCFG54 via CLPD */
560 ret = i2c_read(CONFIG_SYS_I2C_FPGA_ADDR,
561 QIXIS_BRDCFG4_OFFSET, 1, (void *)&brdcfg4, 1);
563 printf("VID: I2C failed to read the CPLD BRDCFG4\n");
567 brdcfg4 = brdcfg4 | 0x08;
569 /* Write to the BRDCFG4 */
570 ret = i2c_write(CONFIG_SYS_I2C_FPGA_ADDR,
571 QIXIS_BRDCFG4_OFFSET, 1, (void *)&brdcfg4, 1);
573 debug("VID: I2C failed to set the SVDD CPLD BRDCFG4\n");
577 /* Wait for the volatge to get to the desired value */
584 /* this function disables the SERDES, changes the SVDD Voltage and enables it*/
585 int board_adjust_vdd(int vdd)
589 debug("%s: vdd = %d\n", __func__, vdd);
591 /* Special settings to be performed when voltage is 900mV */
593 ret = setup_serdes_volt(vdd);
603 #if !defined(CONFIG_SPL_BUILD)
606 init_final_memctl_regs();
607 #if defined(CONFIG_TARGET_LS1088ARDB) && defined(CONFIG_FSL_MC_ENET)
608 u32 __iomem *irq_ccsr = (u32 __iomem *)ISC_BASE;
611 select_i2c_ch_pca9547(I2C_MUX_CH_DEFAULT);
612 board_retimer_init();
614 #ifdef CONFIG_ENV_IS_NOWHERE
615 gd->env_addr = (ulong)&default_environment[0];
618 #if defined(CONFIG_TARGET_LS1088ARDB) && defined(CONFIG_FSL_MC_ENET)
619 /* invert AQR105 IRQ pins polarity */
620 out_le32(irq_ccsr + IRQCR_OFFSET / 4, AQR105_IRQ_MASK);
623 #ifdef CONFIG_FSL_CAAM
626 #ifdef CONFIG_FSL_LS_PPA
632 void detail_board_ddr_info(void)
635 print_size(gd->bd->bi_dram[0].size + gd->bd->bi_dram[1].size, "");
639 #if defined(CONFIG_ARCH_MISC_INIT)
640 int arch_misc_init(void)
646 #ifdef CONFIG_FSL_MC_ENET
647 void board_quiesce_devices(void)
649 fsl_mc_ldpaa_exit(gd->bd);
652 void fdt_fixup_board_enet(void *fdt)
656 offset = fdt_path_offset(fdt, "/fsl-mc");
659 offset = fdt_path_offset(fdt, "/soc/fsl-mc");
662 printf("%s: ERROR: fsl-mc node not found in device tree (error %d)\n",
667 if (get_mc_boot_status() == 0 &&
668 (is_lazy_dpl_addr_valid() || get_dpl_apply_status() == 0))
669 fdt_status_okay(fdt, offset);
671 fdt_status_fail(fdt, offset);
675 #ifdef CONFIG_OF_BOARD_SETUP
676 void fsl_fdt_fixup_flash(void *fdt)
679 #ifdef CONFIG_TFABOOT
680 u32 __iomem *dcfg_ccsr = (u32 __iomem *)DCFG_BASE;
685 * IFC-NOR and QSPI are muxed on SoC.
686 * So disable IFC node in dts if QSPI is enabled or
687 * disable QSPI node in dts in case QSPI is not enabled.
690 #ifdef CONFIG_TFABOOT
691 enum boot_src src = get_boot_src();
692 bool disable_ifc = false;
695 case BOOT_SOURCE_IFC_NOR:
698 case BOOT_SOURCE_QSPI_NOR:
702 val = in_le32(dcfg_ccsr + DCFG_RCWSR15 / 4);
703 if (DCFG_RCWSR15_IFCGRPABASE_QSPI == (val & (u32)0x3))
709 offset = fdt_path_offset(fdt, "/soc/ifc/nor");
712 offset = fdt_path_offset(fdt, "/ifc/nor");
714 offset = fdt_path_offset(fdt, "/soc/quadspi");
717 offset = fdt_path_offset(fdt, "/quadspi");
721 #ifdef CONFIG_FSL_QSPI
722 offset = fdt_path_offset(fdt, "/soc/ifc/nor");
725 offset = fdt_path_offset(fdt, "/ifc/nor");
727 offset = fdt_path_offset(fdt, "/soc/quadspi");
730 offset = fdt_path_offset(fdt, "/quadspi");
736 fdt_status_disabled(fdt, offset);
739 int ft_board_setup(void *blob, bd_t *bd)
742 u64 base[CONFIG_NR_DRAM_BANKS];
743 u64 size[CONFIG_NR_DRAM_BANKS];
745 ft_cpu_setup(blob, bd);
747 /* fixup DT for the two GPP DDR banks */
748 for (i = 0; i < CONFIG_NR_DRAM_BANKS; i++) {
749 base[i] = gd->bd->bi_dram[i].start;
750 size[i] = gd->bd->bi_dram[i].size;
753 #ifdef CONFIG_RESV_RAM
754 /* reduce size if reserved memory is within this bank */
755 if (gd->arch.resv_ram >= base[0] &&
756 gd->arch.resv_ram < base[0] + size[0])
757 size[0] = gd->arch.resv_ram - base[0];
758 else if (gd->arch.resv_ram >= base[1] &&
759 gd->arch.resv_ram < base[1] + size[1])
760 size[1] = gd->arch.resv_ram - base[1];
763 fdt_fixup_memory_banks(blob, base, size, CONFIG_NR_DRAM_BANKS);
765 fdt_fsl_mc_fixup_iommu_map_entry(blob);
767 fsl_fdt_fixup_flash(blob);
769 #ifdef CONFIG_FSL_MC_ENET
770 fdt_fixup_board_enet(blob);
773 fixup_ls1088ardb_pb_banner(blob);
778 #endif /* defined(CONFIG_SPL_BUILD) */
780 #ifdef CONFIG_TFABOOT
781 #ifdef CONFIG_MTD_NOR_FLASH
782 int is_flash_available(void)
784 char *env_hwconfig = env_get("hwconfig");
785 enum boot_src src = get_boot_src();
786 int is_nor_flash_available = 1;
789 case BOOT_SOURCE_IFC_NOR:
790 is_nor_flash_available = 1;
792 case BOOT_SOURCE_QSPI_NOR:
793 is_nor_flash_available = 0;
796 * In Case of SD boot,if qspi is defined in env_hwconfig
797 * disable nor flash probe.
800 if (hwconfig_f("qspi", env_hwconfig))
801 is_nor_flash_available = 0;
804 return is_nor_flash_available;
808 void *env_sf_get_env_addr(void)
810 return (void *)(CONFIG_SYS_FSL_QSPI_BASE + CONFIG_ENV_OFFSET);