board/freescale/ls1088a/ls1088a.c

   1 // SPDX-License-Identifier: GPL-2.0+
   2 /*
   3  * Copyright 2017-2018 NXP
   4  */
   5 #include <common.h>
   6 #include <env.h>
   7 #include <i2c.h>
   8 #include <init.h>
   9 #include <log.h>
  10 #include <malloc.h>
  11 #include <errno.h>
  12 #include <netdev.h>
  13 #include <fsl_ifc.h>
  14 #include <fsl_ddr.h>
  15 #include <fsl_sec.h>
  16 #include <asm/global_data.h>
  17 #include <asm/io.h>
  18 #include <fdt_support.h>
  19 #include <linux/delay.h>
  20 #include <linux/libfdt.h>
  21 #include <fsl-mc/fsl_mc.h>
  22 #include <env_internal.h>
  23 #include <asm/arch-fsl-layerscape/soc.h>
  24 #include <asm/arch/ppa.h>
  25 #include <hwconfig.h>
  26 #include <asm/arch/fsl_serdes.h>
  27 #include <asm/arch/soc.h>
  28 #include <asm/arch-fsl-layerscape/fsl_icid.h>
  29
  30 #include "../common/qixis.h"
  31 #include "ls1088a_qixis.h"
  32 #include "../common/vid.h"
  33 #include <fsl_immap.h>
  34
  35 DECLARE_GLOBAL_DATA_PTR;
  36
  37 #ifdef CONFIG_TARGET_LS1088AQDS
  38 #ifdef CONFIG_TFABOOT
  39 struct ifc_regs ifc_cfg_ifc_nor_boot[CONFIG_SYS_FSL_IFC_BANK_COUNT] = {
  40         {
  41                 "nor0",
  42                 CONFIG_SYS_NOR0_CSPR_EARLY,
  43                 CONFIG_SYS_NOR0_CSPR_EXT,
  44                 CONFIG_SYS_NOR_AMASK,
  45                 CONFIG_SYS_NOR_CSOR,
  46                 {
  47                         CONFIG_SYS_NOR_FTIM0,
  48                         CONFIG_SYS_NOR_FTIM1,
  49                         CONFIG_SYS_NOR_FTIM2,
  50                         CONFIG_SYS_NOR_FTIM3
  51                 },
  52                 0,
  53                 CONFIG_SYS_NOR0_CSPR,
  54                 0,
  55         },
  56         {
  57                 "nor1",
  58                 CONFIG_SYS_NOR1_CSPR_EARLY,
  59                 CONFIG_SYS_NOR0_CSPR_EXT,
  60                 CONFIG_SYS_NOR_AMASK_EARLY,
  61                 CONFIG_SYS_NOR_CSOR,
  62                 {
  63                         CONFIG_SYS_NOR_FTIM0,
  64                         CONFIG_SYS_NOR_FTIM1,
  65                         CONFIG_SYS_NOR_FTIM2,
  66                         CONFIG_SYS_NOR_FTIM3
  67                 },
  68                 0,
  69                 CONFIG_SYS_NOR1_CSPR,
  70                 CONFIG_SYS_NOR_AMASK,
  71         },
  72         {
  73                 "nand",
  74                 CONFIG_SYS_NAND_CSPR,
  75                 CONFIG_SYS_NAND_CSPR_EXT,
  76                 CONFIG_SYS_NAND_AMASK,
  77                 CONFIG_SYS_NAND_CSOR,
  78                 {
  79                         CONFIG_SYS_NAND_FTIM0,
  80                         CONFIG_SYS_NAND_FTIM1,
  81                         CONFIG_SYS_NAND_FTIM2,
  82                         CONFIG_SYS_NAND_FTIM3
  83                 },
  84         },
  85         {
  86                 "fpga",
  87                 CONFIG_SYS_FPGA_CSPR,
  88                 CONFIG_SYS_FPGA_CSPR_EXT,
  89                 SYS_FPGA_AMASK,
  90                 CONFIG_SYS_FPGA_CSOR,
  91                 {
  92                         SYS_FPGA_CS_FTIM0,
  93                         SYS_FPGA_CS_FTIM1,
  94                         SYS_FPGA_CS_FTIM2,
  95                         SYS_FPGA_CS_FTIM3
  96                 },
  97                 0,
  98                 SYS_FPGA_CSPR_FINAL,
  99                 0,
 100         }
 101 };
 102
 103 struct ifc_regs ifc_cfg_qspi_nor_boot[CONFIG_SYS_FSL_IFC_BANK_COUNT] = {
 104         {
 105                 "nand",
 106                 CONFIG_SYS_NAND_CSPR,
 107                 CONFIG_SYS_NAND_CSPR_EXT,
 108                 CONFIG_SYS_NAND_AMASK,
 109                 CONFIG_SYS_NAND_CSOR,
 110                 {
 111                         CONFIG_SYS_NAND_FTIM0,
 112                         CONFIG_SYS_NAND_FTIM1,
 113                         CONFIG_SYS_NAND_FTIM2,
 114                         CONFIG_SYS_NAND_FTIM3
 115                 },
 116         },
 117         {
 118                 "reserved",
 119         },
 120         {
 121                 "fpga",
 122                 CONFIG_SYS_FPGA_CSPR,
 123                 CONFIG_SYS_FPGA_CSPR_EXT,
 124                 SYS_FPGA_AMASK,
 125                 CONFIG_SYS_FPGA_CSOR,
 126                 {
 127                         SYS_FPGA_CS_FTIM0,
 128                         SYS_FPGA_CS_FTIM1,
 129                         SYS_FPGA_CS_FTIM2,
 130                         SYS_FPGA_CS_FTIM3
 131                 },
 132                 0,
 133                 SYS_FPGA_CSPR_FINAL,
 134                 0,
 135         }
 136 };
 137
 138 void ifc_cfg_boot_info(struct ifc_regs_info *regs_info)
 139 {
 140         enum boot_src src = get_boot_src();
 141
 142         if (src == BOOT_SOURCE_QSPI_NOR)
 143                 regs_info->regs = ifc_cfg_qspi_nor_boot;
 144         else
 145                 regs_info->regs = ifc_cfg_ifc_nor_boot;
 146
 147         regs_info->cs_size = CONFIG_SYS_FSL_IFC_BANK_COUNT;
 148 }
 149 #endif /* CONFIG_TFABOOT */
 150 #endif /* CONFIG_TARGET_LS1088AQDS */
 151
 152 int board_early_init_f(void)
 153 {
 154 #if defined(CONFIG_SYS_I2C_EARLY_INIT) && defined(CONFIG_TARGET_LS1088AQDS)
 155         i2c_early_init_f();
 156 #endif
 157         fsl_lsch3_early_init_f();
 158         return 0;
 159 }
 160
 161 #ifdef CONFIG_FSL_QIXIS
 162 unsigned long long get_qixis_addr(void)
 163 {
 164         unsigned long long addr;
 165
 166         if (gd->flags & GD_FLG_RELOC)
 167                 addr = QIXIS_BASE_PHYS;
 168         else
 169                 addr = QIXIS_BASE_PHYS_EARLY;
 170
 171         /*
 172          * IFC address under 256MB is mapped to 0x30000000, any address above
 173          * is mapped to 0x5_10000000 up to 4GB.
 174          */
 175         addr = addr  > 0x10000000 ? addr + 0x500000000ULL : addr + 0x30000000;
 176
 177         return addr;
 178 }
 179 #endif
 180
 181 #if defined(CONFIG_VID)
 182 int init_func_vid(void)
 183 {
 184         if (adjust_vdd(0) < 0)
 185                 printf("core voltage not adjusted\n");
 186
 187         return 0;
 188 }
 189
 190 u16 soc_get_fuse_vid(int vid_index)
 191 {
 192         static const u16 vdd[32] = {
 193                 10250,
 194                 9875,
 195                 9750,
 196                 0,      /* reserved */
 197                 0,      /* reserved */
 198                 0,      /* reserved */
 199                 0,      /* reserved */
 200                 0,      /* reserved */
 201                 9000,
 202                 0,      /* reserved */
 203                 0,      /* reserved */
 204                 0,      /* reserved */
 205                 0,      /* reserved */
 206                 0,      /* reserved */
 207                 0,      /* reserved */
 208                 0,      /* reserved */
 209                 10000,  /* 1.0000V */
 210                 10125,
 211                 10250,
 212                 0,      /* reserved */
 213                 0,      /* reserved */
 214                 0,      /* reserved */
 215                 0,      /* reserved */
 216                 0,      /* reserved */
 217                 0,      /* reserved */
 218                 0,      /* reserved */
 219                 0,      /* reserved */
 220                 0,      /* reserved */
 221                 0,      /* reserved */
 222                 0,      /* reserved */
 223                 0,      /* reserved */
 224                 0,      /* reserved */
 225         };
 226
 227         return vdd[vid_index];
 228 };
 229 #endif
 230
 231 int is_pb_board(void)
 232 {
 233         u8 board_id;
 234
 235         board_id = QIXIS_READ(id);
 236         if (board_id == LS1088ARDB_PB_BOARD)
 237                 return 1;
 238         else
 239                 return 0;
 240 }
 241
 242 int fixup_ls1088ardb_pb_banner(void *fdt)
 243 {
 244         fdt_setprop_string(fdt, 0, "model", "LS1088ARDB-PB Board");
 245
 246         return 0;
 247 }
 248
 249 #if !defined(CONFIG_SPL_BUILD)
 250 int checkboard(void)
 251 {
 252 #ifdef CONFIG_TFABOOT
 253         enum boot_src src = get_boot_src();
 254 #endif
 255         char buf[64];
 256         u8 sw;
 257         static const char *const freq[] = {"100", "125", "156.25",
 258                                             "100 separate SSCG"};
 259         int clock;
 260
 261 #ifdef CONFIG_TARGET_LS1088AQDS
 262         printf("Board: LS1088A-QDS, ");
 263 #else
 264         if (is_pb_board())
 265                 printf("Board: LS1088ARDB-PB, ");
 266         else
 267                 printf("Board: LS1088A-RDB, ");
 268 #endif
 269
 270         sw = QIXIS_READ(arch);
 271         printf("Board Arch: V%d, ", sw >> 4);
 272
 273 #ifdef CONFIG_TARGET_LS1088AQDS
 274         printf("Board version: %c, boot from ", (sw & 0xf) + 'A' - 1);
 275 #else
 276         printf("Board version: %c, boot from ", (sw & 0xf) + 'A');
 277 #endif
 278
 279         memset((u8 *)buf, 0x00, ARRAY_SIZE(buf));
 280
 281         sw = QIXIS_READ(brdcfg[0]);
 282         sw = (sw & QIXIS_LBMAP_MASK) >> QIXIS_LBMAP_SHIFT;
 283
 284 #ifdef CONFIG_TFABOOT
 285         if (src == BOOT_SOURCE_SD_MMC)
 286                 puts("SD card\n");
 287 #else
 288 #ifdef CONFIG_SD_BOOT
 289         puts("SD card\n");
 290 #endif
 291 #endif /* CONFIG_TFABOOT */
 292         switch (sw) {
 293 #ifdef CONFIG_TARGET_LS1088AQDS
 294         case 0:
 295         case 1:
 296         case 2:
 297         case 3:
 298         case 4:
 299         case 5:
 300         case 6:
 301         case 7:
 302                 printf("vBank: %d\n", sw);
 303                 break;
 304         case 8:
 305                 puts("PromJet\n");
 306                 break;
 307         case 15:
 308                 puts("IFCCard\n");
 309                 break;
 310         case 14:
 311 #else
 312         case 0:
 313 #endif
 314                 puts("QSPI:");
 315                 sw = QIXIS_READ(brdcfg[0]);
 316                 sw = (sw & QIXIS_QMAP_MASK) >> QIXIS_QMAP_SHIFT;
 317                 if (sw == 0 || sw == 4)
 318                         puts("0\n");
 319                 else if (sw == 1)
 320                         puts("1\n");
 321                 else
 322                         puts("EMU\n");
 323                 break;
 324
 325         default:
 326                 printf("invalid setting of SW%u\n", QIXIS_LBMAP_SWITCH);
 327                 break;
 328         }
 329
 330 #ifdef CONFIG_TARGET_LS1088AQDS
 331         printf("FPGA: v%d (%s), build %d",
 332                (int)QIXIS_READ(scver), qixis_read_tag(buf),
 333                (int)qixis_read_minor());
 334         /* the timestamp string contains "\n" at the end */
 335         printf(" on %s", qixis_read_time(buf));
 336 #else
 337         printf("CPLD: v%d.%d\n", QIXIS_READ(scver), QIXIS_READ(tagdata));
 338 #endif
 339
 340         /*
 341          * Display the actual SERDES reference clocks as configured by the
 342          * dip switches on the board.  Note that the SWx registers could
 343          * technically be set to force the reference clocks to match the
 344          * values that the SERDES expects (or vice versa).  For now, however,
 345          * we just display both values and hope the user notices when they
 346          * don't match.
 347          */
 348         puts("SERDES1 Reference : ");
 349         sw = QIXIS_READ(brdcfg[2]);
 350         clock = (sw >> 6) & 3;
 351         printf("Clock1 = %sMHz ", freq[clock]);
 352         clock = (sw >> 4) & 3;
 353         printf("Clock2 = %sMHz", freq[clock]);
 354
 355         puts("\nSERDES2 Reference : ");
 356         clock = (sw >> 2) & 3;
 357         printf("Clock1 = %sMHz ", freq[clock]);
 358         clock = (sw >> 0) & 3;
 359         printf("Clock2 = %sMHz\n", freq[clock]);
 360
 361         return 0;
 362 }
 363 #endif
 364
 365 bool if_board_diff_clk(void)
 366 {
 367 #ifdef CONFIG_TARGET_LS1088AQDS
 368         u8 diff_conf = QIXIS_READ(brdcfg[11]);
 369         return diff_conf & 0x40;
 370 #else
 371         u8 diff_conf = QIXIS_READ(dutcfg[11]);
 372         return diff_conf & 0x80;
 373 #endif
 374 }
 375
 376 unsigned long get_board_sys_clk(void)
 377 {
 378         u8 sysclk_conf = QIXIS_READ(brdcfg[1]);
 379
 380         switch (sysclk_conf & 0x0f) {
 381         case QIXIS_SYSCLK_83:
 382                 return 83333333;
 383         case QIXIS_SYSCLK_100:
 384                 return 100000000;
 385         case QIXIS_SYSCLK_125:
 386                 return 125000000;
 387         case QIXIS_SYSCLK_133:
 388                 return 133333333;
 389         case QIXIS_SYSCLK_150:
 390                 return 150000000;
 391         case QIXIS_SYSCLK_160:
 392                 return 160000000;
 393         case QIXIS_SYSCLK_166:
 394                 return 166666666;
 395         }
 396
 397         return 66666666;
 398 }
 399
 400 unsigned long get_board_ddr_clk(void)
 401 {
 402         u8 ddrclk_conf = QIXIS_READ(brdcfg[1]);
 403
 404         if (if_board_diff_clk())
 405                 return get_board_sys_clk();
 406         switch ((ddrclk_conf & 0x30) >> 4) {
 407         case QIXIS_DDRCLK_100:
 408                 return 100000000;
 409         case QIXIS_DDRCLK_125:
 410                 return 125000000;
 411         case QIXIS_DDRCLK_133:
 412                 return 133333333;
 413         }
 414
 415         return 66666666;
 416 }
 417
 418 int select_i2c_ch_pca9547(u8 ch)
 419 {
 420         int ret;
 421
 422 #if !CONFIG_IS_ENABLED(DM_I2C)
 423         ret = i2c_write(I2C_MUX_PCA_ADDR_PRI, 0, 1, &ch, 1);
 424 #else
 425         struct udevice *dev;
 426
 427         ret = i2c_get_chip_for_busnum(0, I2C_MUX_PCA_ADDR_PRI, 1, &dev);
 428         if (!ret)
 429                 ret = dm_i2c_write(dev, 0, &ch, 1);
 430 #endif
 431         if (ret) {
 432                 puts("PCA: failed to select proper channel\n");
 433                 return ret;
 434         }
 435
 436         return 0;
 437 }
 438
 439 #if !defined(CONFIG_SPL_BUILD)
 440 void board_retimer_init(void)
 441 {
 442         u8 reg;
 443
 444         /* Retimer is connected to I2C1_CH5 */
 445         select_i2c_ch_pca9547(I2C_MUX_CH5);
 446
 447         /* Access to Control/Shared register */
 448         reg = 0x0;
 449 #if !CONFIG_IS_ENABLED(DM_I2C)
 450         i2c_write(I2C_RETIMER_ADDR, 0xff, 1, &reg, 1);
 451 #else
 452         struct udevice *dev;
 453
 454         i2c_get_chip_for_busnum(0, I2C_RETIMER_ADDR, 1, &dev);
 455         dm_i2c_write(dev, 0xff, &reg, 1);
 456 #endif
 457
 458         /* Read device revision and ID */
 459 #if !CONFIG_IS_ENABLED(DM_I2C)
 460         i2c_read(I2C_RETIMER_ADDR, 1, 1, &reg, 1);
 461 #else
 462         dm_i2c_read(dev, 1, &reg, 1);
 463 #endif
 464         debug("Retimer version id = 0x%x\n", reg);
 465
 466         /* Enable Broadcast. All writes target all channel register sets */
 467         reg = 0x0c;
 468 #if !CONFIG_IS_ENABLED(DM_I2C)
 469         i2c_write(I2C_RETIMER_ADDR, 0xff, 1, &reg, 1);
 470 #else
 471         dm_i2c_write(dev, 0xff, &reg, 1);
 472 #endif
 473
 474         /* Reset Channel Registers */
 475 #if !CONFIG_IS_ENABLED(DM_I2C)
 476         i2c_read(I2C_RETIMER_ADDR, 0, 1, &reg, 1);
 477 #else
 478         dm_i2c_read(dev, 0, &reg, 1);
 479 #endif
 480         reg |= 0x4;
 481 #if !CONFIG_IS_ENABLED(DM_I2C)
 482         i2c_write(I2C_RETIMER_ADDR, 0, 1, &reg, 1);
 483 #else
 484         dm_i2c_write(dev, 0, &reg, 1);
 485 #endif
 486
 487         /* Set data rate as 10.3125 Gbps */
 488         reg = 0x90;
 489 #if !CONFIG_IS_ENABLED(DM_I2C)
 490         i2c_write(I2C_RETIMER_ADDR, 0x60, 1, &reg, 1);
 491 #else
 492         dm_i2c_write(dev, 0x60, &reg, 1);
 493 #endif
 494         reg = 0xb3;
 495 #if !CONFIG_IS_ENABLED(DM_I2C)
 496         i2c_write(I2C_RETIMER_ADDR, 0x61, 1, &reg, 1);
 497 #else
 498         dm_i2c_write(dev, 0x61, &reg, 1);
 499 #endif
 500         reg = 0x90;
 501 #if !CONFIG_IS_ENABLED(DM_I2C)
 502         i2c_write(I2C_RETIMER_ADDR, 0x62, 1, &reg, 1);
 503 #else
 504         dm_i2c_write(dev, 0x62, &reg, 1);
 505 #endif
 506         reg = 0xb3;
 507 #if !CONFIG_IS_ENABLED(DM_I2C)
 508         i2c_write(I2C_RETIMER_ADDR, 0x63, 1, &reg, 1);
 509 #else
 510         dm_i2c_write(dev, 0x63, &reg, 1);
 511 #endif
 512         reg = 0xcd;
 513 #if !CONFIG_IS_ENABLED(DM_I2C)
 514         i2c_write(I2C_RETIMER_ADDR, 0x64, 1, &reg, 1);
 515 #else
 516         dm_i2c_write(dev, 0x64, &reg, 1);
 517 #endif
 518
 519         /* Select VCO Divider to full rate (000) */
 520 #if !CONFIG_IS_ENABLED(DM_I2C)
 521         i2c_read(I2C_RETIMER_ADDR, 0x2F, 1, &reg, 1);
 522 #else
 523         dm_i2c_read(dev, 0x2F, &reg, 1);
 524 #endif
 525         reg &= 0x0f;
 526         reg |= 0x70;
 527 #if !CONFIG_IS_ENABLED(DM_I2C)
 528         i2c_write(I2C_RETIMER_ADDR, 0x2F, 1, &reg, 1);
 529 #else
 530         dm_i2c_write(dev, 0x2F, &reg, 1);
 531 #endif
 532
 533 #ifdef  CONFIG_TARGET_LS1088AQDS
 534         /* Retimer is connected to I2C1_CH5 */
 535         select_i2c_ch_pca9547(I2C_MUX_CH5);
 536
 537         /* Access to Control/Shared register */
 538         reg = 0x0;
 539 #if !CONFIG_IS_ENABLED(DM_I2C)
 540         i2c_write(I2C_RETIMER_ADDR2, 0xff, 1, &reg, 1);
 541 #else
 542         i2c_get_chip_for_busnum(0, I2C_RETIMER_ADDR2, 1, &dev);
 543         dm_i2c_write(dev, 0xff, &reg, 1);
 544 #endif
 545
 546         /* Read device revision and ID */
 547 #if !CONFIG_IS_ENABLED(DM_I2C)
 548         i2c_read(I2C_RETIMER_ADDR2, 1, 1, &reg, 1);
 549 #else
 550         dm_i2c_read(dev, 1, &reg, 1);
 551 #endif
 552         debug("Retimer version id = 0x%x\n", reg);
 553
 554         /* Enable Broadcast. All writes target all channel register sets */
 555         reg = 0x0c;
 556 #if !CONFIG_IS_ENABLED(DM_I2C)
 557         i2c_write(I2C_RETIMER_ADDR2, 0xff, 1, &reg, 1);
 558 #else
 559         dm_i2c_write(dev, 0xff, &reg, 1);
 560 #endif
 561
 562         /* Reset Channel Registers */
 563 #if !CONFIG_IS_ENABLED(DM_I2C)
 564         i2c_read(I2C_RETIMER_ADDR2, 0, 1, &reg, 1);
 565 #else
 566         dm_i2c_read(dev, 0, &reg, 1);
 567 #endif
 568         reg |= 0x4;
 569 #if !CONFIG_IS_ENABLED(DM_I2C)
 570         i2c_write(I2C_RETIMER_ADDR2, 0, 1, &reg, 1);
 571 #else
 572         dm_i2c_write(dev, 0, &reg, 1);
 573 #endif
 574
 575         /* Set data rate as 10.3125 Gbps */
 576         reg = 0x90;
 577 #if !CONFIG_IS_ENABLED(DM_I2C)
 578         i2c_write(I2C_RETIMER_ADDR2, 0x60, 1, &reg, 1);
 579 #else
 580         dm_i2c_write(dev, 0x60, &reg, 1);
 581 #endif
 582         reg = 0xb3;
 583 #if !CONFIG_IS_ENABLED(DM_I2C)
 584         i2c_write(I2C_RETIMER_ADDR2, 0x61, 1, &reg, 1);
 585 #else
 586         dm_i2c_write(dev, 0x61, &reg, 1);
 587 #endif
 588         reg = 0x90;
 589 #if !CONFIG_IS_ENABLED(DM_I2C)
 590         i2c_write(I2C_RETIMER_ADDR2, 0x62, 1, &reg, 1);
 591 #else
 592         dm_i2c_write(dev, 0x62, &reg, 1);
 593 #endif
 594         reg = 0xb3;
 595 #if !CONFIG_IS_ENABLED(DM_I2C)
 596         i2c_write(I2C_RETIMER_ADDR2, 0x63, 1, &reg, 1);
 597 #else
 598         dm_i2c_write(dev, 0x63, &reg, 1);
 599 #endif
 600         reg = 0xcd;
 601 #if !CONFIG_IS_ENABLED(DM_I2C)
 602         i2c_write(I2C_RETIMER_ADDR2, 0x64, 1, &reg, 1);
 603 #else
 604         dm_i2c_write(dev, 0x64, &reg, 1);
 605 #endif
 606
 607         /* Select VCO Divider to full rate (000) */
 608 #if !CONFIG_IS_ENABLED(DM_I2C)
 609         i2c_read(I2C_RETIMER_ADDR2, 0x2F, 1, &reg, 1);
 610 #else
 611         dm_i2c_read(dev, 0x2F, &reg, 1);
 612 #endif
 613         reg &= 0x0f;
 614         reg |= 0x70;
 615 #if !CONFIG_IS_ENABLED(DM_I2C)
 616         i2c_write(I2C_RETIMER_ADDR2, 0x2F, 1, &reg, 1);
 617 #else
 618         dm_i2c_write(dev, 0x2F, &reg, 1);
 619 #endif
 620
 621 #endif
 622         /*return the default channel*/
 623         select_i2c_ch_pca9547(I2C_MUX_CH_DEFAULT);
 624 }
 625
 626 #ifdef CONFIG_MISC_INIT_R
 627 int misc_init_r(void)
 628 {
 629 #ifdef CONFIG_TARGET_LS1088ARDB
 630         u8 brdcfg5;
 631
 632         if (hwconfig("esdhc-force-sd")) {
 633                 brdcfg5 = QIXIS_READ(brdcfg[5]);
 634                 brdcfg5 &= ~BRDCFG5_SPISDHC_MASK;
 635                 brdcfg5 |= BRDCFG5_FORCE_SD;
 636                 QIXIS_WRITE(brdcfg[5], brdcfg5);
 637         }
 638 #endif
 639
 640 #ifdef CONFIG_TARGET_LS1088AQDS
 641          u8 brdcfg4, brdcfg5;
 642
 643         if (hwconfig("dspi-on-board")) {
 644                 brdcfg4 = QIXIS_READ(brdcfg[4]);
 645                 brdcfg4 &= ~BRDCFG4_USBOSC_MASK;
 646                 brdcfg4 |= BRDCFG4_SPI;
 647                 QIXIS_WRITE(brdcfg[4], brdcfg4);
 648
 649                 brdcfg5 = QIXIS_READ(brdcfg[5]);
 650                 brdcfg5 &= ~BRDCFG5_SPR_MASK;
 651                 brdcfg5 |= BRDCFG5_SPI_ON_BOARD;
 652                 QIXIS_WRITE(brdcfg[5], brdcfg5);
 653         } else if (hwconfig("dspi-off-board")) {
 654                 brdcfg4 = QIXIS_READ(brdcfg[4]);
 655                 brdcfg4 &= ~BRDCFG4_USBOSC_MASK;
 656                 brdcfg4 |= BRDCFG4_SPI;
 657                 QIXIS_WRITE(brdcfg[4], brdcfg4);
 658
 659                 brdcfg5 = QIXIS_READ(brdcfg[5]);
 660                 brdcfg5 &= ~BRDCFG5_SPR_MASK;
 661                 brdcfg5 |= BRDCFG5_SPI_OFF_BOARD;
 662                 QIXIS_WRITE(brdcfg[5], brdcfg5);
 663         }
 664 #endif
 665         return 0;
 666 }
 667 #endif
 668 #endif
 669
 670 int i2c_multiplexer_select_vid_channel(u8 channel)
 671 {
 672         return select_i2c_ch_pca9547(channel);
 673 }
 674
 675 #ifdef CONFIG_TARGET_LS1088AQDS
 676 /* read the current value(SVDD) of the LTM Regulator Voltage */
 677 int get_serdes_volt(void)
 678 {
 679         int  ret, vcode = 0;
 680         u8 chan = PWM_CHANNEL0;
 681
 682         /* Select the PAGE 0 using PMBus commands PAGE for VDD */
 683 #if !CONFIG_IS_ENABLED(DM_I2C)
 684         ret = i2c_write(I2C_SVDD_MONITOR_ADDR,
 685                         PMBUS_CMD_PAGE, 1, &chan, 1);
 686 #else
 687         struct udevice *dev;
 688
 689         ret = i2c_get_chip_for_busnum(0, I2C_SVDD_MONITOR_ADDR, 1, &dev);
 690         if (!ret)
 691                 ret = dm_i2c_write(dev, PMBUS_CMD_PAGE,
 692                                    &chan, 1);
 693 #endif
 694
 695         if (ret) {
 696                 printf("VID: failed to select VDD Page 0\n");
 697                 return ret;
 698         }
 699
 700         /* Read the output voltage using PMBus command READ_VOUT */
 701 #if !CONFIG_IS_ENABLED(DM_I2C)
 702         ret = i2c_read(I2C_SVDD_MONITOR_ADDR,
 703                        PMBUS_CMD_READ_VOUT, 1, (void *)&vcode, 2);
 704 #else
 705         dm_i2c_read(dev, PMBUS_CMD_READ_VOUT, (void *)&vcode, 2);
 706 #endif
 707         if (ret) {
 708                 printf("VID: failed to read the volatge\n");
 709                 return ret;
 710         }
 711
 712         return vcode;
 713 }
 714
 715 int set_serdes_volt(int svdd)
 716 {
 717         int ret, vdd_last;
 718         u8 buff[5] = {0x04, PWM_CHANNEL0, PMBUS_CMD_VOUT_COMMAND,
 719                         svdd & 0xFF, (svdd & 0xFF00) >> 8};
 720
 721         /* Write the desired voltage code to the SVDD regulator */
 722 #if !CONFIG_IS_ENABLED(DM_I2C)
 723         ret = i2c_write(I2C_SVDD_MONITOR_ADDR,
 724                         PMBUS_CMD_PAGE_PLUS_WRITE, 1, (void *)&buff, 5);
 725 #else
 726         struct udevice *dev;
 727
 728         ret = i2c_get_chip_for_busnum(0, I2C_SVDD_MONITOR_ADDR, 1, &dev);
 729         if (!ret)
 730                 ret = dm_i2c_write(dev, PMBUS_CMD_PAGE_PLUS_WRITE,
 731                                    (void *)&buff, 5);
 732 #endif
 733         if (ret) {
 734                 printf("VID: I2C failed to write to the volatge regulator\n");
 735                 return -1;
 736         }
 737
 738         /* Wait for the volatge to get to the desired value */
 739         do {
 740                 vdd_last = get_serdes_volt();
 741                 if (vdd_last < 0) {
 742                         printf("VID: Couldn't read sensor abort VID adjust\n");
 743                         return -1;
 744                 }
 745         } while (vdd_last != svdd);
 746
 747         return 1;
 748 }
 749 #else
 750 int get_serdes_volt(void)
 751 {
 752         return 0;
 753 }
 754
 755 int set_serdes_volt(int svdd)
 756 {
 757         int ret;
 758         u8 brdcfg4;
 759
 760         printf("SVDD changing of RDB\n");
 761
 762         /* Read the BRDCFG54 via CLPD */
 763 #if !CONFIG_IS_ENABLED(DM_I2C)
 764         ret = i2c_read(CONFIG_SYS_I2C_FPGA_ADDR,
 765                        QIXIS_BRDCFG4_OFFSET, 1, (void *)&brdcfg4, 1);
 766 #else
 767         struct udevice *dev;
 768
 769         ret = i2c_get_chip_for_busnum(0, CONFIG_SYS_I2C_FPGA_ADDR, 1, &dev);
 770         if (!ret)
 771                 ret = dm_i2c_read(dev, QIXIS_BRDCFG4_OFFSET,
 772                                   (void *)&brdcfg4, 1);
 773 #endif
 774
 775         if (ret) {
 776                 printf("VID: I2C failed to read the CPLD BRDCFG4\n");
 777                 return -1;
 778         }
 779
 780         brdcfg4 = brdcfg4 | 0x08;
 781
 782         /* Write to the BRDCFG4 */
 783 #if !CONFIG_IS_ENABLED(DM_I2C)
 784         ret = i2c_write(CONFIG_SYS_I2C_FPGA_ADDR,
 785                         QIXIS_BRDCFG4_OFFSET, 1, (void *)&brdcfg4, 1);
 786 #else
 787         ret = dm_i2c_write(dev, QIXIS_BRDCFG4_OFFSET,
 788                            (void *)&brdcfg4, 1);
 789 #endif
 790
 791         if (ret) {
 792                 debug("VID: I2C failed to set the SVDD CPLD BRDCFG4\n");
 793                 return -1;
 794         }
 795
 796         /* Wait for the volatge to get to the desired value */
 797         udelay(10000);
 798
 799         return 1;
 800 }
 801 #endif
 802
 803 /* this function disables the SERDES, changes the SVDD Voltage and enables it*/
 804 int board_adjust_vdd(int vdd)
 805 {
 806         int ret = 0;
 807
 808         debug("%s: vdd = %d\n", __func__, vdd);
 809
 810         /* Special settings to be performed when voltage is 900mV */
 811         if (vdd == 900) {
 812                 ret = setup_serdes_volt(vdd);
 813                 if (ret < 0) {
 814                         ret = -1;
 815                         goto exit;
 816                 }
 817         }
 818 exit:
 819         return ret;
 820 }
 821
 822 #if !defined(CONFIG_SPL_BUILD)
 823 int board_init(void)
 824 {
 825         init_final_memctl_regs();
 826 #if defined(CONFIG_TARGET_LS1088ARDB) && defined(CONFIG_FSL_MC_ENET)
 827         u32 __iomem *irq_ccsr = (u32 __iomem *)ISC_BASE;
 828 #endif
 829
 830         select_i2c_ch_pca9547(I2C_MUX_CH_DEFAULT);
 831         board_retimer_init();
 832
 833 #ifdef CONFIG_ENV_IS_NOWHERE
 834         gd->env_addr = (ulong)&default_environment[0];
 835 #endif
 836
 837 #if defined(CONFIG_TARGET_LS1088ARDB) && defined(CONFIG_FSL_MC_ENET)
 838         /* invert AQR105 IRQ pins polarity */
 839         out_le32(irq_ccsr + IRQCR_OFFSET / 4, AQR105_IRQ_MASK);
 840 #endif
 841
 842 #ifdef CONFIG_FSL_CAAM
 843         sec_init();
 844 #endif
 845 #ifdef CONFIG_FSL_LS_PPA
 846         ppa_init();
 847 #endif
 848
 849 #if !defined(CONFIG_SYS_EARLY_PCI_INIT) && defined(CONFIG_DM_ETH)
 850         pci_init();
 851 #endif
 852
 853         return 0;
 854 }
 855
 856 void detail_board_ddr_info(void)
 857 {
 858         puts("\nDDR    ");
 859         print_size(gd->bd->bi_dram[0].size + gd->bd->bi_dram[1].size, "");
 860         print_ddr_info(0);
 861 }
 862
 863 #ifdef CONFIG_FSL_MC_ENET
 864 void board_quiesce_devices(void)
 865 {
 866         fsl_mc_ldpaa_exit(gd->bd);
 867 }
 868
 869 void fdt_fixup_board_enet(void *fdt)
 870 {
 871         int offset;
 872
 873         offset = fdt_path_offset(fdt, "/fsl-mc");
 874
 875         if (offset < 0)
 876                 offset = fdt_path_offset(fdt, "/soc/fsl-mc");
 877
 878         if (offset < 0) {
 879                 printf("%s: ERROR: fsl-mc node not found in device tree (error %d)\n",
 880                        __func__, offset);
 881                 return;
 882         }
 883
 884         if (get_mc_boot_status() == 0 &&
 885             (is_lazy_dpl_addr_valid() || get_dpl_apply_status() == 0))
 886                 fdt_status_okay(fdt, offset);
 887         else
 888                 fdt_status_fail(fdt, offset);
 889 }
 890 #endif
 891
 892 #ifdef CONFIG_OF_BOARD_SETUP
 893 void fsl_fdt_fixup_flash(void *fdt)
 894 {
 895         int offset;
 896 #ifdef CONFIG_TFABOOT
 897         u32 __iomem *dcfg_ccsr = (u32 __iomem *)DCFG_BASE;
 898         u32 val;
 899 #endif
 900
 901 /*
 902  * IFC-NOR and QSPI are muxed on SoC.
 903  * So disable IFC node in dts if QSPI is enabled or
 904  * disable QSPI node in dts in case QSPI is not enabled.
 905  */
 906
 907 #ifdef CONFIG_TFABOOT
 908         enum boot_src src = get_boot_src();
 909         bool disable_ifc = false;
 910
 911         switch (src) {
 912         case BOOT_SOURCE_IFC_NOR:
 913                 disable_ifc = false;
 914                 break;
 915         case BOOT_SOURCE_QSPI_NOR:
 916                 disable_ifc = true;
 917                 break;
 918         default:
 919                 val = in_le32(dcfg_ccsr + DCFG_RCWSR15 / 4);
 920                 if (DCFG_RCWSR15_IFCGRPABASE_QSPI == (val & (u32)0x3))
 921                         disable_ifc = true;
 922                 break;
 923         }
 924
 925         if (disable_ifc) {
 926                 offset = fdt_path_offset(fdt, "/soc/ifc/nor");
 927
 928                 if (offset < 0)
 929                         offset = fdt_path_offset(fdt, "/ifc/nor");
 930         } else {
 931                 offset = fdt_path_offset(fdt, "/soc/quadspi");
 932
 933                 if (offset < 0)
 934                         offset = fdt_path_offset(fdt, "/quadspi");
 935         }
 936
 937 #else
 938 #ifdef CONFIG_FSL_QSPI
 939         offset = fdt_path_offset(fdt, "/soc/ifc/nor");
 940
 941         if (offset < 0)
 942                 offset = fdt_path_offset(fdt, "/ifc/nor");
 943 #else
 944         offset = fdt_path_offset(fdt, "/soc/quadspi");
 945
 946         if (offset < 0)
 947                 offset = fdt_path_offset(fdt, "/quadspi");
 948 #endif
 949 #endif
 950         if (offset < 0)
 951                 return;
 952
 953         fdt_status_disabled(fdt, offset);
 954 }
 955
 956 int ft_board_setup(void *blob, struct bd_info *bd)
 957 {
 958         int i;
 959         u16 mc_memory_bank = 0;
 960
 961         u64 *base;
 962         u64 *size;
 963         u64 mc_memory_base = 0;
 964         u64 mc_memory_size = 0;
 965         u16 total_memory_banks;
 966
 967         ft_cpu_setup(blob, bd);
 968
 969         fdt_fixup_mc_ddr(&mc_memory_base, &mc_memory_size);
 970
 971         if (mc_memory_base != 0)
 972                 mc_memory_bank++;
 973
 974         total_memory_banks = CONFIG_NR_DRAM_BANKS + mc_memory_bank;
 975
 976         base = calloc(total_memory_banks, sizeof(u64));
 977         size = calloc(total_memory_banks, sizeof(u64));
 978
 979         /* fixup DT for the two GPP DDR banks */
 980         for (i = 0; i < CONFIG_NR_DRAM_BANKS; i++) {
 981                 base[i] = gd->bd->bi_dram[i].start;
 982                 size[i] = gd->bd->bi_dram[i].size;
 983         }
 984
 985 #ifdef CONFIG_RESV_RAM
 986         /* reduce size if reserved memory is within this bank */
 987         if (gd->arch.resv_ram >= base[0] &&
 988             gd->arch.resv_ram < base[0] + size[0])
 989                 size[0] = gd->arch.resv_ram - base[0];
 990         else if (gd->arch.resv_ram >= base[1] &&
 991                  gd->arch.resv_ram < base[1] + size[1])
 992                 size[1] = gd->arch.resv_ram - base[1];
 993 #endif
 994
 995         if (mc_memory_base != 0) {
 996                 for (i = 0; i <= total_memory_banks; i++) {
 997                         if (base[i] == 0 && size[i] == 0) {
 998                                 base[i] = mc_memory_base;
 999                                 size[i] = mc_memory_size;
1000                                 break;
1001                         }
1002                 }
1003         }
1004
1005         fdt_fixup_memory_banks(blob, base, size, total_memory_banks);
1006
1007         fdt_fsl_mc_fixup_iommu_map_entry(blob);
1008
1009         fsl_fdt_fixup_flash(blob);
1010
1011 #ifdef CONFIG_FSL_MC_ENET
1012         fdt_fixup_board_enet(blob);
1013 #endif
1014
1015         fdt_fixup_icid(blob);
1016
1017         if (is_pb_board())
1018                 fixup_ls1088ardb_pb_banner(blob);
1019
1020         return 0;
1021 }
1022 #endif
1023 #endif /* defined(CONFIG_SPL_BUILD) */
1024
1025 #ifdef CONFIG_TFABOOT
1026 #ifdef CONFIG_MTD_NOR_FLASH
1027 int is_flash_available(void)
1028 {
1029         char *env_hwconfig = env_get("hwconfig");
1030         enum boot_src src = get_boot_src();
1031         int is_nor_flash_available = 1;
1032
1033         switch (src) {
1034         case BOOT_SOURCE_IFC_NOR:
1035                 is_nor_flash_available = 1;
1036                 break;
1037         case BOOT_SOURCE_QSPI_NOR:
1038                 is_nor_flash_available = 0;
1039                 break;
1040         /*
1041          * In Case of SD boot,if qspi is defined in env_hwconfig
1042          * disable nor flash probe.
1043          */
1044         default:
1045                 if (hwconfig_f("qspi", env_hwconfig))
1046                         is_nor_flash_available = 0;
1047                 break;
1048         }
1049         return is_nor_flash_available;
1050 }
1051 #endif
1052
1053 #ifdef CONFIG_ENV_IS_IN_SPI_FLASH
1054 void *env_sf_get_env_addr(void)
1055 {
1056         return (void *)(CONFIG_SYS_FSL_QSPI_BASE + CONFIG_ENV_OFFSET);
1057 }
1058 #endif
1059 #endif