board/freescale/ls1088a/ls1088a.c

   1 // SPDX-License-Identifier: GPL-2.0+
   2 /*
   3  * Copyright 2017-2018 NXP
   4  */
   5 #include <common.h>
   6 #include <env.h>
   7 #include <i2c.h>
   8 #include <init.h>
   9 #include <log.h>
  10 #include <malloc.h>
  11 #include <errno.h>
  12 #include <netdev.h>
  13 #include <fsl_ifc.h>
  14 #include <fsl_ddr.h>
  15 #include <fsl_sec.h>
  16 #include <asm/global_data.h>
  17 #include <asm/io.h>
  18 #include <fdt_support.h>
  19 #include <linux/delay.h>
  20 #include <linux/libfdt.h>
  21 #include <fsl-mc/fsl_mc.h>
  22 #include <env_internal.h>
  23 #include <asm/arch-fsl-layerscape/soc.h>
  24 #include <asm/arch/ppa.h>
  25 #include <hwconfig.h>
  26 #include <asm/arch/fsl_serdes.h>
  27 #include <asm/arch/soc.h>
  28 #include <asm/arch-fsl-layerscape/fsl_icid.h>
  29
  30 #include "../common/qixis.h"
  31 #include "ls1088a_qixis.h"
  32 #include "../common/vid.h"
  33 #include <fsl_immap.h>
  34
  35 DECLARE_GLOBAL_DATA_PTR;
  36
  37 #ifdef CONFIG_TARGET_LS1088AQDS
  38 #ifdef CONFIG_TFABOOT
  39 struct ifc_regs ifc_cfg_ifc_nor_boot[CONFIG_SYS_FSL_IFC_BANK_COUNT] = {
  40         {
  41                 "nor0",
  42                 CONFIG_SYS_NOR0_CSPR_EARLY,
  43                 CONFIG_SYS_NOR0_CSPR_EXT,
  44                 CONFIG_SYS_NOR_AMASK,
  45                 CONFIG_SYS_NOR_CSOR,
  46                 {
  47                         CONFIG_SYS_NOR_FTIM0,
  48                         CONFIG_SYS_NOR_FTIM1,
  49                         CONFIG_SYS_NOR_FTIM2,
  50                         CONFIG_SYS_NOR_FTIM3
  51                 },
  52                 0,
  53                 CONFIG_SYS_NOR0_CSPR,
  54                 0,
  55         },
  56         {
  57                 "nor1",
  58                 CONFIG_SYS_NOR1_CSPR_EARLY,
  59                 CONFIG_SYS_NOR0_CSPR_EXT,
  60                 CONFIG_SYS_NOR_AMASK_EARLY,
  61                 CONFIG_SYS_NOR_CSOR,
  62                 {
  63                         CONFIG_SYS_NOR_FTIM0,
  64                         CONFIG_SYS_NOR_FTIM1,
  65                         CONFIG_SYS_NOR_FTIM2,
  66                         CONFIG_SYS_NOR_FTIM3
  67                 },
  68                 0,
  69                 CONFIG_SYS_NOR1_CSPR,
  70                 CONFIG_SYS_NOR_AMASK,
  71         },
  72         {
  73                 "nand",
  74                 CONFIG_SYS_NAND_CSPR,
  75                 CONFIG_SYS_NAND_CSPR_EXT,
  76                 CONFIG_SYS_NAND_AMASK,
  77                 CONFIG_SYS_NAND_CSOR,
  78                 {
  79                         CONFIG_SYS_NAND_FTIM0,
  80                         CONFIG_SYS_NAND_FTIM1,
  81                         CONFIG_SYS_NAND_FTIM2,
  82                         CONFIG_SYS_NAND_FTIM3
  83                 },
  84         },
  85         {
  86                 "fpga",
  87                 CONFIG_SYS_FPGA_CSPR,
  88                 CONFIG_SYS_FPGA_CSPR_EXT,
  89                 SYS_FPGA_AMASK,
  90                 CONFIG_SYS_FPGA_CSOR,
  91                 {
  92                         SYS_FPGA_CS_FTIM0,
  93                         SYS_FPGA_CS_FTIM1,
  94                         SYS_FPGA_CS_FTIM2,
  95                         SYS_FPGA_CS_FTIM3
  96                 },
  97                 0,
  98                 SYS_FPGA_CSPR_FINAL,
  99                 0,
 100         }
 101 };
 102
 103 struct ifc_regs ifc_cfg_qspi_nor_boot[CONFIG_SYS_FSL_IFC_BANK_COUNT] = {
 104         {
 105                 "nand",
 106                 CONFIG_SYS_NAND_CSPR,
 107                 CONFIG_SYS_NAND_CSPR_EXT,
 108                 CONFIG_SYS_NAND_AMASK,
 109                 CONFIG_SYS_NAND_CSOR,
 110                 {
 111                         CONFIG_SYS_NAND_FTIM0,
 112                         CONFIG_SYS_NAND_FTIM1,
 113                         CONFIG_SYS_NAND_FTIM2,
 114                         CONFIG_SYS_NAND_FTIM3
 115                 },
 116         },
 117         {
 118                 "reserved",
 119         },
 120         {
 121                 "fpga",
 122                 CONFIG_SYS_FPGA_CSPR,
 123                 CONFIG_SYS_FPGA_CSPR_EXT,
 124                 SYS_FPGA_AMASK,
 125                 CONFIG_SYS_FPGA_CSOR,
 126                 {
 127                         SYS_FPGA_CS_FTIM0,
 128                         SYS_FPGA_CS_FTIM1,
 129                         SYS_FPGA_CS_FTIM2,
 130                         SYS_FPGA_CS_FTIM3
 131                 },
 132                 0,
 133                 SYS_FPGA_CSPR_FINAL,
 134                 0,
 135         }
 136 };
 137
 138 void ifc_cfg_boot_info(struct ifc_regs_info *regs_info)
 139 {
 140         enum boot_src src = get_boot_src();
 141
 142         if (src == BOOT_SOURCE_QSPI_NOR)
 143                 regs_info->regs = ifc_cfg_qspi_nor_boot;
 144         else
 145                 regs_info->regs = ifc_cfg_ifc_nor_boot;
 146
 147         regs_info->cs_size = CONFIG_SYS_FSL_IFC_BANK_COUNT;
 148 }
 149 #endif /* CONFIG_TFABOOT */
 150 #endif /* CONFIG_TARGET_LS1088AQDS */
 151
 152 int board_early_init_f(void)
 153 {
 154 #if defined(CONFIG_SYS_I2C_EARLY_INIT) && defined(CONFIG_TARGET_LS1088AQDS)
 155         i2c_early_init_f();
 156 #endif
 157         fsl_lsch3_early_init_f();
 158         return 0;
 159 }
 160
 161 #ifdef CONFIG_FSL_QIXIS
 162 unsigned long long get_qixis_addr(void)
 163 {
 164         unsigned long long addr;
 165
 166         if (gd->flags & GD_FLG_RELOC)
 167                 addr = QIXIS_BASE_PHYS;
 168         else
 169                 addr = QIXIS_BASE_PHYS_EARLY;
 170
 171         /*
 172          * IFC address under 256MB is mapped to 0x30000000, any address above
 173          * is mapped to 0x5_10000000 up to 4GB.
 174          */
 175         addr = addr  > 0x10000000 ? addr + 0x500000000ULL : addr + 0x30000000;
 176
 177         return addr;
 178 }
 179 #endif
 180
 181 #if defined(CONFIG_VID)
 182 int init_func_vid(void)
 183 {
 184         if (adjust_vdd(0) < 0)
 185                 printf("core voltage not adjusted\n");
 186
 187         return 0;
 188 }
 189 #endif
 190
 191 int is_pb_board(void)
 192 {
 193         u8 board_id;
 194
 195         board_id = QIXIS_READ(id);
 196         if (board_id == LS1088ARDB_PB_BOARD)
 197                 return 1;
 198         else
 199                 return 0;
 200 }
 201
 202 int fixup_ls1088ardb_pb_banner(void *fdt)
 203 {
 204         fdt_setprop_string(fdt, 0, "model", "LS1088ARDB-PB Board");
 205
 206         return 0;
 207 }
 208
 209 #if !defined(CONFIG_SPL_BUILD)
 210 int checkboard(void)
 211 {
 212 #ifdef CONFIG_TFABOOT
 213         enum boot_src src = get_boot_src();
 214 #endif
 215         char buf[64];
 216         u8 sw;
 217         static const char *const freq[] = {"100", "125", "156.25",
 218                                             "100 separate SSCG"};
 219         int clock;
 220
 221 #ifdef CONFIG_TARGET_LS1088AQDS
 222         printf("Board: LS1088A-QDS, ");
 223 #else
 224         if (is_pb_board())
 225                 printf("Board: LS1088ARDB-PB, ");
 226         else
 227                 printf("Board: LS1088A-RDB, ");
 228 #endif
 229
 230         sw = QIXIS_READ(arch);
 231         printf("Board Arch: V%d, ", sw >> 4);
 232
 233 #ifdef CONFIG_TARGET_LS1088AQDS
 234         printf("Board version: %c, boot from ", (sw & 0xf) + 'A' - 1);
 235 #else
 236         printf("Board version: %c, boot from ", (sw & 0xf) + 'A');
 237 #endif
 238
 239         memset((u8 *)buf, 0x00, ARRAY_SIZE(buf));
 240
 241         sw = QIXIS_READ(brdcfg[0]);
 242         sw = (sw & QIXIS_LBMAP_MASK) >> QIXIS_LBMAP_SHIFT;
 243
 244 #ifdef CONFIG_TFABOOT
 245         if (src == BOOT_SOURCE_SD_MMC)
 246                 puts("SD card\n");
 247 #else
 248 #ifdef CONFIG_SD_BOOT
 249         puts("SD card\n");
 250 #endif
 251 #endif /* CONFIG_TFABOOT */
 252         switch (sw) {
 253 #ifdef CONFIG_TARGET_LS1088AQDS
 254         case 0:
 255         case 1:
 256         case 2:
 257         case 3:
 258         case 4:
 259         case 5:
 260         case 6:
 261         case 7:
 262                 printf("vBank: %d\n", sw);
 263                 break;
 264         case 8:
 265                 puts("PromJet\n");
 266                 break;
 267         case 15:
 268                 puts("IFCCard\n");
 269                 break;
 270         case 14:
 271 #else
 272         case 0:
 273 #endif
 274                 puts("QSPI:");
 275                 sw = QIXIS_READ(brdcfg[0]);
 276                 sw = (sw & QIXIS_QMAP_MASK) >> QIXIS_QMAP_SHIFT;
 277                 if (sw == 0 || sw == 4)
 278                         puts("0\n");
 279                 else if (sw == 1)
 280                         puts("1\n");
 281                 else
 282                         puts("EMU\n");
 283                 break;
 284
 285         default:
 286                 printf("invalid setting of SW%u\n", QIXIS_LBMAP_SWITCH);
 287                 break;
 288         }
 289
 290 #ifdef CONFIG_TARGET_LS1088AQDS
 291         printf("FPGA: v%d (%s), build %d",
 292                (int)QIXIS_READ(scver), qixis_read_tag(buf),
 293                (int)qixis_read_minor());
 294         /* the timestamp string contains "\n" at the end */
 295         printf(" on %s", qixis_read_time(buf));
 296 #else
 297         printf("CPLD: v%d.%d\n", QIXIS_READ(scver), QIXIS_READ(tagdata));
 298 #endif
 299
 300         /*
 301          * Display the actual SERDES reference clocks as configured by the
 302          * dip switches on the board.  Note that the SWx registers could
 303          * technically be set to force the reference clocks to match the
 304          * values that the SERDES expects (or vice versa).  For now, however,
 305          * we just display both values and hope the user notices when they
 306          * don't match.
 307          */
 308         puts("SERDES1 Reference : ");
 309         sw = QIXIS_READ(brdcfg[2]);
 310         clock = (sw >> 6) & 3;
 311         printf("Clock1 = %sMHz ", freq[clock]);
 312         clock = (sw >> 4) & 3;
 313         printf("Clock2 = %sMHz", freq[clock]);
 314
 315         puts("\nSERDES2 Reference : ");
 316         clock = (sw >> 2) & 3;
 317         printf("Clock1 = %sMHz ", freq[clock]);
 318         clock = (sw >> 0) & 3;
 319         printf("Clock2 = %sMHz\n", freq[clock]);
 320
 321         return 0;
 322 }
 323 #endif
 324
 325 bool if_board_diff_clk(void)
 326 {
 327 #ifdef CONFIG_TARGET_LS1088AQDS
 328         u8 diff_conf = QIXIS_READ(brdcfg[11]);
 329         return diff_conf & 0x40;
 330 #else
 331         u8 diff_conf = QIXIS_READ(dutcfg[11]);
 332         return diff_conf & 0x80;
 333 #endif
 334 }
 335
 336 unsigned long get_board_sys_clk(void)
 337 {
 338         u8 sysclk_conf = QIXIS_READ(brdcfg[1]);
 339
 340         switch (sysclk_conf & 0x0f) {
 341         case QIXIS_SYSCLK_83:
 342                 return 83333333;
 343         case QIXIS_SYSCLK_100:
 344                 return 100000000;
 345         case QIXIS_SYSCLK_125:
 346                 return 125000000;
 347         case QIXIS_SYSCLK_133:
 348                 return 133333333;
 349         case QIXIS_SYSCLK_150:
 350                 return 150000000;
 351         case QIXIS_SYSCLK_160:
 352                 return 160000000;
 353         case QIXIS_SYSCLK_166:
 354                 return 166666666;
 355         }
 356
 357         return 66666666;
 358 }
 359
 360 unsigned long get_board_ddr_clk(void)
 361 {
 362         u8 ddrclk_conf = QIXIS_READ(brdcfg[1]);
 363
 364         if (if_board_diff_clk())
 365                 return get_board_sys_clk();
 366         switch ((ddrclk_conf & 0x30) >> 4) {
 367         case QIXIS_DDRCLK_100:
 368                 return 100000000;
 369         case QIXIS_DDRCLK_125:
 370                 return 125000000;
 371         case QIXIS_DDRCLK_133:
 372                 return 133333333;
 373         }
 374
 375         return 66666666;
 376 }
 377
 378 int select_i2c_ch_pca9547(u8 ch)
 379 {
 380         int ret;
 381
 382 #if !CONFIG_IS_ENABLED(DM_I2C)
 383         ret = i2c_write(I2C_MUX_PCA_ADDR_PRI, 0, 1, &ch, 1);
 384 #else
 385         struct udevice *dev;
 386
 387         ret = i2c_get_chip_for_busnum(0, I2C_MUX_PCA_ADDR_PRI, 1, &dev);
 388         if (!ret)
 389                 ret = dm_i2c_write(dev, 0, &ch, 1);
 390 #endif
 391         if (ret) {
 392                 puts("PCA: failed to select proper channel\n");
 393                 return ret;
 394         }
 395
 396         return 0;
 397 }
 398
 399 #if !defined(CONFIG_SPL_BUILD)
 400 void board_retimer_init(void)
 401 {
 402         u8 reg;
 403
 404         /* Retimer is connected to I2C1_CH5 */
 405         select_i2c_ch_pca9547(I2C_MUX_CH5);
 406
 407         /* Access to Control/Shared register */
 408         reg = 0x0;
 409 #if !CONFIG_IS_ENABLED(DM_I2C)
 410         i2c_write(I2C_RETIMER_ADDR, 0xff, 1, &reg, 1);
 411 #else
 412         struct udevice *dev;
 413
 414         i2c_get_chip_for_busnum(0, I2C_RETIMER_ADDR, 1, &dev);
 415         dm_i2c_write(dev, 0xff, &reg, 1);
 416 #endif
 417
 418         /* Read device revision and ID */
 419 #if !CONFIG_IS_ENABLED(DM_I2C)
 420         i2c_read(I2C_RETIMER_ADDR, 1, 1, &reg, 1);
 421 #else
 422         dm_i2c_read(dev, 1, &reg, 1);
 423 #endif
 424         debug("Retimer version id = 0x%x\n", reg);
 425
 426         /* Enable Broadcast. All writes target all channel register sets */
 427         reg = 0x0c;
 428 #if !CONFIG_IS_ENABLED(DM_I2C)
 429         i2c_write(I2C_RETIMER_ADDR, 0xff, 1, &reg, 1);
 430 #else
 431         dm_i2c_write(dev, 0xff, &reg, 1);
 432 #endif
 433
 434         /* Reset Channel Registers */
 435 #if !CONFIG_IS_ENABLED(DM_I2C)
 436         i2c_read(I2C_RETIMER_ADDR, 0, 1, &reg, 1);
 437 #else
 438         dm_i2c_read(dev, 0, &reg, 1);
 439 #endif
 440         reg |= 0x4;
 441 #if !CONFIG_IS_ENABLED(DM_I2C)
 442         i2c_write(I2C_RETIMER_ADDR, 0, 1, &reg, 1);
 443 #else
 444         dm_i2c_write(dev, 0, &reg, 1);
 445 #endif
 446
 447         /* Set data rate as 10.3125 Gbps */
 448         reg = 0x90;
 449 #if !CONFIG_IS_ENABLED(DM_I2C)
 450         i2c_write(I2C_RETIMER_ADDR, 0x60, 1, &reg, 1);
 451 #else
 452         dm_i2c_write(dev, 0x60, &reg, 1);
 453 #endif
 454         reg = 0xb3;
 455 #if !CONFIG_IS_ENABLED(DM_I2C)
 456         i2c_write(I2C_RETIMER_ADDR, 0x61, 1, &reg, 1);
 457 #else
 458         dm_i2c_write(dev, 0x61, &reg, 1);
 459 #endif
 460         reg = 0x90;
 461 #if !CONFIG_IS_ENABLED(DM_I2C)
 462         i2c_write(I2C_RETIMER_ADDR, 0x62, 1, &reg, 1);
 463 #else
 464         dm_i2c_write(dev, 0x62, &reg, 1);
 465 #endif
 466         reg = 0xb3;
 467 #if !CONFIG_IS_ENABLED(DM_I2C)
 468         i2c_write(I2C_RETIMER_ADDR, 0x63, 1, &reg, 1);
 469 #else
 470         dm_i2c_write(dev, 0x63, &reg, 1);
 471 #endif
 472         reg = 0xcd;
 473 #if !CONFIG_IS_ENABLED(DM_I2C)
 474         i2c_write(I2C_RETIMER_ADDR, 0x64, 1, &reg, 1);
 475 #else
 476         dm_i2c_write(dev, 0x64, &reg, 1);
 477 #endif
 478
 479         /* Select VCO Divider to full rate (000) */
 480 #if !CONFIG_IS_ENABLED(DM_I2C)
 481         i2c_read(I2C_RETIMER_ADDR, 0x2F, 1, &reg, 1);
 482 #else
 483         dm_i2c_read(dev, 0x2F, &reg, 1);
 484 #endif
 485         reg &= 0x0f;
 486         reg |= 0x70;
 487 #if !CONFIG_IS_ENABLED(DM_I2C)
 488         i2c_write(I2C_RETIMER_ADDR, 0x2F, 1, &reg, 1);
 489 #else
 490         dm_i2c_write(dev, 0x2F, &reg, 1);
 491 #endif
 492
 493 #ifdef  CONFIG_TARGET_LS1088AQDS
 494         /* Retimer is connected to I2C1_CH5 */
 495         select_i2c_ch_pca9547(I2C_MUX_CH5);
 496
 497         /* Access to Control/Shared register */
 498         reg = 0x0;
 499 #if !CONFIG_IS_ENABLED(DM_I2C)
 500         i2c_write(I2C_RETIMER_ADDR2, 0xff, 1, &reg, 1);
 501 #else
 502         i2c_get_chip_for_busnum(0, I2C_RETIMER_ADDR2, 1, &dev);
 503         dm_i2c_write(dev, 0xff, &reg, 1);
 504 #endif
 505
 506         /* Read device revision and ID */
 507 #if !CONFIG_IS_ENABLED(DM_I2C)
 508         i2c_read(I2C_RETIMER_ADDR2, 1, 1, &reg, 1);
 509 #else
 510         dm_i2c_read(dev, 1, &reg, 1);
 511 #endif
 512         debug("Retimer version id = 0x%x\n", reg);
 513
 514         /* Enable Broadcast. All writes target all channel register sets */
 515         reg = 0x0c;
 516 #if !CONFIG_IS_ENABLED(DM_I2C)
 517         i2c_write(I2C_RETIMER_ADDR2, 0xff, 1, &reg, 1);
 518 #else
 519         dm_i2c_write(dev, 0xff, &reg, 1);
 520 #endif
 521
 522         /* Reset Channel Registers */
 523 #if !CONFIG_IS_ENABLED(DM_I2C)
 524         i2c_read(I2C_RETIMER_ADDR2, 0, 1, &reg, 1);
 525 #else
 526         dm_i2c_read(dev, 0, &reg, 1);
 527 #endif
 528         reg |= 0x4;
 529 #if !CONFIG_IS_ENABLED(DM_I2C)
 530         i2c_write(I2C_RETIMER_ADDR2, 0, 1, &reg, 1);
 531 #else
 532         dm_i2c_write(dev, 0, &reg, 1);
 533 #endif
 534
 535         /* Set data rate as 10.3125 Gbps */
 536         reg = 0x90;
 537 #if !CONFIG_IS_ENABLED(DM_I2C)
 538         i2c_write(I2C_RETIMER_ADDR2, 0x60, 1, &reg, 1);
 539 #else
 540         dm_i2c_write(dev, 0x60, &reg, 1);
 541 #endif
 542         reg = 0xb3;
 543 #if !CONFIG_IS_ENABLED(DM_I2C)
 544         i2c_write(I2C_RETIMER_ADDR2, 0x61, 1, &reg, 1);
 545 #else
 546         dm_i2c_write(dev, 0x61, &reg, 1);
 547 #endif
 548         reg = 0x90;
 549 #if !CONFIG_IS_ENABLED(DM_I2C)
 550         i2c_write(I2C_RETIMER_ADDR2, 0x62, 1, &reg, 1);
 551 #else
 552         dm_i2c_write(dev, 0x62, &reg, 1);
 553 #endif
 554         reg = 0xb3;
 555 #if !CONFIG_IS_ENABLED(DM_I2C)
 556         i2c_write(I2C_RETIMER_ADDR2, 0x63, 1, &reg, 1);
 557 #else
 558         dm_i2c_write(dev, 0x63, &reg, 1);
 559 #endif
 560         reg = 0xcd;
 561 #if !CONFIG_IS_ENABLED(DM_I2C)
 562         i2c_write(I2C_RETIMER_ADDR2, 0x64, 1, &reg, 1);
 563 #else
 564         dm_i2c_write(dev, 0x64, &reg, 1);
 565 #endif
 566
 567         /* Select VCO Divider to full rate (000) */
 568 #if !CONFIG_IS_ENABLED(DM_I2C)
 569         i2c_read(I2C_RETIMER_ADDR2, 0x2F, 1, &reg, 1);
 570 #else
 571         dm_i2c_read(dev, 0x2F, &reg, 1);
 572 #endif
 573         reg &= 0x0f;
 574         reg |= 0x70;
 575 #if !CONFIG_IS_ENABLED(DM_I2C)
 576         i2c_write(I2C_RETIMER_ADDR2, 0x2F, 1, &reg, 1);
 577 #else
 578         dm_i2c_write(dev, 0x2F, &reg, 1);
 579 #endif
 580
 581 #endif
 582         /*return the default channel*/
 583         select_i2c_ch_pca9547(I2C_MUX_CH_DEFAULT);
 584 }
 585
 586 #ifdef CONFIG_MISC_INIT_R
 587 int misc_init_r(void)
 588 {
 589 #ifdef CONFIG_TARGET_LS1088ARDB
 590         u8 brdcfg5;
 591
 592         if (hwconfig("esdhc-force-sd")) {
 593                 brdcfg5 = QIXIS_READ(brdcfg[5]);
 594                 brdcfg5 &= ~BRDCFG5_SPISDHC_MASK;
 595                 brdcfg5 |= BRDCFG5_FORCE_SD;
 596                 QIXIS_WRITE(brdcfg[5], brdcfg5);
 597         }
 598 #endif
 599
 600 #ifdef CONFIG_TARGET_LS1088AQDS
 601          u8 brdcfg4, brdcfg5;
 602
 603         if (hwconfig("dspi-on-board")) {
 604                 brdcfg4 = QIXIS_READ(brdcfg[4]);
 605                 brdcfg4 &= ~BRDCFG4_USBOSC_MASK;
 606                 brdcfg4 |= BRDCFG4_SPI;
 607                 QIXIS_WRITE(brdcfg[4], brdcfg4);
 608
 609                 brdcfg5 = QIXIS_READ(brdcfg[5]);
 610                 brdcfg5 &= ~BRDCFG5_SPR_MASK;
 611                 brdcfg5 |= BRDCFG5_SPI_ON_BOARD;
 612                 QIXIS_WRITE(brdcfg[5], brdcfg5);
 613         } else if (hwconfig("dspi-off-board")) {
 614                 brdcfg4 = QIXIS_READ(brdcfg[4]);
 615                 brdcfg4 &= ~BRDCFG4_USBOSC_MASK;
 616                 brdcfg4 |= BRDCFG4_SPI;
 617                 QIXIS_WRITE(brdcfg[4], brdcfg4);
 618
 619                 brdcfg5 = QIXIS_READ(brdcfg[5]);
 620                 brdcfg5 &= ~BRDCFG5_SPR_MASK;
 621                 brdcfg5 |= BRDCFG5_SPI_OFF_BOARD;
 622                 QIXIS_WRITE(brdcfg[5], brdcfg5);
 623         }
 624 #endif
 625         return 0;
 626 }
 627 #endif
 628 #endif
 629
 630 int i2c_multiplexer_select_vid_channel(u8 channel)
 631 {
 632         return select_i2c_ch_pca9547(channel);
 633 }
 634
 635 #ifdef CONFIG_TARGET_LS1088AQDS
 636 /* read the current value(SVDD) of the LTM Regulator Voltage */
 637 int get_serdes_volt(void)
 638 {
 639         int  ret, vcode = 0;
 640         u8 chan = PWM_CHANNEL0;
 641
 642         /* Select the PAGE 0 using PMBus commands PAGE for VDD */
 643 #if !CONFIG_IS_ENABLED(DM_I2C)
 644         ret = i2c_write(I2C_SVDD_MONITOR_ADDR,
 645                         PMBUS_CMD_PAGE, 1, &chan, 1);
 646 #else
 647         struct udevice *dev;
 648
 649         ret = i2c_get_chip_for_busnum(0, I2C_SVDD_MONITOR_ADDR, 1, &dev);
 650         if (!ret)
 651                 ret = dm_i2c_write(dev, PMBUS_CMD_PAGE,
 652                                    &chan, 1);
 653 #endif
 654
 655         if (ret) {
 656                 printf("VID: failed to select VDD Page 0\n");
 657                 return ret;
 658         }
 659
 660         /* Read the output voltage using PMBus command READ_VOUT */
 661 #if !CONFIG_IS_ENABLED(DM_I2C)
 662         ret = i2c_read(I2C_SVDD_MONITOR_ADDR,
 663                        PMBUS_CMD_READ_VOUT, 1, (void *)&vcode, 2);
 664 #else
 665         dm_i2c_read(dev, PMBUS_CMD_READ_VOUT, (void *)&vcode, 2);
 666 #endif
 667         if (ret) {
 668                 printf("VID: failed to read the volatge\n");
 669                 return ret;
 670         }
 671
 672         return vcode;
 673 }
 674
 675 int set_serdes_volt(int svdd)
 676 {
 677         int ret, vdd_last;
 678         u8 buff[5] = {0x04, PWM_CHANNEL0, PMBUS_CMD_VOUT_COMMAND,
 679                         svdd & 0xFF, (svdd & 0xFF00) >> 8};
 680
 681         /* Write the desired voltage code to the SVDD regulator */
 682 #if !CONFIG_IS_ENABLED(DM_I2C)
 683         ret = i2c_write(I2C_SVDD_MONITOR_ADDR,
 684                         PMBUS_CMD_PAGE_PLUS_WRITE, 1, (void *)&buff, 5);
 685 #else
 686         struct udevice *dev;
 687
 688         ret = i2c_get_chip_for_busnum(0, I2C_SVDD_MONITOR_ADDR, 1, &dev);
 689         if (!ret)
 690                 ret = dm_i2c_write(dev, PMBUS_CMD_PAGE_PLUS_WRITE,
 691                                    (void *)&buff, 5);
 692 #endif
 693         if (ret) {
 694                 printf("VID: I2C failed to write to the volatge regulator\n");
 695                 return -1;
 696         }
 697
 698         /* Wait for the volatge to get to the desired value */
 699         do {
 700                 vdd_last = get_serdes_volt();
 701                 if (vdd_last < 0) {
 702                         printf("VID: Couldn't read sensor abort VID adjust\n");
 703                         return -1;
 704                 }
 705         } while (vdd_last != svdd);
 706
 707         return 1;
 708 }
 709 #else
 710 int get_serdes_volt(void)
 711 {
 712         return 0;
 713 }
 714
 715 int set_serdes_volt(int svdd)
 716 {
 717         int ret;
 718         u8 brdcfg4;
 719
 720         printf("SVDD changing of RDB\n");
 721
 722         /* Read the BRDCFG54 via CLPD */
 723 #if !CONFIG_IS_ENABLED(DM_I2C)
 724         ret = i2c_read(CONFIG_SYS_I2C_FPGA_ADDR,
 725                        QIXIS_BRDCFG4_OFFSET, 1, (void *)&brdcfg4, 1);
 726 #else
 727         struct udevice *dev;
 728
 729         ret = i2c_get_chip_for_busnum(0, CONFIG_SYS_I2C_FPGA_ADDR, 1, &dev);
 730         if (!ret)
 731                 ret = dm_i2c_read(dev, QIXIS_BRDCFG4_OFFSET,
 732                                   (void *)&brdcfg4, 1);
 733 #endif
 734
 735         if (ret) {
 736                 printf("VID: I2C failed to read the CPLD BRDCFG4\n");
 737                 return -1;
 738         }
 739
 740         brdcfg4 = brdcfg4 | 0x08;
 741
 742         /* Write to the BRDCFG4 */
 743 #if !CONFIG_IS_ENABLED(DM_I2C)
 744         ret = i2c_write(CONFIG_SYS_I2C_FPGA_ADDR,
 745                         QIXIS_BRDCFG4_OFFSET, 1, (void *)&brdcfg4, 1);
 746 #else
 747         ret = dm_i2c_write(dev, QIXIS_BRDCFG4_OFFSET,
 748                            (void *)&brdcfg4, 1);
 749 #endif
 750
 751         if (ret) {
 752                 debug("VID: I2C failed to set the SVDD CPLD BRDCFG4\n");
 753                 return -1;
 754         }
 755
 756         /* Wait for the volatge to get to the desired value */
 757         udelay(10000);
 758
 759         return 1;
 760 }
 761 #endif
 762
 763 /* this function disables the SERDES, changes the SVDD Voltage and enables it*/
 764 int board_adjust_vdd(int vdd)
 765 {
 766         int ret = 0;
 767
 768         debug("%s: vdd = %d\n", __func__, vdd);
 769
 770         /* Special settings to be performed when voltage is 900mV */
 771         if (vdd == 900) {
 772                 ret = setup_serdes_volt(vdd);
 773                 if (ret < 0) {
 774                         ret = -1;
 775                         goto exit;
 776                 }
 777         }
 778 exit:
 779         return ret;
 780 }
 781
 782 #if !defined(CONFIG_SPL_BUILD)
 783 int board_init(void)
 784 {
 785         init_final_memctl_regs();
 786 #if defined(CONFIG_TARGET_LS1088ARDB) && defined(CONFIG_FSL_MC_ENET)
 787         u32 __iomem *irq_ccsr = (u32 __iomem *)ISC_BASE;
 788 #endif
 789
 790         select_i2c_ch_pca9547(I2C_MUX_CH_DEFAULT);
 791         board_retimer_init();
 792
 793 #ifdef CONFIG_ENV_IS_NOWHERE
 794         gd->env_addr = (ulong)&default_environment[0];
 795 #endif
 796
 797 #if defined(CONFIG_TARGET_LS1088ARDB) && defined(CONFIG_FSL_MC_ENET)
 798         /* invert AQR105 IRQ pins polarity */
 799         out_le32(irq_ccsr + IRQCR_OFFSET / 4, AQR105_IRQ_MASK);
 800 #endif
 801
 802 #ifdef CONFIG_FSL_CAAM
 803         sec_init();
 804 #endif
 805 #ifdef CONFIG_FSL_LS_PPA
 806         ppa_init();
 807 #endif
 808
 809 #if !defined(CONFIG_SYS_EARLY_PCI_INIT) && defined(CONFIG_DM_ETH)
 810         pci_init();
 811 #endif
 812
 813         return 0;
 814 }
 815
 816 void detail_board_ddr_info(void)
 817 {
 818         puts("\nDDR    ");
 819         print_size(gd->bd->bi_dram[0].size + gd->bd->bi_dram[1].size, "");
 820         print_ddr_info(0);
 821 }
 822
 823 #ifdef CONFIG_FSL_MC_ENET
 824 void board_quiesce_devices(void)
 825 {
 826         fsl_mc_ldpaa_exit(gd->bd);
 827 }
 828
 829 void fdt_fixup_board_enet(void *fdt)
 830 {
 831         int offset;
 832
 833         offset = fdt_path_offset(fdt, "/fsl-mc");
 834
 835         if (offset < 0)
 836                 offset = fdt_path_offset(fdt, "/soc/fsl-mc");
 837
 838         if (offset < 0) {
 839                 printf("%s: ERROR: fsl-mc node not found in device tree (error %d)\n",
 840                        __func__, offset);
 841                 return;
 842         }
 843
 844         if (get_mc_boot_status() == 0 &&
 845             (is_lazy_dpl_addr_valid() || get_dpl_apply_status() == 0))
 846                 fdt_status_okay(fdt, offset);
 847         else
 848                 fdt_status_fail(fdt, offset);
 849 }
 850 #endif
 851
 852 #ifdef CONFIG_OF_BOARD_SETUP
 853 void fsl_fdt_fixup_flash(void *fdt)
 854 {
 855         int offset;
 856 #ifdef CONFIG_TFABOOT
 857         u32 __iomem *dcfg_ccsr = (u32 __iomem *)DCFG_BASE;
 858         u32 val;
 859 #endif
 860
 861 /*
 862  * IFC-NOR and QSPI are muxed on SoC.
 863  * So disable IFC node in dts if QSPI is enabled or
 864  * disable QSPI node in dts in case QSPI is not enabled.
 865  */
 866
 867 #ifdef CONFIG_TFABOOT
 868         enum boot_src src = get_boot_src();
 869         bool disable_ifc = false;
 870
 871         switch (src) {
 872         case BOOT_SOURCE_IFC_NOR:
 873                 disable_ifc = false;
 874                 break;
 875         case BOOT_SOURCE_QSPI_NOR:
 876                 disable_ifc = true;
 877                 break;
 878         default:
 879                 val = in_le32(dcfg_ccsr + DCFG_RCWSR15 / 4);
 880                 if (DCFG_RCWSR15_IFCGRPABASE_QSPI == (val & (u32)0x3))
 881                         disable_ifc = true;
 882                 break;
 883         }
 884
 885         if (disable_ifc) {
 886                 offset = fdt_path_offset(fdt, "/soc/ifc/nor");
 887
 888                 if (offset < 0)
 889                         offset = fdt_path_offset(fdt, "/ifc/nor");
 890         } else {
 891                 offset = fdt_path_offset(fdt, "/soc/quadspi");
 892
 893                 if (offset < 0)
 894                         offset = fdt_path_offset(fdt, "/quadspi");
 895         }
 896
 897 #else
 898 #ifdef CONFIG_FSL_QSPI
 899         offset = fdt_path_offset(fdt, "/soc/ifc/nor");
 900
 901         if (offset < 0)
 902                 offset = fdt_path_offset(fdt, "/ifc/nor");
 903 #else
 904         offset = fdt_path_offset(fdt, "/soc/quadspi");
 905
 906         if (offset < 0)
 907                 offset = fdt_path_offset(fdt, "/quadspi");
 908 #endif
 909 #endif
 910         if (offset < 0)
 911                 return;
 912
 913         fdt_status_disabled(fdt, offset);
 914 }
 915
 916 int ft_board_setup(void *blob, struct bd_info *bd)
 917 {
 918         int i;
 919         u16 mc_memory_bank = 0;
 920
 921         u64 *base;
 922         u64 *size;
 923         u64 mc_memory_base = 0;
 924         u64 mc_memory_size = 0;
 925         u16 total_memory_banks;
 926
 927         ft_cpu_setup(blob, bd);
 928
 929         fdt_fixup_mc_ddr(&mc_memory_base, &mc_memory_size);
 930
 931         if (mc_memory_base != 0)
 932                 mc_memory_bank++;
 933
 934         total_memory_banks = CONFIG_NR_DRAM_BANKS + mc_memory_bank;
 935
 936         base = calloc(total_memory_banks, sizeof(u64));
 937         size = calloc(total_memory_banks, sizeof(u64));
 938
 939         /* fixup DT for the two GPP DDR banks */
 940         for (i = 0; i < CONFIG_NR_DRAM_BANKS; i++) {
 941                 base[i] = gd->bd->bi_dram[i].start;
 942                 size[i] = gd->bd->bi_dram[i].size;
 943         }
 944
 945 #ifdef CONFIG_RESV_RAM
 946         /* reduce size if reserved memory is within this bank */
 947         if (gd->arch.resv_ram >= base[0] &&
 948             gd->arch.resv_ram < base[0] + size[0])
 949                 size[0] = gd->arch.resv_ram - base[0];
 950         else if (gd->arch.resv_ram >= base[1] &&
 951                  gd->arch.resv_ram < base[1] + size[1])
 952                 size[1] = gd->arch.resv_ram - base[1];
 953 #endif
 954
 955         if (mc_memory_base != 0) {
 956                 for (i = 0; i <= total_memory_banks; i++) {
 957                         if (base[i] == 0 && size[i] == 0) {
 958                                 base[i] = mc_memory_base;
 959                                 size[i] = mc_memory_size;
 960                                 break;
 961                         }
 962                 }
 963         }
 964
 965         fdt_fixup_memory_banks(blob, base, size, total_memory_banks);
 966
 967         fdt_fsl_mc_fixup_iommu_map_entry(blob);
 968
 969         fsl_fdt_fixup_flash(blob);
 970
 971 #ifdef CONFIG_FSL_MC_ENET
 972         fdt_fixup_board_enet(blob);
 973 #endif
 974
 975         fdt_fixup_icid(blob);
 976
 977         if (is_pb_board())
 978                 fixup_ls1088ardb_pb_banner(blob);
 979
 980         return 0;
 981 }
 982 #endif
 983 #endif /* defined(CONFIG_SPL_BUILD) */
 984
 985 #ifdef CONFIG_TFABOOT
 986 #ifdef CONFIG_MTD_NOR_FLASH
 987 int is_flash_available(void)
 988 {
 989         char *env_hwconfig = env_get("hwconfig");
 990         enum boot_src src = get_boot_src();
 991         int is_nor_flash_available = 1;
 992
 993         switch (src) {
 994         case BOOT_SOURCE_IFC_NOR:
 995                 is_nor_flash_available = 1;
 996                 break;
 997         case BOOT_SOURCE_QSPI_NOR:
 998                 is_nor_flash_available = 0;
 999                 break;
1000         /*
1001          * In Case of SD boot,if qspi is defined in env_hwconfig
1002          * disable nor flash probe.
1003          */
1004         default:
1005                 if (hwconfig_f("qspi", env_hwconfig))
1006                         is_nor_flash_available = 0;
1007                 break;
1008         }
1009         return is_nor_flash_available;
1010 }
1011 #endif
1012
1013 #ifdef CONFIG_ENV_IS_IN_SPI_FLASH
1014 void *env_sf_get_env_addr(void)
1015 {
1016         return (void *)(CONFIG_SYS_FSL_QSPI_BASE + CONFIG_ENV_OFFSET);
1017 }
1018 #endif
1019 #endif