1 // SPDX-License-Identifier: GPL-2.0+
3 * Copyright 2017-2018 NXP
17 #include <fdt_support.h>
18 #include <linux/delay.h>
19 #include <linux/libfdt.h>
20 #include <fsl-mc/fsl_mc.h>
21 #include <env_internal.h>
22 #include <asm/arch-fsl-layerscape/soc.h>
23 #include <asm/arch/ppa.h>
25 #include <asm/arch/fsl_serdes.h>
26 #include <asm/arch/soc.h>
27 #include <asm/arch-fsl-layerscape/fsl_icid.h>
29 #include "../common/qixis.h"
30 #include "ls1088a_qixis.h"
31 #include "../common/vid.h"
32 #include <fsl_immap.h>
34 DECLARE_GLOBAL_DATA_PTR;
36 #ifdef CONFIG_TARGET_LS1088AQDS
38 struct ifc_regs ifc_cfg_ifc_nor_boot[CONFIG_SYS_FSL_IFC_BANK_COUNT] = {
41 CONFIG_SYS_NOR0_CSPR_EARLY,
42 CONFIG_SYS_NOR0_CSPR_EXT,
57 CONFIG_SYS_NOR1_CSPR_EARLY,
58 CONFIG_SYS_NOR0_CSPR_EXT,
59 CONFIG_SYS_NOR_AMASK_EARLY,
74 CONFIG_SYS_NAND_CSPR_EXT,
75 CONFIG_SYS_NAND_AMASK,
78 CONFIG_SYS_NAND_FTIM0,
79 CONFIG_SYS_NAND_FTIM1,
80 CONFIG_SYS_NAND_FTIM2,
87 CONFIG_SYS_FPGA_CSPR_EXT,
102 struct ifc_regs ifc_cfg_qspi_nor_boot[CONFIG_SYS_FSL_IFC_BANK_COUNT] = {
105 CONFIG_SYS_NAND_CSPR,
106 CONFIG_SYS_NAND_CSPR_EXT,
107 CONFIG_SYS_NAND_AMASK,
108 CONFIG_SYS_NAND_CSOR,
110 CONFIG_SYS_NAND_FTIM0,
111 CONFIG_SYS_NAND_FTIM1,
112 CONFIG_SYS_NAND_FTIM2,
113 CONFIG_SYS_NAND_FTIM3
121 CONFIG_SYS_FPGA_CSPR,
122 CONFIG_SYS_FPGA_CSPR_EXT,
124 CONFIG_SYS_FPGA_CSOR,
137 void ifc_cfg_boot_info(struct ifc_regs_info *regs_info)
139 enum boot_src src = get_boot_src();
141 if (src == BOOT_SOURCE_QSPI_NOR)
142 regs_info->regs = ifc_cfg_qspi_nor_boot;
144 regs_info->regs = ifc_cfg_ifc_nor_boot;
146 regs_info->cs_size = CONFIG_SYS_FSL_IFC_BANK_COUNT;
148 #endif /* CONFIG_TFABOOT */
149 #endif /* CONFIG_TARGET_LS1088AQDS */
151 int board_early_init_f(void)
153 #if defined(CONFIG_SYS_I2C_EARLY_INIT) && defined(CONFIG_TARGET_LS1088AQDS)
156 fsl_lsch3_early_init_f();
160 #ifdef CONFIG_FSL_QIXIS
161 unsigned long long get_qixis_addr(void)
163 unsigned long long addr;
165 if (gd->flags & GD_FLG_RELOC)
166 addr = QIXIS_BASE_PHYS;
168 addr = QIXIS_BASE_PHYS_EARLY;
171 * IFC address under 256MB is mapped to 0x30000000, any address above
172 * is mapped to 0x5_10000000 up to 4GB.
174 addr = addr > 0x10000000 ? addr + 0x500000000ULL : addr + 0x30000000;
180 #if defined(CONFIG_VID)
181 int init_func_vid(void)
183 if (adjust_vdd(0) < 0)
184 printf("core voltage not adjusted\n");
190 int is_pb_board(void)
194 board_id = QIXIS_READ(id);
195 if (board_id == LS1088ARDB_PB_BOARD)
201 int fixup_ls1088ardb_pb_banner(void *fdt)
203 fdt_setprop_string(fdt, 0, "model", "LS1088ARDB-PB Board");
208 #if !defined(CONFIG_SPL_BUILD)
211 #ifdef CONFIG_TFABOOT
212 enum boot_src src = get_boot_src();
216 static const char *const freq[] = {"100", "125", "156.25",
217 "100 separate SSCG"};
220 #ifdef CONFIG_TARGET_LS1088AQDS
221 printf("Board: LS1088A-QDS, ");
224 printf("Board: LS1088ARDB-PB, ");
226 printf("Board: LS1088A-RDB, ");
229 sw = QIXIS_READ(arch);
230 printf("Board Arch: V%d, ", sw >> 4);
232 #ifdef CONFIG_TARGET_LS1088AQDS
233 printf("Board version: %c, boot from ", (sw & 0xf) + 'A' - 1);
235 printf("Board version: %c, boot from ", (sw & 0xf) + 'A');
238 memset((u8 *)buf, 0x00, ARRAY_SIZE(buf));
240 sw = QIXIS_READ(brdcfg[0]);
241 sw = (sw & QIXIS_LBMAP_MASK) >> QIXIS_LBMAP_SHIFT;
243 #ifdef CONFIG_TFABOOT
244 if (src == BOOT_SOURCE_SD_MMC)
247 #ifdef CONFIG_SD_BOOT
250 #endif /* CONFIG_TFABOOT */
252 #ifdef CONFIG_TARGET_LS1088AQDS
261 printf("vBank: %d\n", sw);
274 sw = QIXIS_READ(brdcfg[0]);
275 sw = (sw & QIXIS_QMAP_MASK) >> QIXIS_QMAP_SHIFT;
276 if (sw == 0 || sw == 4)
285 printf("invalid setting of SW%u\n", QIXIS_LBMAP_SWITCH);
289 #ifdef CONFIG_TARGET_LS1088AQDS
290 printf("FPGA: v%d (%s), build %d",
291 (int)QIXIS_READ(scver), qixis_read_tag(buf),
292 (int)qixis_read_minor());
293 /* the timestamp string contains "\n" at the end */
294 printf(" on %s", qixis_read_time(buf));
296 printf("CPLD: v%d.%d\n", QIXIS_READ(scver), QIXIS_READ(tagdata));
300 * Display the actual SERDES reference clocks as configured by the
301 * dip switches on the board. Note that the SWx registers could
302 * technically be set to force the reference clocks to match the
303 * values that the SERDES expects (or vice versa). For now, however,
304 * we just display both values and hope the user notices when they
307 puts("SERDES1 Reference : ");
308 sw = QIXIS_READ(brdcfg[2]);
309 clock = (sw >> 6) & 3;
310 printf("Clock1 = %sMHz ", freq[clock]);
311 clock = (sw >> 4) & 3;
312 printf("Clock2 = %sMHz", freq[clock]);
314 puts("\nSERDES2 Reference : ");
315 clock = (sw >> 2) & 3;
316 printf("Clock1 = %sMHz ", freq[clock]);
317 clock = (sw >> 0) & 3;
318 printf("Clock2 = %sMHz\n", freq[clock]);
324 bool if_board_diff_clk(void)
326 #ifdef CONFIG_TARGET_LS1088AQDS
327 u8 diff_conf = QIXIS_READ(brdcfg[11]);
328 return diff_conf & 0x40;
330 u8 diff_conf = QIXIS_READ(dutcfg[11]);
331 return diff_conf & 0x80;
335 unsigned long get_board_sys_clk(void)
337 u8 sysclk_conf = QIXIS_READ(brdcfg[1]);
339 switch (sysclk_conf & 0x0f) {
340 case QIXIS_SYSCLK_83:
342 case QIXIS_SYSCLK_100:
344 case QIXIS_SYSCLK_125:
346 case QIXIS_SYSCLK_133:
348 case QIXIS_SYSCLK_150:
350 case QIXIS_SYSCLK_160:
352 case QIXIS_SYSCLK_166:
359 unsigned long get_board_ddr_clk(void)
361 u8 ddrclk_conf = QIXIS_READ(brdcfg[1]);
363 if (if_board_diff_clk())
364 return get_board_sys_clk();
365 switch ((ddrclk_conf & 0x30) >> 4) {
366 case QIXIS_DDRCLK_100:
368 case QIXIS_DDRCLK_125:
370 case QIXIS_DDRCLK_133:
377 int select_i2c_ch_pca9547(u8 ch)
381 #ifndef CONFIG_DM_I2C
382 ret = i2c_write(I2C_MUX_PCA_ADDR_PRI, 0, 1, &ch, 1);
386 ret = i2c_get_chip_for_busnum(0, I2C_MUX_PCA_ADDR_PRI, 1, &dev);
388 ret = dm_i2c_write(dev, 0, &ch, 1);
391 puts("PCA: failed to select proper channel\n");
398 #if !defined(CONFIG_SPL_BUILD)
399 void board_retimer_init(void)
403 /* Retimer is connected to I2C1_CH5 */
404 select_i2c_ch_pca9547(I2C_MUX_CH5);
406 /* Access to Control/Shared register */
408 #ifndef CONFIG_DM_I2C
409 i2c_write(I2C_RETIMER_ADDR, 0xff, 1, ®, 1);
413 i2c_get_chip_for_busnum(0, I2C_RETIMER_ADDR, 1, &dev);
414 dm_i2c_write(dev, 0xff, ®, 1);
417 /* Read device revision and ID */
418 #ifndef CONFIG_DM_I2C
419 i2c_read(I2C_RETIMER_ADDR, 1, 1, ®, 1);
421 dm_i2c_read(dev, 1, ®, 1);
423 debug("Retimer version id = 0x%x\n", reg);
425 /* Enable Broadcast. All writes target all channel register sets */
427 #ifndef CONFIG_DM_I2C
428 i2c_write(I2C_RETIMER_ADDR, 0xff, 1, ®, 1);
430 dm_i2c_write(dev, 0xff, ®, 1);
433 /* Reset Channel Registers */
434 #ifndef CONFIG_DM_I2C
435 i2c_read(I2C_RETIMER_ADDR, 0, 1, ®, 1);
437 dm_i2c_read(dev, 0, ®, 1);
440 #ifndef CONFIG_DM_I2C
441 i2c_write(I2C_RETIMER_ADDR, 0, 1, ®, 1);
443 dm_i2c_write(dev, 0, ®, 1);
446 /* Set data rate as 10.3125 Gbps */
448 #ifndef CONFIG_DM_I2C
449 i2c_write(I2C_RETIMER_ADDR, 0x60, 1, ®, 1);
451 dm_i2c_write(dev, 0x60, ®, 1);
454 #ifndef CONFIG_DM_I2C
455 i2c_write(I2C_RETIMER_ADDR, 0x61, 1, ®, 1);
457 dm_i2c_write(dev, 0x61, ®, 1);
460 #ifndef CONFIG_DM_I2C
461 i2c_write(I2C_RETIMER_ADDR, 0x62, 1, ®, 1);
463 dm_i2c_write(dev, 0x62, ®, 1);
466 #ifndef CONFIG_DM_I2C
467 i2c_write(I2C_RETIMER_ADDR, 0x63, 1, ®, 1);
469 dm_i2c_write(dev, 0x63, ®, 1);
472 #ifndef CONFIG_DM_I2C
473 i2c_write(I2C_RETIMER_ADDR, 0x64, 1, ®, 1);
475 dm_i2c_write(dev, 0x64, ®, 1);
478 /* Select VCO Divider to full rate (000) */
479 #ifndef CONFIG_DM_I2C
480 i2c_read(I2C_RETIMER_ADDR, 0x2F, 1, ®, 1);
482 dm_i2c_read(dev, 0x2F, ®, 1);
486 #ifndef CONFIG_DM_I2C
487 i2c_write(I2C_RETIMER_ADDR, 0x2F, 1, ®, 1);
489 dm_i2c_write(dev, 0x2F, ®, 1);
492 #ifdef CONFIG_TARGET_LS1088AQDS
493 /* Retimer is connected to I2C1_CH5 */
494 select_i2c_ch_pca9547(I2C_MUX_CH5);
496 /* Access to Control/Shared register */
498 #ifndef CONFIG_DM_I2C
499 i2c_write(I2C_RETIMER_ADDR2, 0xff, 1, ®, 1);
501 i2c_get_chip_for_busnum(0, I2C_RETIMER_ADDR2, 1, &dev);
502 dm_i2c_write(dev, 0xff, ®, 1);
505 /* Read device revision and ID */
506 #ifndef CONFIG_DM_I2C
507 i2c_read(I2C_RETIMER_ADDR2, 1, 1, ®, 1);
509 dm_i2c_read(dev, 1, ®, 1);
511 debug("Retimer version id = 0x%x\n", reg);
513 /* Enable Broadcast. All writes target all channel register sets */
515 #ifndef CONFIG_DM_I2C
516 i2c_write(I2C_RETIMER_ADDR2, 0xff, 1, ®, 1);
518 dm_i2c_write(dev, 0xff, ®, 1);
521 /* Reset Channel Registers */
522 #ifndef CONFIG_DM_I2C
523 i2c_read(I2C_RETIMER_ADDR2, 0, 1, ®, 1);
525 dm_i2c_read(dev, 0, ®, 1);
528 #ifndef CONFIG_DM_I2C
529 i2c_write(I2C_RETIMER_ADDR2, 0, 1, ®, 1);
531 dm_i2c_write(dev, 0, ®, 1);
534 /* Set data rate as 10.3125 Gbps */
536 #ifndef CONFIG_DM_I2C
537 i2c_write(I2C_RETIMER_ADDR2, 0x60, 1, ®, 1);
539 dm_i2c_write(dev, 0x60, ®, 1);
542 #ifndef CONFIG_DM_I2C
543 i2c_write(I2C_RETIMER_ADDR2, 0x61, 1, ®, 1);
545 dm_i2c_write(dev, 0x61, ®, 1);
548 #ifndef CONFIG_DM_I2C
549 i2c_write(I2C_RETIMER_ADDR2, 0x62, 1, ®, 1);
551 dm_i2c_write(dev, 0x62, ®, 1);
554 #ifndef CONFIG_DM_I2C
555 i2c_write(I2C_RETIMER_ADDR2, 0x63, 1, ®, 1);
557 dm_i2c_write(dev, 0x63, ®, 1);
560 #ifndef CONFIG_DM_I2C
561 i2c_write(I2C_RETIMER_ADDR2, 0x64, 1, ®, 1);
563 dm_i2c_write(dev, 0x64, ®, 1);
566 /* Select VCO Divider to full rate (000) */
567 #ifndef CONFIG_DM_I2C
568 i2c_read(I2C_RETIMER_ADDR2, 0x2F, 1, ®, 1);
570 dm_i2c_read(dev, 0x2F, ®, 1);
574 #ifndef CONFIG_DM_I2C
575 i2c_write(I2C_RETIMER_ADDR2, 0x2F, 1, ®, 1);
577 dm_i2c_write(dev, 0x2F, ®, 1);
581 /*return the default channel*/
582 select_i2c_ch_pca9547(I2C_MUX_CH_DEFAULT);
585 #ifdef CONFIG_MISC_INIT_R
586 int misc_init_r(void)
588 #ifdef CONFIG_TARGET_LS1088ARDB
591 if (hwconfig("esdhc-force-sd")) {
592 brdcfg5 = QIXIS_READ(brdcfg[5]);
593 brdcfg5 &= ~BRDCFG5_SPISDHC_MASK;
594 brdcfg5 |= BRDCFG5_FORCE_SD;
595 QIXIS_WRITE(brdcfg[5], brdcfg5);
599 #ifdef CONFIG_TARGET_LS1088AQDS
602 if (hwconfig("dspi-on-board")) {
603 brdcfg4 = QIXIS_READ(brdcfg[4]);
604 brdcfg4 &= ~BRDCFG4_USBOSC_MASK;
605 brdcfg4 |= BRDCFG4_SPI;
606 QIXIS_WRITE(brdcfg[4], brdcfg4);
608 brdcfg5 = QIXIS_READ(brdcfg[5]);
609 brdcfg5 &= ~BRDCFG5_SPR_MASK;
610 brdcfg5 |= BRDCFG5_SPI_ON_BOARD;
611 QIXIS_WRITE(brdcfg[5], brdcfg5);
612 } else if (hwconfig("dspi-off-board")) {
613 brdcfg4 = QIXIS_READ(brdcfg[4]);
614 brdcfg4 &= ~BRDCFG4_USBOSC_MASK;
615 brdcfg4 |= BRDCFG4_SPI;
616 QIXIS_WRITE(brdcfg[4], brdcfg4);
618 brdcfg5 = QIXIS_READ(brdcfg[5]);
619 brdcfg5 &= ~BRDCFG5_SPR_MASK;
620 brdcfg5 |= BRDCFG5_SPI_OFF_BOARD;
621 QIXIS_WRITE(brdcfg[5], brdcfg5);
629 int i2c_multiplexer_select_vid_channel(u8 channel)
631 return select_i2c_ch_pca9547(channel);
634 #ifdef CONFIG_TARGET_LS1088AQDS
635 /* read the current value(SVDD) of the LTM Regulator Voltage */
636 int get_serdes_volt(void)
639 u8 chan = PWM_CHANNEL0;
641 /* Select the PAGE 0 using PMBus commands PAGE for VDD */
642 #ifndef CONFIG_DM_I2C
643 ret = i2c_write(I2C_SVDD_MONITOR_ADDR,
644 PMBUS_CMD_PAGE, 1, &chan, 1);
648 ret = i2c_get_chip_for_busnum(0, I2C_SVDD_MONITOR_ADDR, 1, &dev);
650 ret = dm_i2c_write(dev, PMBUS_CMD_PAGE,
655 printf("VID: failed to select VDD Page 0\n");
659 /* Read the output voltage using PMBus command READ_VOUT */
660 #ifndef CONFIG_DM_I2C
661 ret = i2c_read(I2C_SVDD_MONITOR_ADDR,
662 PMBUS_CMD_READ_VOUT, 1, (void *)&vcode, 2);
664 dm_i2c_read(dev, PMBUS_CMD_READ_VOUT, (void *)&vcode, 2);
667 printf("VID: failed to read the volatge\n");
674 int set_serdes_volt(int svdd)
677 u8 buff[5] = {0x04, PWM_CHANNEL0, PMBUS_CMD_VOUT_COMMAND,
678 svdd & 0xFF, (svdd & 0xFF00) >> 8};
680 /* Write the desired voltage code to the SVDD regulator */
681 #ifndef CONFIG_DM_I2C
682 ret = i2c_write(I2C_SVDD_MONITOR_ADDR,
683 PMBUS_CMD_PAGE_PLUS_WRITE, 1, (void *)&buff, 5);
687 ret = i2c_get_chip_for_busnum(0, I2C_SVDD_MONITOR_ADDR, 1, &dev);
689 ret = dm_i2c_write(dev, PMBUS_CMD_PAGE_PLUS_WRITE,
693 printf("VID: I2C failed to write to the volatge regulator\n");
697 /* Wait for the volatge to get to the desired value */
699 vdd_last = get_serdes_volt();
701 printf("VID: Couldn't read sensor abort VID adjust\n");
704 } while (vdd_last != svdd);
709 int get_serdes_volt(void)
714 int set_serdes_volt(int svdd)
719 printf("SVDD changing of RDB\n");
721 /* Read the BRDCFG54 via CLPD */
722 #ifndef CONFIG_DM_I2C
723 ret = i2c_read(CONFIG_SYS_I2C_FPGA_ADDR,
724 QIXIS_BRDCFG4_OFFSET, 1, (void *)&brdcfg4, 1);
728 ret = i2c_get_chip_for_busnum(0, CONFIG_SYS_I2C_FPGA_ADDR, 1, &dev);
730 ret = dm_i2c_read(dev, QIXIS_BRDCFG4_OFFSET,
731 (void *)&brdcfg4, 1);
735 printf("VID: I2C failed to read the CPLD BRDCFG4\n");
739 brdcfg4 = brdcfg4 | 0x08;
741 /* Write to the BRDCFG4 */
742 #ifndef CONFIG_DM_I2C
743 ret = i2c_write(CONFIG_SYS_I2C_FPGA_ADDR,
744 QIXIS_BRDCFG4_OFFSET, 1, (void *)&brdcfg4, 1);
746 ret = dm_i2c_write(dev, QIXIS_BRDCFG4_OFFSET,
747 (void *)&brdcfg4, 1);
751 debug("VID: I2C failed to set the SVDD CPLD BRDCFG4\n");
755 /* Wait for the volatge to get to the desired value */
762 /* this function disables the SERDES, changes the SVDD Voltage and enables it*/
763 int board_adjust_vdd(int vdd)
767 debug("%s: vdd = %d\n", __func__, vdd);
769 /* Special settings to be performed when voltage is 900mV */
771 ret = setup_serdes_volt(vdd);
781 #if !defined(CONFIG_SPL_BUILD)
784 init_final_memctl_regs();
785 #if defined(CONFIG_TARGET_LS1088ARDB) && defined(CONFIG_FSL_MC_ENET)
786 u32 __iomem *irq_ccsr = (u32 __iomem *)ISC_BASE;
789 select_i2c_ch_pca9547(I2C_MUX_CH_DEFAULT);
790 board_retimer_init();
792 #ifdef CONFIG_ENV_IS_NOWHERE
793 gd->env_addr = (ulong)&default_environment[0];
796 #if defined(CONFIG_TARGET_LS1088ARDB) && defined(CONFIG_FSL_MC_ENET)
797 /* invert AQR105 IRQ pins polarity */
798 out_le32(irq_ccsr + IRQCR_OFFSET / 4, AQR105_IRQ_MASK);
801 #ifdef CONFIG_FSL_CAAM
804 #ifdef CONFIG_FSL_LS_PPA
808 #if !defined(CONFIG_SYS_EARLY_PCI_INIT) && defined(CONFIG_DM_ETH)
815 void detail_board_ddr_info(void)
818 print_size(gd->bd->bi_dram[0].size + gd->bd->bi_dram[1].size, "");
822 #ifdef CONFIG_FSL_MC_ENET
823 void board_quiesce_devices(void)
825 fsl_mc_ldpaa_exit(gd->bd);
828 void fdt_fixup_board_enet(void *fdt)
832 offset = fdt_path_offset(fdt, "/fsl-mc");
835 offset = fdt_path_offset(fdt, "/soc/fsl-mc");
838 printf("%s: ERROR: fsl-mc node not found in device tree (error %d)\n",
843 if (get_mc_boot_status() == 0 &&
844 (is_lazy_dpl_addr_valid() || get_dpl_apply_status() == 0))
845 fdt_status_okay(fdt, offset);
847 fdt_status_fail(fdt, offset);
851 #ifdef CONFIG_OF_BOARD_SETUP
852 void fsl_fdt_fixup_flash(void *fdt)
855 #ifdef CONFIG_TFABOOT
856 u32 __iomem *dcfg_ccsr = (u32 __iomem *)DCFG_BASE;
861 * IFC-NOR and QSPI are muxed on SoC.
862 * So disable IFC node in dts if QSPI is enabled or
863 * disable QSPI node in dts in case QSPI is not enabled.
866 #ifdef CONFIG_TFABOOT
867 enum boot_src src = get_boot_src();
868 bool disable_ifc = false;
871 case BOOT_SOURCE_IFC_NOR:
874 case BOOT_SOURCE_QSPI_NOR:
878 val = in_le32(dcfg_ccsr + DCFG_RCWSR15 / 4);
879 if (DCFG_RCWSR15_IFCGRPABASE_QSPI == (val & (u32)0x3))
885 offset = fdt_path_offset(fdt, "/soc/ifc/nor");
888 offset = fdt_path_offset(fdt, "/ifc/nor");
890 offset = fdt_path_offset(fdt, "/soc/quadspi");
893 offset = fdt_path_offset(fdt, "/quadspi");
897 #ifdef CONFIG_FSL_QSPI
898 offset = fdt_path_offset(fdt, "/soc/ifc/nor");
901 offset = fdt_path_offset(fdt, "/ifc/nor");
903 offset = fdt_path_offset(fdt, "/soc/quadspi");
906 offset = fdt_path_offset(fdt, "/quadspi");
912 fdt_status_disabled(fdt, offset);
915 int ft_board_setup(void *blob, struct bd_info *bd)
918 u16 mc_memory_bank = 0;
922 u64 mc_memory_base = 0;
923 u64 mc_memory_size = 0;
924 u16 total_memory_banks;
926 ft_cpu_setup(blob, bd);
928 fdt_fixup_mc_ddr(&mc_memory_base, &mc_memory_size);
930 if (mc_memory_base != 0)
933 total_memory_banks = CONFIG_NR_DRAM_BANKS + mc_memory_bank;
935 base = calloc(total_memory_banks, sizeof(u64));
936 size = calloc(total_memory_banks, sizeof(u64));
938 /* fixup DT for the two GPP DDR banks */
939 for (i = 0; i < CONFIG_NR_DRAM_BANKS; i++) {
940 base[i] = gd->bd->bi_dram[i].start;
941 size[i] = gd->bd->bi_dram[i].size;
944 #ifdef CONFIG_RESV_RAM
945 /* reduce size if reserved memory is within this bank */
946 if (gd->arch.resv_ram >= base[0] &&
947 gd->arch.resv_ram < base[0] + size[0])
948 size[0] = gd->arch.resv_ram - base[0];
949 else if (gd->arch.resv_ram >= base[1] &&
950 gd->arch.resv_ram < base[1] + size[1])
951 size[1] = gd->arch.resv_ram - base[1];
954 if (mc_memory_base != 0) {
955 for (i = 0; i <= total_memory_banks; i++) {
956 if (base[i] == 0 && size[i] == 0) {
957 base[i] = mc_memory_base;
958 size[i] = mc_memory_size;
964 fdt_fixup_memory_banks(blob, base, size, total_memory_banks);
966 fdt_fsl_mc_fixup_iommu_map_entry(blob);
968 fsl_fdt_fixup_flash(blob);
970 #ifdef CONFIG_FSL_MC_ENET
971 fdt_fixup_board_enet(blob);
974 fdt_fixup_icid(blob);
977 fixup_ls1088ardb_pb_banner(blob);
982 #endif /* defined(CONFIG_SPL_BUILD) */
984 #ifdef CONFIG_TFABOOT
985 #ifdef CONFIG_MTD_NOR_FLASH
986 int is_flash_available(void)
988 char *env_hwconfig = env_get("hwconfig");
989 enum boot_src src = get_boot_src();
990 int is_nor_flash_available = 1;
993 case BOOT_SOURCE_IFC_NOR:
994 is_nor_flash_available = 1;
996 case BOOT_SOURCE_QSPI_NOR:
997 is_nor_flash_available = 0;
1000 * In Case of SD boot,if qspi is defined in env_hwconfig
1001 * disable nor flash probe.
1004 if (hwconfig_f("qspi", env_hwconfig))
1005 is_nor_flash_available = 0;
1008 return is_nor_flash_available;
1012 #ifdef CONFIG_ENV_IS_IN_SPI_FLASH
1013 void *env_sf_get_env_addr(void)
1015 return (void *)(CONFIG_SYS_FSL_QSPI_BASE + CONFIG_ENV_OFFSET);