board/freescale/ls1088a/ls1088a.c

   1 // SPDX-License-Identifier: GPL-2.0+
   2 /*
   3  * Copyright 2017-2018 NXP
   4  */
   5 #include <common.h>
   6 #include <env.h>
   7 #include <i2c.h>
   8 #include <init.h>
   9 #include <log.h>
  10 #include <malloc.h>
  11 #include <errno.h>
  12 #include <netdev.h>
  13 #include <fsl_ifc.h>
  14 #include <fsl_ddr.h>
  15 #include <fsl_sec.h>
  16 #include <asm/global_data.h>
  17 #include <asm/io.h>
  18 #include <fdt_support.h>
  19 #include <linux/delay.h>
  20 #include <linux/libfdt.h>
  21 #include <fsl-mc/fsl_mc.h>
  22 #include <env_internal.h>
  23 #include <asm/arch-fsl-layerscape/soc.h>
  24 #include <asm/arch/ppa.h>
  25 #include <hwconfig.h>
  26 #include <asm/arch/fsl_serdes.h>
  27 #include <asm/arch/soc.h>
  28 #include <asm/arch-fsl-layerscape/fsl_icid.h>
  29 #include "../common/i2c_mux.h"
  30
  31 #include "../common/qixis.h"
  32 #include "ls1088a_qixis.h"
  33 #include "../common/vid.h"
  34 #include <fsl_immap.h>
  35
  36 DECLARE_GLOBAL_DATA_PTR;
  37
  38 #ifdef CONFIG_TARGET_LS1088AQDS
  39 #ifdef CONFIG_TFABOOT
  40 struct ifc_regs ifc_cfg_ifc_nor_boot[CONFIG_SYS_FSL_IFC_BANK_COUNT] = {
  41         {
  42                 "nor0",
  43                 CONFIG_SYS_NOR0_CSPR_EARLY,
  44                 CONFIG_SYS_NOR0_CSPR_EXT,
  45                 CONFIG_SYS_NOR_AMASK,
  46                 CONFIG_SYS_NOR_CSOR,
  47                 {
  48                         CONFIG_SYS_NOR_FTIM0,
  49                         CONFIG_SYS_NOR_FTIM1,
  50                         CONFIG_SYS_NOR_FTIM2,
  51                         CONFIG_SYS_NOR_FTIM3
  52                 },
  53                 0,
  54                 CONFIG_SYS_NOR0_CSPR,
  55                 0,
  56         },
  57         {
  58                 "nor1",
  59                 CONFIG_SYS_NOR1_CSPR_EARLY,
  60                 CONFIG_SYS_NOR0_CSPR_EXT,
  61                 CONFIG_SYS_NOR_AMASK_EARLY,
  62                 CONFIG_SYS_NOR_CSOR,
  63                 {
  64                         CONFIG_SYS_NOR_FTIM0,
  65                         CONFIG_SYS_NOR_FTIM1,
  66                         CONFIG_SYS_NOR_FTIM2,
  67                         CONFIG_SYS_NOR_FTIM3
  68                 },
  69                 0,
  70                 CONFIG_SYS_NOR1_CSPR,
  71                 CONFIG_SYS_NOR_AMASK,
  72         },
  73         {
  74                 "nand",
  75                 CONFIG_SYS_NAND_CSPR,
  76                 CONFIG_SYS_NAND_CSPR_EXT,
  77                 CONFIG_SYS_NAND_AMASK,
  78                 CONFIG_SYS_NAND_CSOR,
  79                 {
  80                         CONFIG_SYS_NAND_FTIM0,
  81                         CONFIG_SYS_NAND_FTIM1,
  82                         CONFIG_SYS_NAND_FTIM2,
  83                         CONFIG_SYS_NAND_FTIM3
  84                 },
  85         },
  86         {
  87                 "fpga",
  88                 CONFIG_SYS_FPGA_CSPR,
  89                 CONFIG_SYS_FPGA_CSPR_EXT,
  90                 SYS_FPGA_AMASK,
  91                 CONFIG_SYS_FPGA_CSOR,
  92                 {
  93                         SYS_FPGA_CS_FTIM0,
  94                         SYS_FPGA_CS_FTIM1,
  95                         SYS_FPGA_CS_FTIM2,
  96                         SYS_FPGA_CS_FTIM3
  97                 },
  98                 0,
  99                 SYS_FPGA_CSPR_FINAL,
 100                 0,
 101         }
 102 };
 103
 104 struct ifc_regs ifc_cfg_qspi_nor_boot[CONFIG_SYS_FSL_IFC_BANK_COUNT] = {
 105         {
 106                 "nand",
 107                 CONFIG_SYS_NAND_CSPR,
 108                 CONFIG_SYS_NAND_CSPR_EXT,
 109                 CONFIG_SYS_NAND_AMASK,
 110                 CONFIG_SYS_NAND_CSOR,
 111                 {
 112                         CONFIG_SYS_NAND_FTIM0,
 113                         CONFIG_SYS_NAND_FTIM1,
 114                         CONFIG_SYS_NAND_FTIM2,
 115                         CONFIG_SYS_NAND_FTIM3
 116                 },
 117         },
 118         {
 119                 "reserved",
 120         },
 121         {
 122                 "fpga",
 123                 CONFIG_SYS_FPGA_CSPR,
 124                 CONFIG_SYS_FPGA_CSPR_EXT,
 125                 SYS_FPGA_AMASK,
 126                 CONFIG_SYS_FPGA_CSOR,
 127                 {
 128                         SYS_FPGA_CS_FTIM0,
 129                         SYS_FPGA_CS_FTIM1,
 130                         SYS_FPGA_CS_FTIM2,
 131                         SYS_FPGA_CS_FTIM3
 132                 },
 133                 0,
 134                 SYS_FPGA_CSPR_FINAL,
 135                 0,
 136         }
 137 };
 138
 139 void ifc_cfg_boot_info(struct ifc_regs_info *regs_info)
 140 {
 141         enum boot_src src = get_boot_src();
 142
 143         if (src == BOOT_SOURCE_QSPI_NOR)
 144                 regs_info->regs = ifc_cfg_qspi_nor_boot;
 145         else
 146                 regs_info->regs = ifc_cfg_ifc_nor_boot;
 147
 148         regs_info->cs_size = CONFIG_SYS_FSL_IFC_BANK_COUNT;
 149 }
 150 #endif /* CONFIG_TFABOOT */
 151 #endif /* CONFIG_TARGET_LS1088AQDS */
 152
 153 int board_early_init_f(void)
 154 {
 155 #if defined(CONFIG_SYS_I2C_EARLY_INIT) && defined(CONFIG_TARGET_LS1088AQDS)
 156         i2c_early_init_f();
 157 #endif
 158         fsl_lsch3_early_init_f();
 159         return 0;
 160 }
 161
 162 #ifdef CONFIG_FSL_QIXIS
 163 unsigned long long get_qixis_addr(void)
 164 {
 165         unsigned long long addr;
 166
 167         if (gd->flags & GD_FLG_RELOC)
 168                 addr = QIXIS_BASE_PHYS;
 169         else
 170                 addr = QIXIS_BASE_PHYS_EARLY;
 171
 172         /*
 173          * IFC address under 256MB is mapped to 0x30000000, any address above
 174          * is mapped to 0x5_10000000 up to 4GB.
 175          */
 176         addr = addr  > 0x10000000 ? addr + 0x500000000ULL : addr + 0x30000000;
 177
 178         return addr;
 179 }
 180 #endif
 181
 182 #if defined(CONFIG_VID)
 183 int init_func_vid(void)
 184 {
 185         if (adjust_vdd(0) < 0)
 186                 printf("core voltage not adjusted\n");
 187
 188         return 0;
 189 }
 190
 191 u16 soc_get_fuse_vid(int vid_index)
 192 {
 193         static const u16 vdd[32] = {
 194                 10250,
 195                 9875,
 196                 9750,
 197                 0,      /* reserved */
 198                 0,      /* reserved */
 199                 0,      /* reserved */
 200                 0,      /* reserved */
 201                 0,      /* reserved */
 202                 9000,
 203                 0,      /* reserved */
 204                 0,      /* reserved */
 205                 0,      /* reserved */
 206                 0,      /* reserved */
 207                 0,      /* reserved */
 208                 0,      /* reserved */
 209                 0,      /* reserved */
 210                 10000,  /* 1.0000V */
 211                 10125,
 212                 10250,
 213                 0,      /* reserved */
 214                 0,      /* reserved */
 215                 0,      /* reserved */
 216                 0,      /* reserved */
 217                 0,      /* reserved */
 218                 0,      /* reserved */
 219                 0,      /* reserved */
 220                 0,      /* reserved */
 221                 0,      /* reserved */
 222                 0,      /* reserved */
 223                 0,      /* reserved */
 224                 0,      /* reserved */
 225                 0,      /* reserved */
 226         };
 227
 228         return vdd[vid_index];
 229 };
 230 #endif
 231
 232 int is_pb_board(void)
 233 {
 234         u8 board_id;
 235
 236         board_id = QIXIS_READ(id);
 237         if (board_id == LS1088ARDB_PB_BOARD)
 238                 return 1;
 239         else
 240                 return 0;
 241 }
 242
 243 int fixup_ls1088ardb_pb_banner(void *fdt)
 244 {
 245         fdt_setprop_string(fdt, 0, "model", "LS1088ARDB-PB Board");
 246
 247         return 0;
 248 }
 249
 250 #if !defined(CONFIG_SPL_BUILD)
 251 int checkboard(void)
 252 {
 253 #ifdef CONFIG_TFABOOT
 254         enum boot_src src = get_boot_src();
 255 #endif
 256         char buf[64];
 257         u8 sw;
 258         static const char *const freq[] = {"100", "125", "156.25",
 259                                             "100 separate SSCG"};
 260         int clock;
 261
 262 #ifdef CONFIG_TARGET_LS1088AQDS
 263         printf("Board: LS1088A-QDS, ");
 264 #else
 265         if (is_pb_board())
 266                 printf("Board: LS1088ARDB-PB, ");
 267         else
 268                 printf("Board: LS1088A-RDB, ");
 269 #endif
 270
 271         sw = QIXIS_READ(arch);
 272         printf("Board Arch: V%d, ", sw >> 4);
 273
 274 #ifdef CONFIG_TARGET_LS1088AQDS
 275         printf("Board version: %c, boot from ", (sw & 0xf) + 'A' - 1);
 276 #else
 277         printf("Board version: %c, boot from ", (sw & 0xf) + 'A');
 278 #endif
 279
 280         memset((u8 *)buf, 0x00, ARRAY_SIZE(buf));
 281
 282         sw = QIXIS_READ(brdcfg[0]);
 283         sw = (sw & QIXIS_LBMAP_MASK) >> QIXIS_LBMAP_SHIFT;
 284
 285 #ifdef CONFIG_TFABOOT
 286         if (src == BOOT_SOURCE_SD_MMC)
 287                 puts("SD card\n");
 288 #else
 289 #ifdef CONFIG_SD_BOOT
 290         puts("SD card\n");
 291 #endif
 292 #endif /* CONFIG_TFABOOT */
 293         switch (sw) {
 294 #ifdef CONFIG_TARGET_LS1088AQDS
 295         case 0:
 296         case 1:
 297         case 2:
 298         case 3:
 299         case 4:
 300         case 5:
 301         case 6:
 302         case 7:
 303                 printf("vBank: %d\n", sw);
 304                 break;
 305         case 8:
 306                 puts("PromJet\n");
 307                 break;
 308         case 15:
 309                 puts("IFCCard\n");
 310                 break;
 311         case 14:
 312 #else
 313         case 0:
 314 #endif
 315                 puts("QSPI:");
 316                 sw = QIXIS_READ(brdcfg[0]);
 317                 sw = (sw & QIXIS_QMAP_MASK) >> QIXIS_QMAP_SHIFT;
 318                 if (sw == 0 || sw == 4)
 319                         puts("0\n");
 320                 else if (sw == 1)
 321                         puts("1\n");
 322                 else
 323                         puts("EMU\n");
 324                 break;
 325
 326         default:
 327                 printf("invalid setting of SW%u\n", QIXIS_LBMAP_SWITCH);
 328                 break;
 329         }
 330
 331 #ifdef CONFIG_TARGET_LS1088AQDS
 332         printf("FPGA: v%d (%s), build %d",
 333                (int)QIXIS_READ(scver), qixis_read_tag(buf),
 334                (int)qixis_read_minor());
 335         /* the timestamp string contains "\n" at the end */
 336         printf(" on %s", qixis_read_time(buf));
 337 #else
 338         printf("CPLD: v%d.%d\n", QIXIS_READ(scver), QIXIS_READ(tagdata));
 339 #endif
 340
 341         /*
 342          * Display the actual SERDES reference clocks as configured by the
 343          * dip switches on the board.  Note that the SWx registers could
 344          * technically be set to force the reference clocks to match the
 345          * values that the SERDES expects (or vice versa).  For now, however,
 346          * we just display both values and hope the user notices when they
 347          * don't match.
 348          */
 349         puts("SERDES1 Reference : ");
 350         sw = QIXIS_READ(brdcfg[2]);
 351         clock = (sw >> 6) & 3;
 352         printf("Clock1 = %sMHz ", freq[clock]);
 353         clock = (sw >> 4) & 3;
 354         printf("Clock2 = %sMHz", freq[clock]);
 355
 356         puts("\nSERDES2 Reference : ");
 357         clock = (sw >> 2) & 3;
 358         printf("Clock1 = %sMHz ", freq[clock]);
 359         clock = (sw >> 0) & 3;
 360         printf("Clock2 = %sMHz\n", freq[clock]);
 361
 362         return 0;
 363 }
 364 #endif
 365
 366 bool if_board_diff_clk(void)
 367 {
 368 #ifdef CONFIG_TARGET_LS1088AQDS
 369         u8 diff_conf = QIXIS_READ(brdcfg[11]);
 370         return diff_conf & 0x40;
 371 #else
 372         u8 diff_conf = QIXIS_READ(dutcfg[11]);
 373         return diff_conf & 0x80;
 374 #endif
 375 }
 376
 377 unsigned long get_board_sys_clk(void)
 378 {
 379         u8 sysclk_conf = QIXIS_READ(brdcfg[1]);
 380
 381         switch (sysclk_conf & 0x0f) {
 382         case QIXIS_SYSCLK_83:
 383                 return 83333333;
 384         case QIXIS_SYSCLK_100:
 385                 return 100000000;
 386         case QIXIS_SYSCLK_125:
 387                 return 125000000;
 388         case QIXIS_SYSCLK_133:
 389                 return 133333333;
 390         case QIXIS_SYSCLK_150:
 391                 return 150000000;
 392         case QIXIS_SYSCLK_160:
 393                 return 160000000;
 394         case QIXIS_SYSCLK_166:
 395                 return 166666666;
 396         }
 397
 398         return 66666666;
 399 }
 400
 401 unsigned long get_board_ddr_clk(void)
 402 {
 403         u8 ddrclk_conf = QIXIS_READ(brdcfg[1]);
 404
 405         if (if_board_diff_clk())
 406                 return get_board_sys_clk();
 407         switch ((ddrclk_conf & 0x30) >> 4) {
 408         case QIXIS_DDRCLK_100:
 409                 return 100000000;
 410         case QIXIS_DDRCLK_125:
 411                 return 125000000;
 412         case QIXIS_DDRCLK_133:
 413                 return 133333333;
 414         }
 415
 416         return 66666666;
 417 }
 418
 419 #if !defined(CONFIG_SPL_BUILD)
 420 void board_retimer_init(void)
 421 {
 422         u8 reg;
 423
 424         /* Retimer is connected to I2C1_CH5 */
 425         select_i2c_ch_pca9547(I2C_MUX_CH5, 0);
 426
 427         /* Access to Control/Shared register */
 428         reg = 0x0;
 429 #if !CONFIG_IS_ENABLED(DM_I2C)
 430         i2c_write(I2C_RETIMER_ADDR, 0xff, 1, &reg, 1);
 431 #else
 432         struct udevice *dev;
 433
 434         i2c_get_chip_for_busnum(0, I2C_RETIMER_ADDR, 1, &dev);
 435         dm_i2c_write(dev, 0xff, &reg, 1);
 436 #endif
 437
 438         /* Read device revision and ID */
 439 #if !CONFIG_IS_ENABLED(DM_I2C)
 440         i2c_read(I2C_RETIMER_ADDR, 1, 1, &reg, 1);
 441 #else
 442         dm_i2c_read(dev, 1, &reg, 1);
 443 #endif
 444         debug("Retimer version id = 0x%x\n", reg);
 445
 446         /* Enable Broadcast. All writes target all channel register sets */
 447         reg = 0x0c;
 448 #if !CONFIG_IS_ENABLED(DM_I2C)
 449         i2c_write(I2C_RETIMER_ADDR, 0xff, 1, &reg, 1);
 450 #else
 451         dm_i2c_write(dev, 0xff, &reg, 1);
 452 #endif
 453
 454         /* Reset Channel Registers */
 455 #if !CONFIG_IS_ENABLED(DM_I2C)
 456         i2c_read(I2C_RETIMER_ADDR, 0, 1, &reg, 1);
 457 #else
 458         dm_i2c_read(dev, 0, &reg, 1);
 459 #endif
 460         reg |= 0x4;
 461 #if !CONFIG_IS_ENABLED(DM_I2C)
 462         i2c_write(I2C_RETIMER_ADDR, 0, 1, &reg, 1);
 463 #else
 464         dm_i2c_write(dev, 0, &reg, 1);
 465 #endif
 466
 467         /* Set data rate as 10.3125 Gbps */
 468         reg = 0x90;
 469 #if !CONFIG_IS_ENABLED(DM_I2C)
 470         i2c_write(I2C_RETIMER_ADDR, 0x60, 1, &reg, 1);
 471 #else
 472         dm_i2c_write(dev, 0x60, &reg, 1);
 473 #endif
 474         reg = 0xb3;
 475 #if !CONFIG_IS_ENABLED(DM_I2C)
 476         i2c_write(I2C_RETIMER_ADDR, 0x61, 1, &reg, 1);
 477 #else
 478         dm_i2c_write(dev, 0x61, &reg, 1);
 479 #endif
 480         reg = 0x90;
 481 #if !CONFIG_IS_ENABLED(DM_I2C)
 482         i2c_write(I2C_RETIMER_ADDR, 0x62, 1, &reg, 1);
 483 #else
 484         dm_i2c_write(dev, 0x62, &reg, 1);
 485 #endif
 486         reg = 0xb3;
 487 #if !CONFIG_IS_ENABLED(DM_I2C)
 488         i2c_write(I2C_RETIMER_ADDR, 0x63, 1, &reg, 1);
 489 #else
 490         dm_i2c_write(dev, 0x63, &reg, 1);
 491 #endif
 492         reg = 0xcd;
 493 #if !CONFIG_IS_ENABLED(DM_I2C)
 494         i2c_write(I2C_RETIMER_ADDR, 0x64, 1, &reg, 1);
 495 #else
 496         dm_i2c_write(dev, 0x64, &reg, 1);
 497 #endif
 498
 499         /* Select VCO Divider to full rate (000) */
 500 #if !CONFIG_IS_ENABLED(DM_I2C)
 501         i2c_read(I2C_RETIMER_ADDR, 0x2F, 1, &reg, 1);
 502 #else
 503         dm_i2c_read(dev, 0x2F, &reg, 1);
 504 #endif
 505         reg &= 0x0f;
 506         reg |= 0x70;
 507 #if !CONFIG_IS_ENABLED(DM_I2C)
 508         i2c_write(I2C_RETIMER_ADDR, 0x2F, 1, &reg, 1);
 509 #else
 510         dm_i2c_write(dev, 0x2F, &reg, 1);
 511 #endif
 512
 513 #ifdef  CONFIG_TARGET_LS1088AQDS
 514         /* Retimer is connected to I2C1_CH5 */
 515         select_i2c_ch_pca9547(I2C_MUX_CH5, 0);
 516
 517         /* Access to Control/Shared register */
 518         reg = 0x0;
 519 #if !CONFIG_IS_ENABLED(DM_I2C)
 520         i2c_write(I2C_RETIMER_ADDR2, 0xff, 1, &reg, 1);
 521 #else
 522         i2c_get_chip_for_busnum(0, I2C_RETIMER_ADDR2, 1, &dev);
 523         dm_i2c_write(dev, 0xff, &reg, 1);
 524 #endif
 525
 526         /* Read device revision and ID */
 527 #if !CONFIG_IS_ENABLED(DM_I2C)
 528         i2c_read(I2C_RETIMER_ADDR2, 1, 1, &reg, 1);
 529 #else
 530         dm_i2c_read(dev, 1, &reg, 1);
 531 #endif
 532         debug("Retimer version id = 0x%x\n", reg);
 533
 534         /* Enable Broadcast. All writes target all channel register sets */
 535         reg = 0x0c;
 536 #if !CONFIG_IS_ENABLED(DM_I2C)
 537         i2c_write(I2C_RETIMER_ADDR2, 0xff, 1, &reg, 1);
 538 #else
 539         dm_i2c_write(dev, 0xff, &reg, 1);
 540 #endif
 541
 542         /* Reset Channel Registers */
 543 #if !CONFIG_IS_ENABLED(DM_I2C)
 544         i2c_read(I2C_RETIMER_ADDR2, 0, 1, &reg, 1);
 545 #else
 546         dm_i2c_read(dev, 0, &reg, 1);
 547 #endif
 548         reg |= 0x4;
 549 #if !CONFIG_IS_ENABLED(DM_I2C)
 550         i2c_write(I2C_RETIMER_ADDR2, 0, 1, &reg, 1);
 551 #else
 552         dm_i2c_write(dev, 0, &reg, 1);
 553 #endif
 554
 555         /* Set data rate as 10.3125 Gbps */
 556         reg = 0x90;
 557 #if !CONFIG_IS_ENABLED(DM_I2C)
 558         i2c_write(I2C_RETIMER_ADDR2, 0x60, 1, &reg, 1);
 559 #else
 560         dm_i2c_write(dev, 0x60, &reg, 1);
 561 #endif
 562         reg = 0xb3;
 563 #if !CONFIG_IS_ENABLED(DM_I2C)
 564         i2c_write(I2C_RETIMER_ADDR2, 0x61, 1, &reg, 1);
 565 #else
 566         dm_i2c_write(dev, 0x61, &reg, 1);
 567 #endif
 568         reg = 0x90;
 569 #if !CONFIG_IS_ENABLED(DM_I2C)
 570         i2c_write(I2C_RETIMER_ADDR2, 0x62, 1, &reg, 1);
 571 #else
 572         dm_i2c_write(dev, 0x62, &reg, 1);
 573 #endif
 574         reg = 0xb3;
 575 #if !CONFIG_IS_ENABLED(DM_I2C)
 576         i2c_write(I2C_RETIMER_ADDR2, 0x63, 1, &reg, 1);
 577 #else
 578         dm_i2c_write(dev, 0x63, &reg, 1);
 579 #endif
 580         reg = 0xcd;
 581 #if !CONFIG_IS_ENABLED(DM_I2C)
 582         i2c_write(I2C_RETIMER_ADDR2, 0x64, 1, &reg, 1);
 583 #else
 584         dm_i2c_write(dev, 0x64, &reg, 1);
 585 #endif
 586
 587         /* Select VCO Divider to full rate (000) */
 588 #if !CONFIG_IS_ENABLED(DM_I2C)
 589         i2c_read(I2C_RETIMER_ADDR2, 0x2F, 1, &reg, 1);
 590 #else
 591         dm_i2c_read(dev, 0x2F, &reg, 1);
 592 #endif
 593         reg &= 0x0f;
 594         reg |= 0x70;
 595 #if !CONFIG_IS_ENABLED(DM_I2C)
 596         i2c_write(I2C_RETIMER_ADDR2, 0x2F, 1, &reg, 1);
 597 #else
 598         dm_i2c_write(dev, 0x2F, &reg, 1);
 599 #endif
 600
 601 #endif
 602         /*return the default channel*/
 603         select_i2c_ch_pca9547(I2C_MUX_CH_DEFAULT, 0);
 604 }
 605
 606 #ifdef CONFIG_MISC_INIT_R
 607 int misc_init_r(void)
 608 {
 609 #ifdef CONFIG_TARGET_LS1088ARDB
 610         u8 brdcfg5;
 611
 612         if (hwconfig("esdhc-force-sd")) {
 613                 brdcfg5 = QIXIS_READ(brdcfg[5]);
 614                 brdcfg5 &= ~BRDCFG5_SPISDHC_MASK;
 615                 brdcfg5 |= BRDCFG5_FORCE_SD;
 616                 QIXIS_WRITE(brdcfg[5], brdcfg5);
 617         }
 618 #endif
 619
 620 #ifdef CONFIG_TARGET_LS1088AQDS
 621          u8 brdcfg4, brdcfg5;
 622
 623         if (hwconfig("dspi-on-board")) {
 624                 brdcfg4 = QIXIS_READ(brdcfg[4]);
 625                 brdcfg4 &= ~BRDCFG4_USBOSC_MASK;
 626                 brdcfg4 |= BRDCFG4_SPI;
 627                 QIXIS_WRITE(brdcfg[4], brdcfg4);
 628
 629                 brdcfg5 = QIXIS_READ(brdcfg[5]);
 630                 brdcfg5 &= ~BRDCFG5_SPR_MASK;
 631                 brdcfg5 |= BRDCFG5_SPI_ON_BOARD;
 632                 QIXIS_WRITE(brdcfg[5], brdcfg5);
 633         } else if (hwconfig("dspi-off-board")) {
 634                 brdcfg4 = QIXIS_READ(brdcfg[4]);
 635                 brdcfg4 &= ~BRDCFG4_USBOSC_MASK;
 636                 brdcfg4 |= BRDCFG4_SPI;
 637                 QIXIS_WRITE(brdcfg[4], brdcfg4);
 638
 639                 brdcfg5 = QIXIS_READ(brdcfg[5]);
 640                 brdcfg5 &= ~BRDCFG5_SPR_MASK;
 641                 brdcfg5 |= BRDCFG5_SPI_OFF_BOARD;
 642                 QIXIS_WRITE(brdcfg[5], brdcfg5);
 643         }
 644 #endif
 645         return 0;
 646 }
 647 #endif
 648 #endif
 649
 650 int i2c_multiplexer_select_vid_channel(u8 channel)
 651 {
 652         return select_i2c_ch_pca9547(channel, 0);
 653 }
 654
 655 #ifdef CONFIG_TARGET_LS1088AQDS
 656 /* read the current value(SVDD) of the LTM Regulator Voltage */
 657 int get_serdes_volt(void)
 658 {
 659         int  ret, vcode = 0;
 660         u8 chan = PWM_CHANNEL0;
 661
 662         /* Select the PAGE 0 using PMBus commands PAGE for VDD */
 663 #if !CONFIG_IS_ENABLED(DM_I2C)
 664         ret = i2c_write(I2C_SVDD_MONITOR_ADDR,
 665                         PMBUS_CMD_PAGE, 1, &chan, 1);
 666 #else
 667         struct udevice *dev;
 668
 669         ret = i2c_get_chip_for_busnum(0, I2C_SVDD_MONITOR_ADDR, 1, &dev);
 670         if (!ret)
 671                 ret = dm_i2c_write(dev, PMBUS_CMD_PAGE,
 672                                    &chan, 1);
 673 #endif
 674
 675         if (ret) {
 676                 printf("VID: failed to select VDD Page 0\n");
 677                 return ret;
 678         }
 679
 680         /* Read the output voltage using PMBus command READ_VOUT */
 681 #if !CONFIG_IS_ENABLED(DM_I2C)
 682         ret = i2c_read(I2C_SVDD_MONITOR_ADDR,
 683                        PMBUS_CMD_READ_VOUT, 1, (void *)&vcode, 2);
 684 #else
 685         dm_i2c_read(dev, PMBUS_CMD_READ_VOUT, (void *)&vcode, 2);
 686 #endif
 687         if (ret) {
 688                 printf("VID: failed to read the volatge\n");
 689                 return ret;
 690         }
 691
 692         return vcode;
 693 }
 694
 695 int set_serdes_volt(int svdd)
 696 {
 697         int ret, vdd_last;
 698         u8 buff[5] = {0x04, PWM_CHANNEL0, PMBUS_CMD_VOUT_COMMAND,
 699                         svdd & 0xFF, (svdd & 0xFF00) >> 8};
 700
 701         /* Write the desired voltage code to the SVDD regulator */
 702 #if !CONFIG_IS_ENABLED(DM_I2C)
 703         ret = i2c_write(I2C_SVDD_MONITOR_ADDR,
 704                         PMBUS_CMD_PAGE_PLUS_WRITE, 1, (void *)&buff, 5);
 705 #else
 706         struct udevice *dev;
 707
 708         ret = i2c_get_chip_for_busnum(0, I2C_SVDD_MONITOR_ADDR, 1, &dev);
 709         if (!ret)
 710                 ret = dm_i2c_write(dev, PMBUS_CMD_PAGE_PLUS_WRITE,
 711                                    (void *)&buff, 5);
 712 #endif
 713         if (ret) {
 714                 printf("VID: I2C failed to write to the volatge regulator\n");
 715                 return -1;
 716         }
 717
 718         /* Wait for the volatge to get to the desired value */
 719         do {
 720                 vdd_last = get_serdes_volt();
 721                 if (vdd_last < 0) {
 722                         printf("VID: Couldn't read sensor abort VID adjust\n");
 723                         return -1;
 724                 }
 725         } while (vdd_last != svdd);
 726
 727         return 1;
 728 }
 729 #else
 730 int get_serdes_volt(void)
 731 {
 732         return 0;
 733 }
 734
 735 int set_serdes_volt(int svdd)
 736 {
 737         int ret;
 738         u8 brdcfg4;
 739
 740         printf("SVDD changing of RDB\n");
 741
 742         /* Read the BRDCFG54 via CLPD */
 743 #if !CONFIG_IS_ENABLED(DM_I2C)
 744         ret = i2c_read(CONFIG_SYS_I2C_FPGA_ADDR,
 745                        QIXIS_BRDCFG4_OFFSET, 1, (void *)&brdcfg4, 1);
 746 #else
 747         struct udevice *dev;
 748
 749         ret = i2c_get_chip_for_busnum(0, CONFIG_SYS_I2C_FPGA_ADDR, 1, &dev);
 750         if (!ret)
 751                 ret = dm_i2c_read(dev, QIXIS_BRDCFG4_OFFSET,
 752                                   (void *)&brdcfg4, 1);
 753 #endif
 754
 755         if (ret) {
 756                 printf("VID: I2C failed to read the CPLD BRDCFG4\n");
 757                 return -1;
 758         }
 759
 760         brdcfg4 = brdcfg4 | 0x08;
 761
 762         /* Write to the BRDCFG4 */
 763 #if !CONFIG_IS_ENABLED(DM_I2C)
 764         ret = i2c_write(CONFIG_SYS_I2C_FPGA_ADDR,
 765                         QIXIS_BRDCFG4_OFFSET, 1, (void *)&brdcfg4, 1);
 766 #else
 767         ret = dm_i2c_write(dev, QIXIS_BRDCFG4_OFFSET,
 768                            (void *)&brdcfg4, 1);
 769 #endif
 770
 771         if (ret) {
 772                 debug("VID: I2C failed to set the SVDD CPLD BRDCFG4\n");
 773                 return -1;
 774         }
 775
 776         /* Wait for the volatge to get to the desired value */
 777         udelay(10000);
 778
 779         return 1;
 780 }
 781 #endif
 782
 783 /* this function disables the SERDES, changes the SVDD Voltage and enables it*/
 784 int board_adjust_vdd(int vdd)
 785 {
 786         int ret = 0;
 787
 788         debug("%s: vdd = %d\n", __func__, vdd);
 789
 790         /* Special settings to be performed when voltage is 900mV */
 791         if (vdd == 900) {
 792                 ret = setup_serdes_volt(vdd);
 793                 if (ret < 0) {
 794                         ret = -1;
 795                         goto exit;
 796                 }
 797         }
 798 exit:
 799         return ret;
 800 }
 801
 802 #if !defined(CONFIG_SPL_BUILD)
 803 int board_init(void)
 804 {
 805         init_final_memctl_regs();
 806 #if defined(CONFIG_TARGET_LS1088ARDB) && defined(CONFIG_FSL_MC_ENET)
 807         u32 __iomem *irq_ccsr = (u32 __iomem *)ISC_BASE;
 808 #endif
 809
 810         select_i2c_ch_pca9547(I2C_MUX_CH_DEFAULT, 0);
 811         board_retimer_init();
 812
 813 #ifdef CONFIG_ENV_IS_NOWHERE
 814         gd->env_addr = (ulong)&default_environment[0];
 815 #endif
 816
 817 #if defined(CONFIG_TARGET_LS1088ARDB) && defined(CONFIG_FSL_MC_ENET)
 818         /* invert AQR105 IRQ pins polarity */
 819         out_le32(irq_ccsr + IRQCR_OFFSET / 4, AQR105_IRQ_MASK);
 820 #endif
 821
 822 #ifdef CONFIG_FSL_CAAM
 823         sec_init();
 824 #endif
 825 #ifdef CONFIG_FSL_LS_PPA
 826         ppa_init();
 827 #endif
 828
 829 #if !defined(CONFIG_SYS_EARLY_PCI_INIT) && defined(CONFIG_DM_ETH)
 830         pci_init();
 831 #endif
 832
 833         return 0;
 834 }
 835
 836 void detail_board_ddr_info(void)
 837 {
 838         puts("\nDDR    ");
 839         print_size(gd->bd->bi_dram[0].size + gd->bd->bi_dram[1].size, "");
 840         print_ddr_info(0);
 841 }
 842
 843 #ifdef CONFIG_FSL_MC_ENET
 844 void board_quiesce_devices(void)
 845 {
 846         fsl_mc_ldpaa_exit(gd->bd);
 847 }
 848
 849 void fdt_fixup_board_enet(void *fdt)
 850 {
 851         int offset;
 852
 853         offset = fdt_path_offset(fdt, "/fsl-mc");
 854
 855         if (offset < 0)
 856                 offset = fdt_path_offset(fdt, "/soc/fsl-mc");
 857
 858         if (offset < 0) {
 859                 printf("%s: ERROR: fsl-mc node not found in device tree (error %d)\n",
 860                        __func__, offset);
 861                 return;
 862         }
 863
 864         if (get_mc_boot_status() == 0 &&
 865             (is_lazy_dpl_addr_valid() || get_dpl_apply_status() == 0))
 866                 fdt_status_okay(fdt, offset);
 867         else
 868                 fdt_status_fail(fdt, offset);
 869 }
 870 #endif
 871
 872 #ifdef CONFIG_OF_BOARD_SETUP
 873 void fsl_fdt_fixup_flash(void *fdt)
 874 {
 875         int offset;
 876 #ifdef CONFIG_TFABOOT
 877         u32 __iomem *dcfg_ccsr = (u32 __iomem *)DCFG_BASE;
 878         u32 val;
 879 #endif
 880
 881 /*
 882  * IFC-NOR and QSPI are muxed on SoC.
 883  * So disable IFC node in dts if QSPI is enabled or
 884  * disable QSPI node in dts in case QSPI is not enabled.
 885  */
 886
 887 #ifdef CONFIG_TFABOOT
 888         enum boot_src src = get_boot_src();
 889         bool disable_ifc = false;
 890
 891         switch (src) {
 892         case BOOT_SOURCE_IFC_NOR:
 893                 disable_ifc = false;
 894                 break;
 895         case BOOT_SOURCE_QSPI_NOR:
 896                 disable_ifc = true;
 897                 break;
 898         default:
 899                 val = in_le32(dcfg_ccsr + DCFG_RCWSR15 / 4);
 900                 if (DCFG_RCWSR15_IFCGRPABASE_QSPI == (val & (u32)0x3))
 901                         disable_ifc = true;
 902                 break;
 903         }
 904
 905         if (disable_ifc) {
 906                 offset = fdt_path_offset(fdt, "/soc/ifc/nor");
 907
 908                 if (offset < 0)
 909                         offset = fdt_path_offset(fdt, "/ifc/nor");
 910         } else {
 911                 offset = fdt_path_offset(fdt, "/soc/quadspi");
 912
 913                 if (offset < 0)
 914                         offset = fdt_path_offset(fdt, "/quadspi");
 915         }
 916
 917 #else
 918 #ifdef CONFIG_FSL_QSPI
 919         offset = fdt_path_offset(fdt, "/soc/ifc/nor");
 920
 921         if (offset < 0)
 922                 offset = fdt_path_offset(fdt, "/ifc/nor");
 923 #else
 924         offset = fdt_path_offset(fdt, "/soc/quadspi");
 925
 926         if (offset < 0)
 927                 offset = fdt_path_offset(fdt, "/quadspi");
 928 #endif
 929 #endif
 930         if (offset < 0)
 931                 return;
 932
 933         fdt_status_disabled(fdt, offset);
 934 }
 935
 936 int ft_board_setup(void *blob, struct bd_info *bd)
 937 {
 938         int i;
 939         u16 mc_memory_bank = 0;
 940
 941         u64 *base;
 942         u64 *size;
 943         u64 mc_memory_base = 0;
 944         u64 mc_memory_size = 0;
 945         u16 total_memory_banks;
 946
 947         ft_cpu_setup(blob, bd);
 948
 949         fdt_fixup_mc_ddr(&mc_memory_base, &mc_memory_size);
 950
 951         if (mc_memory_base != 0)
 952                 mc_memory_bank++;
 953
 954         total_memory_banks = CONFIG_NR_DRAM_BANKS + mc_memory_bank;
 955
 956         base = calloc(total_memory_banks, sizeof(u64));
 957         size = calloc(total_memory_banks, sizeof(u64));
 958
 959         /* fixup DT for the two GPP DDR banks */
 960         for (i = 0; i < CONFIG_NR_DRAM_BANKS; i++) {
 961                 base[i] = gd->bd->bi_dram[i].start;
 962                 size[i] = gd->bd->bi_dram[i].size;
 963         }
 964
 965 #ifdef CONFIG_RESV_RAM
 966         /* reduce size if reserved memory is within this bank */
 967         if (gd->arch.resv_ram >= base[0] &&
 968             gd->arch.resv_ram < base[0] + size[0])
 969                 size[0] = gd->arch.resv_ram - base[0];
 970         else if (gd->arch.resv_ram >= base[1] &&
 971                  gd->arch.resv_ram < base[1] + size[1])
 972                 size[1] = gd->arch.resv_ram - base[1];
 973 #endif
 974
 975         if (mc_memory_base != 0) {
 976                 for (i = 0; i <= total_memory_banks; i++) {
 977                         if (base[i] == 0 && size[i] == 0) {
 978                                 base[i] = mc_memory_base;
 979                                 size[i] = mc_memory_size;
 980                                 break;
 981                         }
 982                 }
 983         }
 984
 985         fdt_fixup_memory_banks(blob, base, size, total_memory_banks);
 986
 987         fdt_fsl_mc_fixup_iommu_map_entry(blob);
 988
 989         fsl_fdt_fixup_flash(blob);
 990
 991 #ifdef CONFIG_FSL_MC_ENET
 992         fdt_fixup_board_enet(blob);
 993 #endif
 994
 995         fdt_fixup_icid(blob);
 996
 997         if (is_pb_board())
 998                 fixup_ls1088ardb_pb_banner(blob);
 999
1000         return 0;
1001 }
1002 #endif
1003 #endif /* defined(CONFIG_SPL_BUILD) */
1004
1005 #ifdef CONFIG_TFABOOT
1006 #ifdef CONFIG_MTD_NOR_FLASH
1007 int is_flash_available(void)
1008 {
1009         char *env_hwconfig = env_get("hwconfig");
1010         enum boot_src src = get_boot_src();
1011         int is_nor_flash_available = 1;
1012
1013         switch (src) {
1014         case BOOT_SOURCE_IFC_NOR:
1015                 is_nor_flash_available = 1;
1016                 break;
1017         case BOOT_SOURCE_QSPI_NOR:
1018                 is_nor_flash_available = 0;
1019                 break;
1020         /*
1021          * In Case of SD boot,if qspi is defined in env_hwconfig
1022          * disable nor flash probe.
1023          */
1024         default:
1025                 if (hwconfig_f("qspi", env_hwconfig))
1026                         is_nor_flash_available = 0;
1027                 break;
1028         }
1029         return is_nor_flash_available;
1030 }
1031 #endif
1032
1033 #ifdef CONFIG_ENV_IS_IN_SPI_FLASH
1034 void *env_sf_get_env_addr(void)
1035 {
1036         return (void *)(CONFIG_SYS_FSL_QSPI_BASE + CONFIG_ENV_OFFSET);
1037 }
1038 #endif
1039 #endif