1 // SPDX-License-Identifier: GPL-2.0+
3 * Copyright 2017-2018 NXP
16 #include <fdt_support.h>
17 #include <linux/libfdt.h>
18 #include <fsl-mc/fsl_mc.h>
19 #include <env_internal.h>
20 #include <asm/arch-fsl-layerscape/soc.h>
21 #include <asm/arch/ppa.h>
23 #include <asm/arch/fsl_serdes.h>
24 #include <asm/arch/soc.h>
25 #include <asm/arch-fsl-layerscape/fsl_icid.h>
27 #include "../common/qixis.h"
28 #include "ls1088a_qixis.h"
29 #include "../common/vid.h"
30 #include <fsl_immap.h>
32 DECLARE_GLOBAL_DATA_PTR;
34 #ifdef CONFIG_TARGET_LS1088AQDS
36 struct ifc_regs ifc_cfg_ifc_nor_boot[CONFIG_SYS_FSL_IFC_BANK_COUNT] = {
39 CONFIG_SYS_NOR0_CSPR_EARLY,
40 CONFIG_SYS_NOR0_CSPR_EXT,
55 CONFIG_SYS_NOR1_CSPR_EARLY,
56 CONFIG_SYS_NOR0_CSPR_EXT,
57 CONFIG_SYS_NOR_AMASK_EARLY,
72 CONFIG_SYS_NAND_CSPR_EXT,
73 CONFIG_SYS_NAND_AMASK,
76 CONFIG_SYS_NAND_FTIM0,
77 CONFIG_SYS_NAND_FTIM1,
78 CONFIG_SYS_NAND_FTIM2,
85 CONFIG_SYS_FPGA_CSPR_EXT,
100 struct ifc_regs ifc_cfg_qspi_nor_boot[CONFIG_SYS_FSL_IFC_BANK_COUNT] = {
103 CONFIG_SYS_NAND_CSPR,
104 CONFIG_SYS_NAND_CSPR_EXT,
105 CONFIG_SYS_NAND_AMASK,
106 CONFIG_SYS_NAND_CSOR,
108 CONFIG_SYS_NAND_FTIM0,
109 CONFIG_SYS_NAND_FTIM1,
110 CONFIG_SYS_NAND_FTIM2,
111 CONFIG_SYS_NAND_FTIM3
119 CONFIG_SYS_FPGA_CSPR,
120 CONFIG_SYS_FPGA_CSPR_EXT,
122 CONFIG_SYS_FPGA_CSOR,
135 void ifc_cfg_boot_info(struct ifc_regs_info *regs_info)
137 enum boot_src src = get_boot_src();
139 if (src == BOOT_SOURCE_QSPI_NOR)
140 regs_info->regs = ifc_cfg_qspi_nor_boot;
142 regs_info->regs = ifc_cfg_ifc_nor_boot;
144 regs_info->cs_size = CONFIG_SYS_FSL_IFC_BANK_COUNT;
146 #endif /* CONFIG_TFABOOT */
147 #endif /* CONFIG_TARGET_LS1088AQDS */
149 int board_early_init_f(void)
151 #if defined(CONFIG_SYS_I2C_EARLY_INIT) && defined(CONFIG_TARGET_LS1088AQDS)
154 fsl_lsch3_early_init_f();
158 #ifdef CONFIG_FSL_QIXIS
159 unsigned long long get_qixis_addr(void)
161 unsigned long long addr;
163 if (gd->flags & GD_FLG_RELOC)
164 addr = QIXIS_BASE_PHYS;
166 addr = QIXIS_BASE_PHYS_EARLY;
169 * IFC address under 256MB is mapped to 0x30000000, any address above
170 * is mapped to 0x5_10000000 up to 4GB.
172 addr = addr > 0x10000000 ? addr + 0x500000000ULL : addr + 0x30000000;
178 #if defined(CONFIG_VID)
179 int init_func_vid(void)
181 if (adjust_vdd(0) < 0)
182 printf("core voltage not adjusted\n");
188 int is_pb_board(void)
192 board_id = QIXIS_READ(id);
193 if (board_id == LS1088ARDB_PB_BOARD)
199 int fixup_ls1088ardb_pb_banner(void *fdt)
201 fdt_setprop_string(fdt, 0, "model", "LS1088ARDB-PB Board");
206 #if !defined(CONFIG_SPL_BUILD)
209 #ifdef CONFIG_TFABOOT
210 enum boot_src src = get_boot_src();
214 static const char *const freq[] = {"100", "125", "156.25",
215 "100 separate SSCG"};
218 #ifdef CONFIG_TARGET_LS1088AQDS
219 printf("Board: LS1088A-QDS, ");
222 printf("Board: LS1088ARDB-PB, ");
224 printf("Board: LS1088A-RDB, ");
227 sw = QIXIS_READ(arch);
228 printf("Board Arch: V%d, ", sw >> 4);
230 #ifdef CONFIG_TARGET_LS1088AQDS
231 printf("Board version: %c, boot from ", (sw & 0xf) + 'A' - 1);
233 printf("Board version: %c, boot from ", (sw & 0xf) + 'A');
236 memset((u8 *)buf, 0x00, ARRAY_SIZE(buf));
238 sw = QIXIS_READ(brdcfg[0]);
239 sw = (sw & QIXIS_LBMAP_MASK) >> QIXIS_LBMAP_SHIFT;
241 #ifdef CONFIG_TFABOOT
242 if (src == BOOT_SOURCE_SD_MMC)
245 #ifdef CONFIG_SD_BOOT
248 #endif /* CONFIG_TFABOOT */
250 #ifdef CONFIG_TARGET_LS1088AQDS
259 printf("vBank: %d\n", sw);
272 sw = QIXIS_READ(brdcfg[0]);
273 sw = (sw & QIXIS_QMAP_MASK) >> QIXIS_QMAP_SHIFT;
274 if (sw == 0 || sw == 4)
283 printf("invalid setting of SW%u\n", QIXIS_LBMAP_SWITCH);
287 #ifdef CONFIG_TARGET_LS1088AQDS
288 printf("FPGA: v%d (%s), build %d",
289 (int)QIXIS_READ(scver), qixis_read_tag(buf),
290 (int)qixis_read_minor());
291 /* the timestamp string contains "\n" at the end */
292 printf(" on %s", qixis_read_time(buf));
294 printf("CPLD: v%d.%d\n", QIXIS_READ(scver), QIXIS_READ(tagdata));
298 * Display the actual SERDES reference clocks as configured by the
299 * dip switches on the board. Note that the SWx registers could
300 * technically be set to force the reference clocks to match the
301 * values that the SERDES expects (or vice versa). For now, however,
302 * we just display both values and hope the user notices when they
305 puts("SERDES1 Reference : ");
306 sw = QIXIS_READ(brdcfg[2]);
307 clock = (sw >> 6) & 3;
308 printf("Clock1 = %sMHz ", freq[clock]);
309 clock = (sw >> 4) & 3;
310 printf("Clock2 = %sMHz", freq[clock]);
312 puts("\nSERDES2 Reference : ");
313 clock = (sw >> 2) & 3;
314 printf("Clock1 = %sMHz ", freq[clock]);
315 clock = (sw >> 0) & 3;
316 printf("Clock2 = %sMHz\n", freq[clock]);
322 bool if_board_diff_clk(void)
324 #ifdef CONFIG_TARGET_LS1088AQDS
325 u8 diff_conf = QIXIS_READ(brdcfg[11]);
326 return diff_conf & 0x40;
328 u8 diff_conf = QIXIS_READ(dutcfg[11]);
329 return diff_conf & 0x80;
333 unsigned long get_board_sys_clk(void)
335 u8 sysclk_conf = QIXIS_READ(brdcfg[1]);
337 switch (sysclk_conf & 0x0f) {
338 case QIXIS_SYSCLK_83:
340 case QIXIS_SYSCLK_100:
342 case QIXIS_SYSCLK_125:
344 case QIXIS_SYSCLK_133:
346 case QIXIS_SYSCLK_150:
348 case QIXIS_SYSCLK_160:
350 case QIXIS_SYSCLK_166:
357 unsigned long get_board_ddr_clk(void)
359 u8 ddrclk_conf = QIXIS_READ(brdcfg[1]);
361 if (if_board_diff_clk())
362 return get_board_sys_clk();
363 switch ((ddrclk_conf & 0x30) >> 4) {
364 case QIXIS_DDRCLK_100:
366 case QIXIS_DDRCLK_125:
368 case QIXIS_DDRCLK_133:
375 int select_i2c_ch_pca9547(u8 ch)
379 #ifndef CONFIG_DM_I2C
380 ret = i2c_write(I2C_MUX_PCA_ADDR_PRI, 0, 1, &ch, 1);
384 ret = i2c_get_chip_for_busnum(0, I2C_MUX_PCA_ADDR_PRI, 1, &dev);
386 ret = dm_i2c_write(dev, 0, &ch, 1);
389 puts("PCA: failed to select proper channel\n");
396 #if !defined(CONFIG_SPL_BUILD)
397 void board_retimer_init(void)
401 /* Retimer is connected to I2C1_CH5 */
402 select_i2c_ch_pca9547(I2C_MUX_CH5);
404 /* Access to Control/Shared register */
406 #ifndef CONFIG_DM_I2C
407 i2c_write(I2C_RETIMER_ADDR, 0xff, 1, ®, 1);
411 i2c_get_chip_for_busnum(0, I2C_RETIMER_ADDR, 1, &dev);
412 dm_i2c_write(dev, 0xff, ®, 1);
415 /* Read device revision and ID */
416 #ifndef CONFIG_DM_I2C
417 i2c_read(I2C_RETIMER_ADDR, 1, 1, ®, 1);
419 dm_i2c_read(dev, 1, ®, 1);
421 debug("Retimer version id = 0x%x\n", reg);
423 /* Enable Broadcast. All writes target all channel register sets */
425 #ifndef CONFIG_DM_I2C
426 i2c_write(I2C_RETIMER_ADDR, 0xff, 1, ®, 1);
428 dm_i2c_write(dev, 0xff, ®, 1);
431 /* Reset Channel Registers */
432 #ifndef CONFIG_DM_I2C
433 i2c_read(I2C_RETIMER_ADDR, 0, 1, ®, 1);
435 dm_i2c_read(dev, 0, ®, 1);
438 #ifndef CONFIG_DM_I2C
439 i2c_write(I2C_RETIMER_ADDR, 0, 1, ®, 1);
441 dm_i2c_write(dev, 0, ®, 1);
444 /* Set data rate as 10.3125 Gbps */
446 #ifndef CONFIG_DM_I2C
447 i2c_write(I2C_RETIMER_ADDR, 0x60, 1, ®, 1);
449 dm_i2c_write(dev, 0x60, ®, 1);
452 #ifndef CONFIG_DM_I2C
453 i2c_write(I2C_RETIMER_ADDR, 0x61, 1, ®, 1);
455 dm_i2c_write(dev, 0x61, ®, 1);
458 #ifndef CONFIG_DM_I2C
459 i2c_write(I2C_RETIMER_ADDR, 0x62, 1, ®, 1);
461 dm_i2c_write(dev, 0x62, ®, 1);
464 #ifndef CONFIG_DM_I2C
465 i2c_write(I2C_RETIMER_ADDR, 0x63, 1, ®, 1);
467 dm_i2c_write(dev, 0x63, ®, 1);
470 #ifndef CONFIG_DM_I2C
471 i2c_write(I2C_RETIMER_ADDR, 0x64, 1, ®, 1);
473 dm_i2c_write(dev, 0x64, ®, 1);
476 /* Select VCO Divider to full rate (000) */
477 #ifndef CONFIG_DM_I2C
478 i2c_read(I2C_RETIMER_ADDR, 0x2F, 1, ®, 1);
480 dm_i2c_read(dev, 0x2F, ®, 1);
484 #ifndef CONFIG_DM_I2C
485 i2c_write(I2C_RETIMER_ADDR, 0x2F, 1, ®, 1);
487 dm_i2c_write(dev, 0x2F, ®, 1);
490 #ifdef CONFIG_TARGET_LS1088AQDS
491 /* Retimer is connected to I2C1_CH5 */
492 select_i2c_ch_pca9547(I2C_MUX_CH5);
494 /* Access to Control/Shared register */
496 #ifndef CONFIG_DM_I2C
497 i2c_write(I2C_RETIMER_ADDR2, 0xff, 1, ®, 1);
499 i2c_get_chip_for_busnum(0, I2C_RETIMER_ADDR2, 1, &dev);
500 dm_i2c_write(dev, 0xff, ®, 1);
503 /* Read device revision and ID */
504 #ifndef CONFIG_DM_I2C
505 i2c_read(I2C_RETIMER_ADDR2, 1, 1, ®, 1);
507 dm_i2c_read(dev, 1, ®, 1);
509 debug("Retimer version id = 0x%x\n", reg);
511 /* Enable Broadcast. All writes target all channel register sets */
513 #ifndef CONFIG_DM_I2C
514 i2c_write(I2C_RETIMER_ADDR2, 0xff, 1, ®, 1);
516 dm_i2c_write(dev, 0xff, ®, 1);
519 /* Reset Channel Registers */
520 #ifndef CONFIG_DM_I2C
521 i2c_read(I2C_RETIMER_ADDR2, 0, 1, ®, 1);
523 dm_i2c_read(dev, 0, ®, 1);
526 #ifndef CONFIG_DM_I2C
527 i2c_write(I2C_RETIMER_ADDR2, 0, 1, ®, 1);
529 dm_i2c_write(dev, 0, ®, 1);
532 /* Set data rate as 10.3125 Gbps */
534 #ifndef CONFIG_DM_I2C
535 i2c_write(I2C_RETIMER_ADDR2, 0x60, 1, ®, 1);
537 dm_i2c_write(dev, 0x60, ®, 1);
540 #ifndef CONFIG_DM_I2C
541 i2c_write(I2C_RETIMER_ADDR2, 0x61, 1, ®, 1);
543 dm_i2c_write(dev, 0x61, ®, 1);
546 #ifndef CONFIG_DM_I2C
547 i2c_write(I2C_RETIMER_ADDR2, 0x62, 1, ®, 1);
549 dm_i2c_write(dev, 0x62, ®, 1);
552 #ifndef CONFIG_DM_I2C
553 i2c_write(I2C_RETIMER_ADDR2, 0x63, 1, ®, 1);
555 dm_i2c_write(dev, 0x63, ®, 1);
558 #ifndef CONFIG_DM_I2C
559 i2c_write(I2C_RETIMER_ADDR2, 0x64, 1, ®, 1);
561 dm_i2c_write(dev, 0x64, ®, 1);
564 /* Select VCO Divider to full rate (000) */
565 #ifndef CONFIG_DM_I2C
566 i2c_read(I2C_RETIMER_ADDR2, 0x2F, 1, ®, 1);
568 dm_i2c_read(dev, 0x2F, ®, 1);
572 #ifndef CONFIG_DM_I2C
573 i2c_write(I2C_RETIMER_ADDR2, 0x2F, 1, ®, 1);
575 dm_i2c_write(dev, 0x2F, ®, 1);
579 /*return the default channel*/
580 select_i2c_ch_pca9547(I2C_MUX_CH_DEFAULT);
583 #ifdef CONFIG_MISC_INIT_R
584 int misc_init_r(void)
586 #ifdef CONFIG_TARGET_LS1088ARDB
589 if (hwconfig("esdhc-force-sd")) {
590 brdcfg5 = QIXIS_READ(brdcfg[5]);
591 brdcfg5 &= ~BRDCFG5_SPISDHC_MASK;
592 brdcfg5 |= BRDCFG5_FORCE_SD;
593 QIXIS_WRITE(brdcfg[5], brdcfg5);
597 #ifdef CONFIG_TARGET_LS1088AQDS
600 if (hwconfig("dspi-on-board")) {
601 brdcfg4 = QIXIS_READ(brdcfg[4]);
602 brdcfg4 &= ~BRDCFG4_USBOSC_MASK;
603 brdcfg4 |= BRDCFG4_SPI;
604 QIXIS_WRITE(brdcfg[4], brdcfg4);
606 brdcfg5 = QIXIS_READ(brdcfg[5]);
607 brdcfg5 &= ~BRDCFG5_SPR_MASK;
608 brdcfg5 |= BRDCFG5_SPI_ON_BOARD;
609 QIXIS_WRITE(brdcfg[5], brdcfg5);
610 } else if (hwconfig("dspi-off-board")) {
611 brdcfg4 = QIXIS_READ(brdcfg[4]);
612 brdcfg4 &= ~BRDCFG4_USBOSC_MASK;
613 brdcfg4 |= BRDCFG4_SPI;
614 QIXIS_WRITE(brdcfg[4], brdcfg4);
616 brdcfg5 = QIXIS_READ(brdcfg[5]);
617 brdcfg5 &= ~BRDCFG5_SPR_MASK;
618 brdcfg5 |= BRDCFG5_SPI_OFF_BOARD;
619 QIXIS_WRITE(brdcfg[5], brdcfg5);
627 int i2c_multiplexer_select_vid_channel(u8 channel)
629 return select_i2c_ch_pca9547(channel);
632 #ifdef CONFIG_TARGET_LS1088AQDS
633 /* read the current value(SVDD) of the LTM Regulator Voltage */
634 int get_serdes_volt(void)
637 u8 chan = PWM_CHANNEL0;
639 /* Select the PAGE 0 using PMBus commands PAGE for VDD */
640 #ifndef CONFIG_DM_I2C
641 ret = i2c_write(I2C_SVDD_MONITOR_ADDR,
642 PMBUS_CMD_PAGE, 1, &chan, 1);
646 ret = i2c_get_chip_for_busnum(0, I2C_SVDD_MONITOR_ADDR, 1, &dev);
648 ret = dm_i2c_write(dev, PMBUS_CMD_PAGE,
653 printf("VID: failed to select VDD Page 0\n");
657 /* Read the output voltage using PMBus command READ_VOUT */
658 #ifndef CONFIG_DM_I2C
659 ret = i2c_read(I2C_SVDD_MONITOR_ADDR,
660 PMBUS_CMD_READ_VOUT, 1, (void *)&vcode, 2);
662 dm_i2c_read(dev, PMBUS_CMD_READ_VOUT, (void *)&vcode, 2);
665 printf("VID: failed to read the volatge\n");
672 int set_serdes_volt(int svdd)
675 u8 buff[5] = {0x04, PWM_CHANNEL0, PMBUS_CMD_VOUT_COMMAND,
676 svdd & 0xFF, (svdd & 0xFF00) >> 8};
678 /* Write the desired voltage code to the SVDD regulator */
679 #ifndef CONFIG_DM_I2C
680 ret = i2c_write(I2C_SVDD_MONITOR_ADDR,
681 PMBUS_CMD_PAGE_PLUS_WRITE, 1, (void *)&buff, 5);
685 ret = i2c_get_chip_for_busnum(0, I2C_SVDD_MONITOR_ADDR, 1, &dev);
687 ret = dm_i2c_write(dev, PMBUS_CMD_PAGE_PLUS_WRITE,
691 printf("VID: I2C failed to write to the volatge regulator\n");
695 /* Wait for the volatge to get to the desired value */
697 vdd_last = get_serdes_volt();
699 printf("VID: Couldn't read sensor abort VID adjust\n");
702 } while (vdd_last != svdd);
707 int get_serdes_volt(void)
712 int set_serdes_volt(int svdd)
717 printf("SVDD changing of RDB\n");
719 /* Read the BRDCFG54 via CLPD */
720 #ifndef CONFIG_DM_I2C
721 ret = i2c_read(CONFIG_SYS_I2C_FPGA_ADDR,
722 QIXIS_BRDCFG4_OFFSET, 1, (void *)&brdcfg4, 1);
726 ret = i2c_get_chip_for_busnum(0, CONFIG_SYS_I2C_FPGA_ADDR, 1, &dev);
728 ret = dm_i2c_read(dev, QIXIS_BRDCFG4_OFFSET,
729 (void *)&brdcfg4, 1);
733 printf("VID: I2C failed to read the CPLD BRDCFG4\n");
737 brdcfg4 = brdcfg4 | 0x08;
739 /* Write to the BRDCFG4 */
740 #ifndef CONFIG_DM_I2C
741 ret = i2c_write(CONFIG_SYS_I2C_FPGA_ADDR,
742 QIXIS_BRDCFG4_OFFSET, 1, (void *)&brdcfg4, 1);
744 ret = dm_i2c_write(dev, QIXIS_BRDCFG4_OFFSET,
745 (void *)&brdcfg4, 1);
749 debug("VID: I2C failed to set the SVDD CPLD BRDCFG4\n");
753 /* Wait for the volatge to get to the desired value */
760 /* this function disables the SERDES, changes the SVDD Voltage and enables it*/
761 int board_adjust_vdd(int vdd)
765 debug("%s: vdd = %d\n", __func__, vdd);
767 /* Special settings to be performed when voltage is 900mV */
769 ret = setup_serdes_volt(vdd);
779 #if !defined(CONFIG_SPL_BUILD)
782 init_final_memctl_regs();
783 #if defined(CONFIG_TARGET_LS1088ARDB) && defined(CONFIG_FSL_MC_ENET)
784 u32 __iomem *irq_ccsr = (u32 __iomem *)ISC_BASE;
787 select_i2c_ch_pca9547(I2C_MUX_CH_DEFAULT);
788 board_retimer_init();
790 #ifdef CONFIG_ENV_IS_NOWHERE
791 gd->env_addr = (ulong)&default_environment[0];
794 #if defined(CONFIG_TARGET_LS1088ARDB) && defined(CONFIG_FSL_MC_ENET)
795 /* invert AQR105 IRQ pins polarity */
796 out_le32(irq_ccsr + IRQCR_OFFSET / 4, AQR105_IRQ_MASK);
799 #ifdef CONFIG_FSL_CAAM
802 #ifdef CONFIG_FSL_LS_PPA
806 #if !defined(CONFIG_SYS_EARLY_PCI_INIT) && defined(CONFIG_DM_ETH)
813 void detail_board_ddr_info(void)
816 print_size(gd->bd->bi_dram[0].size + gd->bd->bi_dram[1].size, "");
820 #ifdef CONFIG_FSL_MC_ENET
821 void board_quiesce_devices(void)
823 fsl_mc_ldpaa_exit(gd->bd);
826 void fdt_fixup_board_enet(void *fdt)
830 offset = fdt_path_offset(fdt, "/fsl-mc");
833 offset = fdt_path_offset(fdt, "/soc/fsl-mc");
836 printf("%s: ERROR: fsl-mc node not found in device tree (error %d)\n",
841 if (get_mc_boot_status() == 0 &&
842 (is_lazy_dpl_addr_valid() || get_dpl_apply_status() == 0))
843 fdt_status_okay(fdt, offset);
845 fdt_status_fail(fdt, offset);
849 #ifdef CONFIG_OF_BOARD_SETUP
850 void fsl_fdt_fixup_flash(void *fdt)
853 #ifdef CONFIG_TFABOOT
854 u32 __iomem *dcfg_ccsr = (u32 __iomem *)DCFG_BASE;
859 * IFC-NOR and QSPI are muxed on SoC.
860 * So disable IFC node in dts if QSPI is enabled or
861 * disable QSPI node in dts in case QSPI is not enabled.
864 #ifdef CONFIG_TFABOOT
865 enum boot_src src = get_boot_src();
866 bool disable_ifc = false;
869 case BOOT_SOURCE_IFC_NOR:
872 case BOOT_SOURCE_QSPI_NOR:
876 val = in_le32(dcfg_ccsr + DCFG_RCWSR15 / 4);
877 if (DCFG_RCWSR15_IFCGRPABASE_QSPI == (val & (u32)0x3))
883 offset = fdt_path_offset(fdt, "/soc/ifc/nor");
886 offset = fdt_path_offset(fdt, "/ifc/nor");
888 offset = fdt_path_offset(fdt, "/soc/quadspi");
891 offset = fdt_path_offset(fdt, "/quadspi");
895 #ifdef CONFIG_FSL_QSPI
896 offset = fdt_path_offset(fdt, "/soc/ifc/nor");
899 offset = fdt_path_offset(fdt, "/ifc/nor");
901 offset = fdt_path_offset(fdt, "/soc/quadspi");
904 offset = fdt_path_offset(fdt, "/quadspi");
910 fdt_status_disabled(fdt, offset);
913 int ft_board_setup(void *blob, bd_t *bd)
916 u16 mc_memory_bank = 0;
920 u64 mc_memory_base = 0;
921 u64 mc_memory_size = 0;
922 u16 total_memory_banks;
924 ft_cpu_setup(blob, bd);
926 fdt_fixup_mc_ddr(&mc_memory_base, &mc_memory_size);
928 if (mc_memory_base != 0)
931 total_memory_banks = CONFIG_NR_DRAM_BANKS + mc_memory_bank;
933 base = calloc(total_memory_banks, sizeof(u64));
934 size = calloc(total_memory_banks, sizeof(u64));
936 /* fixup DT for the two GPP DDR banks */
937 for (i = 0; i < CONFIG_NR_DRAM_BANKS; i++) {
938 base[i] = gd->bd->bi_dram[i].start;
939 size[i] = gd->bd->bi_dram[i].size;
942 #ifdef CONFIG_RESV_RAM
943 /* reduce size if reserved memory is within this bank */
944 if (gd->arch.resv_ram >= base[0] &&
945 gd->arch.resv_ram < base[0] + size[0])
946 size[0] = gd->arch.resv_ram - base[0];
947 else if (gd->arch.resv_ram >= base[1] &&
948 gd->arch.resv_ram < base[1] + size[1])
949 size[1] = gd->arch.resv_ram - base[1];
952 if (mc_memory_base != 0) {
953 for (i = 0; i <= total_memory_banks; i++) {
954 if (base[i] == 0 && size[i] == 0) {
955 base[i] = mc_memory_base;
956 size[i] = mc_memory_size;
962 fdt_fixup_memory_banks(blob, base, size, total_memory_banks);
964 fdt_fsl_mc_fixup_iommu_map_entry(blob);
966 fsl_fdt_fixup_flash(blob);
968 #ifdef CONFIG_FSL_MC_ENET
969 fdt_fixup_board_enet(blob);
972 fdt_fixup_icid(blob);
975 fixup_ls1088ardb_pb_banner(blob);
980 #endif /* defined(CONFIG_SPL_BUILD) */
982 #ifdef CONFIG_TFABOOT
983 #ifdef CONFIG_MTD_NOR_FLASH
984 int is_flash_available(void)
986 char *env_hwconfig = env_get("hwconfig");
987 enum boot_src src = get_boot_src();
988 int is_nor_flash_available = 1;
991 case BOOT_SOURCE_IFC_NOR:
992 is_nor_flash_available = 1;
994 case BOOT_SOURCE_QSPI_NOR:
995 is_nor_flash_available = 0;
998 * In Case of SD boot,if qspi is defined in env_hwconfig
999 * disable nor flash probe.
1002 if (hwconfig_f("qspi", env_hwconfig))
1003 is_nor_flash_available = 0;
1006 return is_nor_flash_available;
1010 #ifdef CONFIG_ENV_IS_IN_SPI_FLASH
1011 void *env_sf_get_env_addr(void)
1013 return (void *)(CONFIG_SYS_FSL_QSPI_BASE + CONFIG_ENV_OFFSET);