board/freescale/ls1088a/ls1088a.c

   1 // SPDX-License-Identifier: GPL-2.0+
   2 /*
   3  * Copyright 2017-2018 NXP
   4  */
   5 #include <common.h>
   6 #include <env.h>
   7 #include <i2c.h>
   8 #include <init.h>
   9 #include <malloc.h>
  10 #include <errno.h>
  11 #include <netdev.h>
  12 #include <fsl_ifc.h>
  13 #include <fsl_ddr.h>
  14 #include <fsl_sec.h>
  15 #include <asm/io.h>
  16 #include <fdt_support.h>
  17 #include <linux/libfdt.h>
  18 #include <fsl-mc/fsl_mc.h>
  19 #include <env_internal.h>
  20 #include <asm/arch-fsl-layerscape/soc.h>
  21 #include <asm/arch/ppa.h>
  22 #include <hwconfig.h>
  23 #include <asm/arch/fsl_serdes.h>
  24 #include <asm/arch/soc.h>
  25 #include <asm/arch-fsl-layerscape/fsl_icid.h>
  26
  27 #include "../common/qixis.h"
  28 #include "ls1088a_qixis.h"
  29 #include "../common/vid.h"
  30 #include <fsl_immap.h>
  31
  32 DECLARE_GLOBAL_DATA_PTR;
  33
  34 #ifdef CONFIG_TARGET_LS1088AQDS
  35 #ifdef CONFIG_TFABOOT
  36 struct ifc_regs ifc_cfg_ifc_nor_boot[CONFIG_SYS_FSL_IFC_BANK_COUNT] = {
  37         {
  38                 "nor0",
  39                 CONFIG_SYS_NOR0_CSPR_EARLY,
  40                 CONFIG_SYS_NOR0_CSPR_EXT,
  41                 CONFIG_SYS_NOR_AMASK,
  42                 CONFIG_SYS_NOR_CSOR,
  43                 {
  44                         CONFIG_SYS_NOR_FTIM0,
  45                         CONFIG_SYS_NOR_FTIM1,
  46                         CONFIG_SYS_NOR_FTIM2,
  47                         CONFIG_SYS_NOR_FTIM3
  48                 },
  49                 0,
  50                 CONFIG_SYS_NOR0_CSPR,
  51                 0,
  52         },
  53         {
  54                 "nor1",
  55                 CONFIG_SYS_NOR1_CSPR_EARLY,
  56                 CONFIG_SYS_NOR0_CSPR_EXT,
  57                 CONFIG_SYS_NOR_AMASK_EARLY,
  58                 CONFIG_SYS_NOR_CSOR,
  59                 {
  60                         CONFIG_SYS_NOR_FTIM0,
  61                         CONFIG_SYS_NOR_FTIM1,
  62                         CONFIG_SYS_NOR_FTIM2,
  63                         CONFIG_SYS_NOR_FTIM3
  64                 },
  65                 0,
  66                 CONFIG_SYS_NOR1_CSPR,
  67                 CONFIG_SYS_NOR_AMASK,
  68         },
  69         {
  70                 "nand",
  71                 CONFIG_SYS_NAND_CSPR,
  72                 CONFIG_SYS_NAND_CSPR_EXT,
  73                 CONFIG_SYS_NAND_AMASK,
  74                 CONFIG_SYS_NAND_CSOR,
  75                 {
  76                         CONFIG_SYS_NAND_FTIM0,
  77                         CONFIG_SYS_NAND_FTIM1,
  78                         CONFIG_SYS_NAND_FTIM2,
  79                         CONFIG_SYS_NAND_FTIM3
  80                 },
  81         },
  82         {
  83                 "fpga",
  84                 CONFIG_SYS_FPGA_CSPR,
  85                 CONFIG_SYS_FPGA_CSPR_EXT,
  86                 SYS_FPGA_AMASK,
  87                 CONFIG_SYS_FPGA_CSOR,
  88                 {
  89                         SYS_FPGA_CS_FTIM0,
  90                         SYS_FPGA_CS_FTIM1,
  91                         SYS_FPGA_CS_FTIM2,
  92                         SYS_FPGA_CS_FTIM3
  93                 },
  94                 0,
  95                 SYS_FPGA_CSPR_FINAL,
  96                 0,
  97         }
  98 };
  99
 100 struct ifc_regs ifc_cfg_qspi_nor_boot[CONFIG_SYS_FSL_IFC_BANK_COUNT] = {
 101         {
 102                 "nand",
 103                 CONFIG_SYS_NAND_CSPR,
 104                 CONFIG_SYS_NAND_CSPR_EXT,
 105                 CONFIG_SYS_NAND_AMASK,
 106                 CONFIG_SYS_NAND_CSOR,
 107                 {
 108                         CONFIG_SYS_NAND_FTIM0,
 109                         CONFIG_SYS_NAND_FTIM1,
 110                         CONFIG_SYS_NAND_FTIM2,
 111                         CONFIG_SYS_NAND_FTIM3
 112                 },
 113         },
 114         {
 115                 "reserved",
 116         },
 117         {
 118                 "fpga",
 119                 CONFIG_SYS_FPGA_CSPR,
 120                 CONFIG_SYS_FPGA_CSPR_EXT,
 121                 SYS_FPGA_AMASK,
 122                 CONFIG_SYS_FPGA_CSOR,
 123                 {
 124                         SYS_FPGA_CS_FTIM0,
 125                         SYS_FPGA_CS_FTIM1,
 126                         SYS_FPGA_CS_FTIM2,
 127                         SYS_FPGA_CS_FTIM3
 128                 },
 129                 0,
 130                 SYS_FPGA_CSPR_FINAL,
 131                 0,
 132         }
 133 };
 134
 135 void ifc_cfg_boot_info(struct ifc_regs_info *regs_info)
 136 {
 137         enum boot_src src = get_boot_src();
 138
 139         if (src == BOOT_SOURCE_QSPI_NOR)
 140                 regs_info->regs = ifc_cfg_qspi_nor_boot;
 141         else
 142                 regs_info->regs = ifc_cfg_ifc_nor_boot;
 143
 144         regs_info->cs_size = CONFIG_SYS_FSL_IFC_BANK_COUNT;
 145 }
 146 #endif /* CONFIG_TFABOOT */
 147 #endif /* CONFIG_TARGET_LS1088AQDS */
 148
 149 int board_early_init_f(void)
 150 {
 151 #if defined(CONFIG_SYS_I2C_EARLY_INIT) && defined(CONFIG_TARGET_LS1088AQDS)
 152         i2c_early_init_f();
 153 #endif
 154         fsl_lsch3_early_init_f();
 155         return 0;
 156 }
 157
 158 #ifdef CONFIG_FSL_QIXIS
 159 unsigned long long get_qixis_addr(void)
 160 {
 161         unsigned long long addr;
 162
 163         if (gd->flags & GD_FLG_RELOC)
 164                 addr = QIXIS_BASE_PHYS;
 165         else
 166                 addr = QIXIS_BASE_PHYS_EARLY;
 167
 168         /*
 169          * IFC address under 256MB is mapped to 0x30000000, any address above
 170          * is mapped to 0x5_10000000 up to 4GB.
 171          */
 172         addr = addr  > 0x10000000 ? addr + 0x500000000ULL : addr + 0x30000000;
 173
 174         return addr;
 175 }
 176 #endif
 177
 178 #if defined(CONFIG_VID)
 179 int init_func_vid(void)
 180 {
 181         if (adjust_vdd(0) < 0)
 182                 printf("core voltage not adjusted\n");
 183
 184         return 0;
 185 }
 186 #endif
 187
 188 int is_pb_board(void)
 189 {
 190         u8 board_id;
 191
 192         board_id = QIXIS_READ(id);
 193         if (board_id == LS1088ARDB_PB_BOARD)
 194                 return 1;
 195         else
 196                 return 0;
 197 }
 198
 199 int fixup_ls1088ardb_pb_banner(void *fdt)
 200 {
 201         fdt_setprop_string(fdt, 0, "model", "LS1088ARDB-PB Board");
 202
 203         return 0;
 204 }
 205
 206 #if !defined(CONFIG_SPL_BUILD)
 207 int checkboard(void)
 208 {
 209 #ifdef CONFIG_TFABOOT
 210         enum boot_src src = get_boot_src();
 211 #endif
 212         char buf[64];
 213         u8 sw;
 214         static const char *const freq[] = {"100", "125", "156.25",
 215                                             "100 separate SSCG"};
 216         int clock;
 217
 218 #ifdef CONFIG_TARGET_LS1088AQDS
 219         printf("Board: LS1088A-QDS, ");
 220 #else
 221         if (is_pb_board())
 222                 printf("Board: LS1088ARDB-PB, ");
 223         else
 224                 printf("Board: LS1088A-RDB, ");
 225 #endif
 226
 227         sw = QIXIS_READ(arch);
 228         printf("Board Arch: V%d, ", sw >> 4);
 229
 230 #ifdef CONFIG_TARGET_LS1088AQDS
 231         printf("Board version: %c, boot from ", (sw & 0xf) + 'A' - 1);
 232 #else
 233         printf("Board version: %c, boot from ", (sw & 0xf) + 'A');
 234 #endif
 235
 236         memset((u8 *)buf, 0x00, ARRAY_SIZE(buf));
 237
 238         sw = QIXIS_READ(brdcfg[0]);
 239         sw = (sw & QIXIS_LBMAP_MASK) >> QIXIS_LBMAP_SHIFT;
 240
 241 #ifdef CONFIG_TFABOOT
 242         if (src == BOOT_SOURCE_SD_MMC)
 243                 puts("SD card\n");
 244 #else
 245 #ifdef CONFIG_SD_BOOT
 246         puts("SD card\n");
 247 #endif
 248 #endif /* CONFIG_TFABOOT */
 249         switch (sw) {
 250 #ifdef CONFIG_TARGET_LS1088AQDS
 251         case 0:
 252         case 1:
 253         case 2:
 254         case 3:
 255         case 4:
 256         case 5:
 257         case 6:
 258         case 7:
 259                 printf("vBank: %d\n", sw);
 260                 break;
 261         case 8:
 262                 puts("PromJet\n");
 263                 break;
 264         case 15:
 265                 puts("IFCCard\n");
 266                 break;
 267         case 14:
 268 #else
 269         case 0:
 270 #endif
 271                 puts("QSPI:");
 272                 sw = QIXIS_READ(brdcfg[0]);
 273                 sw = (sw & QIXIS_QMAP_MASK) >> QIXIS_QMAP_SHIFT;
 274                 if (sw == 0 || sw == 4)
 275                         puts("0\n");
 276                 else if (sw == 1)
 277                         puts("1\n");
 278                 else
 279                         puts("EMU\n");
 280                 break;
 281
 282         default:
 283                 printf("invalid setting of SW%u\n", QIXIS_LBMAP_SWITCH);
 284                 break;
 285         }
 286
 287 #ifdef CONFIG_TARGET_LS1088AQDS
 288         printf("FPGA: v%d (%s), build %d",
 289                (int)QIXIS_READ(scver), qixis_read_tag(buf),
 290                (int)qixis_read_minor());
 291         /* the timestamp string contains "\n" at the end */
 292         printf(" on %s", qixis_read_time(buf));
 293 #else
 294         printf("CPLD: v%d.%d\n", QIXIS_READ(scver), QIXIS_READ(tagdata));
 295 #endif
 296
 297         /*
 298          * Display the actual SERDES reference clocks as configured by the
 299          * dip switches on the board.  Note that the SWx registers could
 300          * technically be set to force the reference clocks to match the
 301          * values that the SERDES expects (or vice versa).  For now, however,
 302          * we just display both values and hope the user notices when they
 303          * don't match.
 304          */
 305         puts("SERDES1 Reference : ");
 306         sw = QIXIS_READ(brdcfg[2]);
 307         clock = (sw >> 6) & 3;
 308         printf("Clock1 = %sMHz ", freq[clock]);
 309         clock = (sw >> 4) & 3;
 310         printf("Clock2 = %sMHz", freq[clock]);
 311
 312         puts("\nSERDES2 Reference : ");
 313         clock = (sw >> 2) & 3;
 314         printf("Clock1 = %sMHz ", freq[clock]);
 315         clock = (sw >> 0) & 3;
 316         printf("Clock2 = %sMHz\n", freq[clock]);
 317
 318         return 0;
 319 }
 320 #endif
 321
 322 bool if_board_diff_clk(void)
 323 {
 324 #ifdef CONFIG_TARGET_LS1088AQDS
 325         u8 diff_conf = QIXIS_READ(brdcfg[11]);
 326         return diff_conf & 0x40;
 327 #else
 328         u8 diff_conf = QIXIS_READ(dutcfg[11]);
 329         return diff_conf & 0x80;
 330 #endif
 331 }
 332
 333 unsigned long get_board_sys_clk(void)
 334 {
 335         u8 sysclk_conf = QIXIS_READ(brdcfg[1]);
 336
 337         switch (sysclk_conf & 0x0f) {
 338         case QIXIS_SYSCLK_83:
 339                 return 83333333;
 340         case QIXIS_SYSCLK_100:
 341                 return 100000000;
 342         case QIXIS_SYSCLK_125:
 343                 return 125000000;
 344         case QIXIS_SYSCLK_133:
 345                 return 133333333;
 346         case QIXIS_SYSCLK_150:
 347                 return 150000000;
 348         case QIXIS_SYSCLK_160:
 349                 return 160000000;
 350         case QIXIS_SYSCLK_166:
 351                 return 166666666;
 352         }
 353
 354         return 66666666;
 355 }
 356
 357 unsigned long get_board_ddr_clk(void)
 358 {
 359         u8 ddrclk_conf = QIXIS_READ(brdcfg[1]);
 360
 361         if (if_board_diff_clk())
 362                 return get_board_sys_clk();
 363         switch ((ddrclk_conf & 0x30) >> 4) {
 364         case QIXIS_DDRCLK_100:
 365                 return 100000000;
 366         case QIXIS_DDRCLK_125:
 367                 return 125000000;
 368         case QIXIS_DDRCLK_133:
 369                 return 133333333;
 370         }
 371
 372         return 66666666;
 373 }
 374
 375 int select_i2c_ch_pca9547(u8 ch)
 376 {
 377         int ret;
 378
 379 #ifndef CONFIG_DM_I2C
 380         ret = i2c_write(I2C_MUX_PCA_ADDR_PRI, 0, 1, &ch, 1);
 381 #else
 382         struct udevice *dev;
 383
 384         ret = i2c_get_chip_for_busnum(0, I2C_MUX_PCA_ADDR_PRI, 1, &dev);
 385         if (!ret)
 386                 ret = dm_i2c_write(dev, 0, &ch, 1);
 387 #endif
 388         if (ret) {
 389                 puts("PCA: failed to select proper channel\n");
 390                 return ret;
 391         }
 392
 393         return 0;
 394 }
 395
 396 #if !defined(CONFIG_SPL_BUILD)
 397 void board_retimer_init(void)
 398 {
 399         u8 reg;
 400
 401         /* Retimer is connected to I2C1_CH5 */
 402         select_i2c_ch_pca9547(I2C_MUX_CH5);
 403
 404         /* Access to Control/Shared register */
 405         reg = 0x0;
 406 #ifndef CONFIG_DM_I2C
 407         i2c_write(I2C_RETIMER_ADDR, 0xff, 1, &reg, 1);
 408 #else
 409         struct udevice *dev;
 410
 411         i2c_get_chip_for_busnum(0, I2C_RETIMER_ADDR, 1, &dev);
 412         dm_i2c_write(dev, 0xff, &reg, 1);
 413 #endif
 414
 415         /* Read device revision and ID */
 416 #ifndef CONFIG_DM_I2C
 417         i2c_read(I2C_RETIMER_ADDR, 1, 1, &reg, 1);
 418 #else
 419         dm_i2c_read(dev, 1, &reg, 1);
 420 #endif
 421         debug("Retimer version id = 0x%x\n", reg);
 422
 423         /* Enable Broadcast. All writes target all channel register sets */
 424         reg = 0x0c;
 425 #ifndef CONFIG_DM_I2C
 426         i2c_write(I2C_RETIMER_ADDR, 0xff, 1, &reg, 1);
 427 #else
 428         dm_i2c_write(dev, 0xff, &reg, 1);
 429 #endif
 430
 431         /* Reset Channel Registers */
 432 #ifndef CONFIG_DM_I2C
 433         i2c_read(I2C_RETIMER_ADDR, 0, 1, &reg, 1);
 434 #else
 435         dm_i2c_read(dev, 0, &reg, 1);
 436 #endif
 437         reg |= 0x4;
 438 #ifndef CONFIG_DM_I2C
 439         i2c_write(I2C_RETIMER_ADDR, 0, 1, &reg, 1);
 440 #else
 441         dm_i2c_write(dev, 0, &reg, 1);
 442 #endif
 443
 444         /* Set data rate as 10.3125 Gbps */
 445         reg = 0x90;
 446 #ifndef CONFIG_DM_I2C
 447         i2c_write(I2C_RETIMER_ADDR, 0x60, 1, &reg, 1);
 448 #else
 449         dm_i2c_write(dev, 0x60, &reg, 1);
 450 #endif
 451         reg = 0xb3;
 452 #ifndef CONFIG_DM_I2C
 453         i2c_write(I2C_RETIMER_ADDR, 0x61, 1, &reg, 1);
 454 #else
 455         dm_i2c_write(dev, 0x61, &reg, 1);
 456 #endif
 457         reg = 0x90;
 458 #ifndef CONFIG_DM_I2C
 459         i2c_write(I2C_RETIMER_ADDR, 0x62, 1, &reg, 1);
 460 #else
 461         dm_i2c_write(dev, 0x62, &reg, 1);
 462 #endif
 463         reg = 0xb3;
 464 #ifndef CONFIG_DM_I2C
 465         i2c_write(I2C_RETIMER_ADDR, 0x63, 1, &reg, 1);
 466 #else
 467         dm_i2c_write(dev, 0x63, &reg, 1);
 468 #endif
 469         reg = 0xcd;
 470 #ifndef CONFIG_DM_I2C
 471         i2c_write(I2C_RETIMER_ADDR, 0x64, 1, &reg, 1);
 472 #else
 473         dm_i2c_write(dev, 0x64, &reg, 1);
 474 #endif
 475
 476         /* Select VCO Divider to full rate (000) */
 477 #ifndef CONFIG_DM_I2C
 478         i2c_read(I2C_RETIMER_ADDR, 0x2F, 1, &reg, 1);
 479 #else
 480         dm_i2c_read(dev, 0x2F, &reg, 1);
 481 #endif
 482         reg &= 0x0f;
 483         reg |= 0x70;
 484 #ifndef CONFIG_DM_I2C
 485         i2c_write(I2C_RETIMER_ADDR, 0x2F, 1, &reg, 1);
 486 #else
 487         dm_i2c_write(dev, 0x2F, &reg, 1);
 488 #endif
 489
 490 #ifdef  CONFIG_TARGET_LS1088AQDS
 491         /* Retimer is connected to I2C1_CH5 */
 492         select_i2c_ch_pca9547(I2C_MUX_CH5);
 493
 494         /* Access to Control/Shared register */
 495         reg = 0x0;
 496 #ifndef CONFIG_DM_I2C
 497         i2c_write(I2C_RETIMER_ADDR2, 0xff, 1, &reg, 1);
 498 #else
 499         i2c_get_chip_for_busnum(0, I2C_RETIMER_ADDR2, 1, &dev);
 500         dm_i2c_write(dev, 0xff, &reg, 1);
 501 #endif
 502
 503         /* Read device revision and ID */
 504 #ifndef CONFIG_DM_I2C
 505         i2c_read(I2C_RETIMER_ADDR2, 1, 1, &reg, 1);
 506 #else
 507         dm_i2c_read(dev, 1, &reg, 1);
 508 #endif
 509         debug("Retimer version id = 0x%x\n", reg);
 510
 511         /* Enable Broadcast. All writes target all channel register sets */
 512         reg = 0x0c;
 513 #ifndef CONFIG_DM_I2C
 514         i2c_write(I2C_RETIMER_ADDR2, 0xff, 1, &reg, 1);
 515 #else
 516         dm_i2c_write(dev, 0xff, &reg, 1);
 517 #endif
 518
 519         /* Reset Channel Registers */
 520 #ifndef CONFIG_DM_I2C
 521         i2c_read(I2C_RETIMER_ADDR2, 0, 1, &reg, 1);
 522 #else
 523         dm_i2c_read(dev, 0, &reg, 1);
 524 #endif
 525         reg |= 0x4;
 526 #ifndef CONFIG_DM_I2C
 527         i2c_write(I2C_RETIMER_ADDR2, 0, 1, &reg, 1);
 528 #else
 529         dm_i2c_write(dev, 0, &reg, 1);
 530 #endif
 531
 532         /* Set data rate as 10.3125 Gbps */
 533         reg = 0x90;
 534 #ifndef CONFIG_DM_I2C
 535         i2c_write(I2C_RETIMER_ADDR2, 0x60, 1, &reg, 1);
 536 #else
 537         dm_i2c_write(dev, 0x60, &reg, 1);
 538 #endif
 539         reg = 0xb3;
 540 #ifndef CONFIG_DM_I2C
 541         i2c_write(I2C_RETIMER_ADDR2, 0x61, 1, &reg, 1);
 542 #else
 543         dm_i2c_write(dev, 0x61, &reg, 1);
 544 #endif
 545         reg = 0x90;
 546 #ifndef CONFIG_DM_I2C
 547         i2c_write(I2C_RETIMER_ADDR2, 0x62, 1, &reg, 1);
 548 #else
 549         dm_i2c_write(dev, 0x62, &reg, 1);
 550 #endif
 551         reg = 0xb3;
 552 #ifndef CONFIG_DM_I2C
 553         i2c_write(I2C_RETIMER_ADDR2, 0x63, 1, &reg, 1);
 554 #else
 555         dm_i2c_write(dev, 0x63, &reg, 1);
 556 #endif
 557         reg = 0xcd;
 558 #ifndef CONFIG_DM_I2C
 559         i2c_write(I2C_RETIMER_ADDR2, 0x64, 1, &reg, 1);
 560 #else
 561         dm_i2c_write(dev, 0x64, &reg, 1);
 562 #endif
 563
 564         /* Select VCO Divider to full rate (000) */
 565 #ifndef CONFIG_DM_I2C
 566         i2c_read(I2C_RETIMER_ADDR2, 0x2F, 1, &reg, 1);
 567 #else
 568         dm_i2c_read(dev, 0x2F, &reg, 1);
 569 #endif
 570         reg &= 0x0f;
 571         reg |= 0x70;
 572 #ifndef CONFIG_DM_I2C
 573         i2c_write(I2C_RETIMER_ADDR2, 0x2F, 1, &reg, 1);
 574 #else
 575         dm_i2c_write(dev, 0x2F, &reg, 1);
 576 #endif
 577
 578 #endif
 579         /*return the default channel*/
 580         select_i2c_ch_pca9547(I2C_MUX_CH_DEFAULT);
 581 }
 582
 583 #ifdef CONFIG_MISC_INIT_R
 584 int misc_init_r(void)
 585 {
 586 #ifdef CONFIG_TARGET_LS1088ARDB
 587         u8 brdcfg5;
 588
 589         if (hwconfig("esdhc-force-sd")) {
 590                 brdcfg5 = QIXIS_READ(brdcfg[5]);
 591                 brdcfg5 &= ~BRDCFG5_SPISDHC_MASK;
 592                 brdcfg5 |= BRDCFG5_FORCE_SD;
 593                 QIXIS_WRITE(brdcfg[5], brdcfg5);
 594         }
 595 #endif
 596
 597 #ifdef CONFIG_TARGET_LS1088AQDS
 598          u8 brdcfg4, brdcfg5;
 599
 600         if (hwconfig("dspi-on-board")) {
 601                 brdcfg4 = QIXIS_READ(brdcfg[4]);
 602                 brdcfg4 &= ~BRDCFG4_USBOSC_MASK;
 603                 brdcfg4 |= BRDCFG4_SPI;
 604                 QIXIS_WRITE(brdcfg[4], brdcfg4);
 605
 606                 brdcfg5 = QIXIS_READ(brdcfg[5]);
 607                 brdcfg5 &= ~BRDCFG5_SPR_MASK;
 608                 brdcfg5 |= BRDCFG5_SPI_ON_BOARD;
 609                 QIXIS_WRITE(brdcfg[5], brdcfg5);
 610         } else if (hwconfig("dspi-off-board")) {
 611                 brdcfg4 = QIXIS_READ(brdcfg[4]);
 612                 brdcfg4 &= ~BRDCFG4_USBOSC_MASK;
 613                 brdcfg4 |= BRDCFG4_SPI;
 614                 QIXIS_WRITE(brdcfg[4], brdcfg4);
 615
 616                 brdcfg5 = QIXIS_READ(brdcfg[5]);
 617                 brdcfg5 &= ~BRDCFG5_SPR_MASK;
 618                 brdcfg5 |= BRDCFG5_SPI_OFF_BOARD;
 619                 QIXIS_WRITE(brdcfg[5], brdcfg5);
 620         }
 621 #endif
 622         return 0;
 623 }
 624 #endif
 625 #endif
 626
 627 int i2c_multiplexer_select_vid_channel(u8 channel)
 628 {
 629         return select_i2c_ch_pca9547(channel);
 630 }
 631
 632 #ifdef CONFIG_TARGET_LS1088AQDS
 633 /* read the current value(SVDD) of the LTM Regulator Voltage */
 634 int get_serdes_volt(void)
 635 {
 636         int  ret, vcode = 0;
 637         u8 chan = PWM_CHANNEL0;
 638
 639         /* Select the PAGE 0 using PMBus commands PAGE for VDD */
 640 #ifndef CONFIG_DM_I2C
 641         ret = i2c_write(I2C_SVDD_MONITOR_ADDR,
 642                         PMBUS_CMD_PAGE, 1, &chan, 1);
 643 #else
 644         struct udevice *dev;
 645
 646         ret = i2c_get_chip_for_busnum(0, I2C_SVDD_MONITOR_ADDR, 1, &dev);
 647         if (!ret)
 648                 ret = dm_i2c_write(dev, PMBUS_CMD_PAGE,
 649                                    &chan, 1);
 650 #endif
 651
 652         if (ret) {
 653                 printf("VID: failed to select VDD Page 0\n");
 654                 return ret;
 655         }
 656
 657         /* Read the output voltage using PMBus command READ_VOUT */
 658 #ifndef CONFIG_DM_I2C
 659         ret = i2c_read(I2C_SVDD_MONITOR_ADDR,
 660                        PMBUS_CMD_READ_VOUT, 1, (void *)&vcode, 2);
 661 #else
 662         dm_i2c_read(dev, PMBUS_CMD_READ_VOUT, (void *)&vcode, 2);
 663 #endif
 664         if (ret) {
 665                 printf("VID: failed to read the volatge\n");
 666                 return ret;
 667         }
 668
 669         return vcode;
 670 }
 671
 672 int set_serdes_volt(int svdd)
 673 {
 674         int ret, vdd_last;
 675         u8 buff[5] = {0x04, PWM_CHANNEL0, PMBUS_CMD_VOUT_COMMAND,
 676                         svdd & 0xFF, (svdd & 0xFF00) >> 8};
 677
 678         /* Write the desired voltage code to the SVDD regulator */
 679 #ifndef CONFIG_DM_I2C
 680         ret = i2c_write(I2C_SVDD_MONITOR_ADDR,
 681                         PMBUS_CMD_PAGE_PLUS_WRITE, 1, (void *)&buff, 5);
 682 #else
 683         struct udevice *dev;
 684
 685         ret = i2c_get_chip_for_busnum(0, I2C_SVDD_MONITOR_ADDR, 1, &dev);
 686         if (!ret)
 687                 ret = dm_i2c_write(dev, PMBUS_CMD_PAGE_PLUS_WRITE,
 688                                    (void *)&buff, 5);
 689 #endif
 690         if (ret) {
 691                 printf("VID: I2C failed to write to the volatge regulator\n");
 692                 return -1;
 693         }
 694
 695         /* Wait for the volatge to get to the desired value */
 696         do {
 697                 vdd_last = get_serdes_volt();
 698                 if (vdd_last < 0) {
 699                         printf("VID: Couldn't read sensor abort VID adjust\n");
 700                         return -1;
 701                 }
 702         } while (vdd_last != svdd);
 703
 704         return 1;
 705 }
 706 #else
 707 int get_serdes_volt(void)
 708 {
 709         return 0;
 710 }
 711
 712 int set_serdes_volt(int svdd)
 713 {
 714         int ret;
 715         u8 brdcfg4;
 716
 717         printf("SVDD changing of RDB\n");
 718
 719         /* Read the BRDCFG54 via CLPD */
 720 #ifndef CONFIG_DM_I2C
 721         ret = i2c_read(CONFIG_SYS_I2C_FPGA_ADDR,
 722                        QIXIS_BRDCFG4_OFFSET, 1, (void *)&brdcfg4, 1);
 723 #else
 724         struct udevice *dev;
 725
 726         ret = i2c_get_chip_for_busnum(0, CONFIG_SYS_I2C_FPGA_ADDR, 1, &dev);
 727         if (!ret)
 728                 ret = dm_i2c_read(dev, QIXIS_BRDCFG4_OFFSET,
 729                                   (void *)&brdcfg4, 1);
 730 #endif
 731
 732         if (ret) {
 733                 printf("VID: I2C failed to read the CPLD BRDCFG4\n");
 734                 return -1;
 735         }
 736
 737         brdcfg4 = brdcfg4 | 0x08;
 738
 739         /* Write to the BRDCFG4 */
 740 #ifndef CONFIG_DM_I2C
 741         ret = i2c_write(CONFIG_SYS_I2C_FPGA_ADDR,
 742                         QIXIS_BRDCFG4_OFFSET, 1, (void *)&brdcfg4, 1);
 743 #else
 744         ret = dm_i2c_write(dev, QIXIS_BRDCFG4_OFFSET,
 745                            (void *)&brdcfg4, 1);
 746 #endif
 747
 748         if (ret) {
 749                 debug("VID: I2C failed to set the SVDD CPLD BRDCFG4\n");
 750                 return -1;
 751         }
 752
 753         /* Wait for the volatge to get to the desired value */
 754         udelay(10000);
 755
 756         return 1;
 757 }
 758 #endif
 759
 760 /* this function disables the SERDES, changes the SVDD Voltage and enables it*/
 761 int board_adjust_vdd(int vdd)
 762 {
 763         int ret = 0;
 764
 765         debug("%s: vdd = %d\n", __func__, vdd);
 766
 767         /* Special settings to be performed when voltage is 900mV */
 768         if (vdd == 900) {
 769                 ret = setup_serdes_volt(vdd);
 770                 if (ret < 0) {
 771                         ret = -1;
 772                         goto exit;
 773                 }
 774         }
 775 exit:
 776         return ret;
 777 }
 778
 779 #if !defined(CONFIG_SPL_BUILD)
 780 int board_init(void)
 781 {
 782         init_final_memctl_regs();
 783 #if defined(CONFIG_TARGET_LS1088ARDB) && defined(CONFIG_FSL_MC_ENET)
 784         u32 __iomem *irq_ccsr = (u32 __iomem *)ISC_BASE;
 785 #endif
 786
 787         select_i2c_ch_pca9547(I2C_MUX_CH_DEFAULT);
 788         board_retimer_init();
 789
 790 #ifdef CONFIG_ENV_IS_NOWHERE
 791         gd->env_addr = (ulong)&default_environment[0];
 792 #endif
 793
 794 #if defined(CONFIG_TARGET_LS1088ARDB) && defined(CONFIG_FSL_MC_ENET)
 795         /* invert AQR105 IRQ pins polarity */
 796         out_le32(irq_ccsr + IRQCR_OFFSET / 4, AQR105_IRQ_MASK);
 797 #endif
 798
 799 #ifdef CONFIG_FSL_CAAM
 800         sec_init();
 801 #endif
 802 #ifdef CONFIG_FSL_LS_PPA
 803         ppa_init();
 804 #endif
 805
 806 #if !defined(CONFIG_SYS_EARLY_PCI_INIT) && defined(CONFIG_DM_ETH)
 807         pci_init();
 808 #endif
 809
 810         return 0;
 811 }
 812
 813 void detail_board_ddr_info(void)
 814 {
 815         puts("\nDDR    ");
 816         print_size(gd->bd->bi_dram[0].size + gd->bd->bi_dram[1].size, "");
 817         print_ddr_info(0);
 818 }
 819
 820 #ifdef CONFIG_FSL_MC_ENET
 821 void board_quiesce_devices(void)
 822 {
 823         fsl_mc_ldpaa_exit(gd->bd);
 824 }
 825
 826 void fdt_fixup_board_enet(void *fdt)
 827 {
 828         int offset;
 829
 830         offset = fdt_path_offset(fdt, "/fsl-mc");
 831
 832         if (offset < 0)
 833                 offset = fdt_path_offset(fdt, "/soc/fsl-mc");
 834
 835         if (offset < 0) {
 836                 printf("%s: ERROR: fsl-mc node not found in device tree (error %d)\n",
 837                        __func__, offset);
 838                 return;
 839         }
 840
 841         if (get_mc_boot_status() == 0 &&
 842             (is_lazy_dpl_addr_valid() || get_dpl_apply_status() == 0))
 843                 fdt_status_okay(fdt, offset);
 844         else
 845                 fdt_status_fail(fdt, offset);
 846 }
 847 #endif
 848
 849 #ifdef CONFIG_OF_BOARD_SETUP
 850 void fsl_fdt_fixup_flash(void *fdt)
 851 {
 852         int offset;
 853 #ifdef CONFIG_TFABOOT
 854         u32 __iomem *dcfg_ccsr = (u32 __iomem *)DCFG_BASE;
 855         u32 val;
 856 #endif
 857
 858 /*
 859  * IFC-NOR and QSPI are muxed on SoC.
 860  * So disable IFC node in dts if QSPI is enabled or
 861  * disable QSPI node in dts in case QSPI is not enabled.
 862  */
 863
 864 #ifdef CONFIG_TFABOOT
 865         enum boot_src src = get_boot_src();
 866         bool disable_ifc = false;
 867
 868         switch (src) {
 869         case BOOT_SOURCE_IFC_NOR:
 870                 disable_ifc = false;
 871                 break;
 872         case BOOT_SOURCE_QSPI_NOR:
 873                 disable_ifc = true;
 874                 break;
 875         default:
 876                 val = in_le32(dcfg_ccsr + DCFG_RCWSR15 / 4);
 877                 if (DCFG_RCWSR15_IFCGRPABASE_QSPI == (val & (u32)0x3))
 878                         disable_ifc = true;
 879                 break;
 880         }
 881
 882         if (disable_ifc) {
 883                 offset = fdt_path_offset(fdt, "/soc/ifc/nor");
 884
 885                 if (offset < 0)
 886                         offset = fdt_path_offset(fdt, "/ifc/nor");
 887         } else {
 888                 offset = fdt_path_offset(fdt, "/soc/quadspi");
 889
 890                 if (offset < 0)
 891                         offset = fdt_path_offset(fdt, "/quadspi");
 892         }
 893
 894 #else
 895 #ifdef CONFIG_FSL_QSPI
 896         offset = fdt_path_offset(fdt, "/soc/ifc/nor");
 897
 898         if (offset < 0)
 899                 offset = fdt_path_offset(fdt, "/ifc/nor");
 900 #else
 901         offset = fdt_path_offset(fdt, "/soc/quadspi");
 902
 903         if (offset < 0)
 904                 offset = fdt_path_offset(fdt, "/quadspi");
 905 #endif
 906 #endif
 907         if (offset < 0)
 908                 return;
 909
 910         fdt_status_disabled(fdt, offset);
 911 }
 912
 913 int ft_board_setup(void *blob, bd_t *bd)
 914 {
 915         int i;
 916         u16 mc_memory_bank = 0;
 917
 918         u64 *base;
 919         u64 *size;
 920         u64 mc_memory_base = 0;
 921         u64 mc_memory_size = 0;
 922         u16 total_memory_banks;
 923
 924         ft_cpu_setup(blob, bd);
 925
 926         fdt_fixup_mc_ddr(&mc_memory_base, &mc_memory_size);
 927
 928         if (mc_memory_base != 0)
 929                 mc_memory_bank++;
 930
 931         total_memory_banks = CONFIG_NR_DRAM_BANKS + mc_memory_bank;
 932
 933         base = calloc(total_memory_banks, sizeof(u64));
 934         size = calloc(total_memory_banks, sizeof(u64));
 935
 936         /* fixup DT for the two GPP DDR banks */
 937         for (i = 0; i < CONFIG_NR_DRAM_BANKS; i++) {
 938                 base[i] = gd->bd->bi_dram[i].start;
 939                 size[i] = gd->bd->bi_dram[i].size;
 940         }
 941
 942 #ifdef CONFIG_RESV_RAM
 943         /* reduce size if reserved memory is within this bank */
 944         if (gd->arch.resv_ram >= base[0] &&
 945             gd->arch.resv_ram < base[0] + size[0])
 946                 size[0] = gd->arch.resv_ram - base[0];
 947         else if (gd->arch.resv_ram >= base[1] &&
 948                  gd->arch.resv_ram < base[1] + size[1])
 949                 size[1] = gd->arch.resv_ram - base[1];
 950 #endif
 951
 952         if (mc_memory_base != 0) {
 953                 for (i = 0; i <= total_memory_banks; i++) {
 954                         if (base[i] == 0 && size[i] == 0) {
 955                                 base[i] = mc_memory_base;
 956                                 size[i] = mc_memory_size;
 957                                 break;
 958                         }
 959                 }
 960         }
 961
 962         fdt_fixup_memory_banks(blob, base, size, total_memory_banks);
 963
 964         fdt_fsl_mc_fixup_iommu_map_entry(blob);
 965
 966         fsl_fdt_fixup_flash(blob);
 967
 968 #ifdef CONFIG_FSL_MC_ENET
 969         fdt_fixup_board_enet(blob);
 970 #endif
 971
 972         fdt_fixup_icid(blob);
 973
 974         if (is_pb_board())
 975                 fixup_ls1088ardb_pb_banner(blob);
 976
 977         return 0;
 978 }
 979 #endif
 980 #endif /* defined(CONFIG_SPL_BUILD) */
 981
 982 #ifdef CONFIG_TFABOOT
 983 #ifdef CONFIG_MTD_NOR_FLASH
 984 int is_flash_available(void)
 985 {
 986         char *env_hwconfig = env_get("hwconfig");
 987         enum boot_src src = get_boot_src();
 988         int is_nor_flash_available = 1;
 989
 990         switch (src) {
 991         case BOOT_SOURCE_IFC_NOR:
 992                 is_nor_flash_available = 1;
 993                 break;
 994         case BOOT_SOURCE_QSPI_NOR:
 995                 is_nor_flash_available = 0;
 996                 break;
 997         /*
 998          * In Case of SD boot,if qspi is defined in env_hwconfig
 999          * disable nor flash probe.
1000          */
1001         default:
1002                 if (hwconfig_f("qspi", env_hwconfig))
1003                         is_nor_flash_available = 0;
1004                 break;
1005         }
1006         return is_nor_flash_available;
1007 }
1008 #endif
1009
1010 #ifdef CONFIG_ENV_IS_IN_SPI_FLASH
1011 void *env_sf_get_env_addr(void)
1012 {
1013         return (void *)(CONFIG_SYS_FSL_QSPI_BASE + CONFIG_ENV_OFFSET);
1014 }
1015 #endif
1016 #endif