1 // SPDX-License-Identifier: GPL-2.0+
3 * Copyright 2017-2018 NXP
14 #include <fdt_support.h>
15 #include <linux/libfdt.h>
16 #include <fsl-mc/fsl_mc.h>
17 #include <environment.h>
18 #include <asm/arch-fsl-layerscape/soc.h>
19 #include <asm/arch/ppa.h>
21 #include <asm/arch/fsl_serdes.h>
22 #include <asm/arch/soc.h>
24 #include "../common/qixis.h"
25 #include "ls1088a_qixis.h"
26 #include "../common/vid.h"
27 #include <fsl_immap.h>
29 DECLARE_GLOBAL_DATA_PTR;
31 int board_early_init_f(void)
33 #if defined(CONFIG_SYS_I2C_EARLY_INIT) && defined(CONFIG_TARGET_LS1088AQDS)
36 fsl_lsch3_early_init_f();
40 #ifdef CONFIG_FSL_QIXIS
41 unsigned long long get_qixis_addr(void)
43 unsigned long long addr;
45 if (gd->flags & GD_FLG_RELOC)
46 addr = QIXIS_BASE_PHYS;
48 addr = QIXIS_BASE_PHYS_EARLY;
51 * IFC address under 256MB is mapped to 0x30000000, any address above
52 * is mapped to 0x5_10000000 up to 4GB.
54 addr = addr > 0x10000000 ? addr + 0x500000000ULL : addr + 0x30000000;
60 #if defined(CONFIG_VID)
61 int init_func_vid(void)
63 if (adjust_vdd(0) < 0)
64 printf("core voltage not adjusted\n");
74 board_id = QIXIS_READ(id);
75 if (board_id == LS1088ARDB_PB_BOARD)
81 int fixup_ls1088ardb_pb_banner(void *fdt)
83 fdt_setprop_string(fdt, 0, "model", "LS1088ARDB-PB Board");
88 #if !defined(CONFIG_SPL_BUILD)
93 static const char *const freq[] = {"100", "125", "156.25",
97 #ifdef CONFIG_TARGET_LS1088AQDS
98 printf("Board: LS1088A-QDS, ");
101 printf("Board: LS1088ARDB-PB, ");
103 printf("Board: LS1088A-RDB, ");
106 sw = QIXIS_READ(arch);
107 printf("Board Arch: V%d, ", sw >> 4);
109 #ifdef CONFIG_TARGET_LS1088AQDS
110 printf("Board version: %c, boot from ", (sw & 0xf) + 'A' - 1);
112 printf("Board version: %c, boot from ", (sw & 0xf) + 'A');
115 memset((u8 *)buf, 0x00, ARRAY_SIZE(buf));
117 sw = QIXIS_READ(brdcfg[0]);
118 sw = (sw & QIXIS_LBMAP_MASK) >> QIXIS_LBMAP_SHIFT;
120 #ifdef CONFIG_SD_BOOT
124 #ifdef CONFIG_TARGET_LS1088AQDS
133 printf("vBank: %d\n", sw);
146 sw = QIXIS_READ(brdcfg[0]);
147 sw = (sw & QIXIS_QMAP_MASK) >> QIXIS_QMAP_SHIFT;
148 if (sw == 0 || sw == 4)
157 printf("invalid setting of SW%u\n", QIXIS_LBMAP_SWITCH);
161 #ifdef CONFIG_TARGET_LS1088AQDS
162 printf("FPGA: v%d (%s), build %d",
163 (int)QIXIS_READ(scver), qixis_read_tag(buf),
164 (int)qixis_read_minor());
165 /* the timestamp string contains "\n" at the end */
166 printf(" on %s", qixis_read_time(buf));
168 printf("CPLD: v%d.%d\n", QIXIS_READ(scver), QIXIS_READ(tagdata));
172 * Display the actual SERDES reference clocks as configured by the
173 * dip switches on the board. Note that the SWx registers could
174 * technically be set to force the reference clocks to match the
175 * values that the SERDES expects (or vice versa). For now, however,
176 * we just display both values and hope the user notices when they
179 puts("SERDES1 Reference : ");
180 sw = QIXIS_READ(brdcfg[2]);
181 clock = (sw >> 6) & 3;
182 printf("Clock1 = %sMHz ", freq[clock]);
183 clock = (sw >> 4) & 3;
184 printf("Clock2 = %sMHz", freq[clock]);
186 puts("\nSERDES2 Reference : ");
187 clock = (sw >> 2) & 3;
188 printf("Clock1 = %sMHz ", freq[clock]);
189 clock = (sw >> 0) & 3;
190 printf("Clock2 = %sMHz\n", freq[clock]);
196 bool if_board_diff_clk(void)
198 #ifdef CONFIG_TARGET_LS1088AQDS
199 u8 diff_conf = QIXIS_READ(brdcfg[11]);
200 return diff_conf & 0x40;
202 u8 diff_conf = QIXIS_READ(dutcfg[11]);
203 return diff_conf & 0x80;
207 unsigned long get_board_sys_clk(void)
209 u8 sysclk_conf = QIXIS_READ(brdcfg[1]);
211 switch (sysclk_conf & 0x0f) {
212 case QIXIS_SYSCLK_83:
214 case QIXIS_SYSCLK_100:
216 case QIXIS_SYSCLK_125:
218 case QIXIS_SYSCLK_133:
220 case QIXIS_SYSCLK_150:
222 case QIXIS_SYSCLK_160:
224 case QIXIS_SYSCLK_166:
231 unsigned long get_board_ddr_clk(void)
233 u8 ddrclk_conf = QIXIS_READ(brdcfg[1]);
235 if (if_board_diff_clk())
236 return get_board_sys_clk();
237 switch ((ddrclk_conf & 0x30) >> 4) {
238 case QIXIS_DDRCLK_100:
240 case QIXIS_DDRCLK_125:
242 case QIXIS_DDRCLK_133:
249 int select_i2c_ch_pca9547(u8 ch)
253 ret = i2c_write(I2C_MUX_PCA_ADDR_PRI, 0, 1, &ch, 1);
255 puts("PCA: failed to select proper channel\n");
262 #if !defined(CONFIG_SPL_BUILD)
263 void board_retimer_init(void)
267 /* Retimer is connected to I2C1_CH5 */
268 select_i2c_ch_pca9547(I2C_MUX_CH5);
270 /* Access to Control/Shared register */
272 i2c_write(I2C_RETIMER_ADDR, 0xff, 1, ®, 1);
274 /* Read device revision and ID */
275 i2c_read(I2C_RETIMER_ADDR, 1, 1, ®, 1);
276 debug("Retimer version id = 0x%x\n", reg);
278 /* Enable Broadcast. All writes target all channel register sets */
280 i2c_write(I2C_RETIMER_ADDR, 0xff, 1, ®, 1);
282 /* Reset Channel Registers */
283 i2c_read(I2C_RETIMER_ADDR, 0, 1, ®, 1);
285 i2c_write(I2C_RETIMER_ADDR, 0, 1, ®, 1);
287 /* Set data rate as 10.3125 Gbps */
289 i2c_write(I2C_RETIMER_ADDR, 0x60, 1, ®, 1);
291 i2c_write(I2C_RETIMER_ADDR, 0x61, 1, ®, 1);
293 i2c_write(I2C_RETIMER_ADDR, 0x62, 1, ®, 1);
295 i2c_write(I2C_RETIMER_ADDR, 0x63, 1, ®, 1);
297 i2c_write(I2C_RETIMER_ADDR, 0x64, 1, ®, 1);
299 /* Select VCO Divider to full rate (000) */
300 i2c_read(I2C_RETIMER_ADDR, 0x2F, 1, ®, 1);
303 i2c_write(I2C_RETIMER_ADDR, 0x2F, 1, ®, 1);
305 #ifdef CONFIG_TARGET_LS1088AQDS
306 /* Retimer is connected to I2C1_CH5 */
307 select_i2c_ch_pca9547(I2C_MUX_CH5);
309 /* Access to Control/Shared register */
311 i2c_write(I2C_RETIMER_ADDR2, 0xff, 1, ®, 1);
313 /* Read device revision and ID */
314 i2c_read(I2C_RETIMER_ADDR2, 1, 1, ®, 1);
315 debug("Retimer version id = 0x%x\n", reg);
317 /* Enable Broadcast. All writes target all channel register sets */
319 i2c_write(I2C_RETIMER_ADDR2, 0xff, 1, ®, 1);
321 /* Reset Channel Registers */
322 i2c_read(I2C_RETIMER_ADDR2, 0, 1, ®, 1);
324 i2c_write(I2C_RETIMER_ADDR2, 0, 1, ®, 1);
326 /* Set data rate as 10.3125 Gbps */
328 i2c_write(I2C_RETIMER_ADDR2, 0x60, 1, ®, 1);
330 i2c_write(I2C_RETIMER_ADDR2, 0x61, 1, ®, 1);
332 i2c_write(I2C_RETIMER_ADDR2, 0x62, 1, ®, 1);
334 i2c_write(I2C_RETIMER_ADDR2, 0x63, 1, ®, 1);
336 i2c_write(I2C_RETIMER_ADDR2, 0x64, 1, ®, 1);
338 /* Select VCO Divider to full rate (000) */
339 i2c_read(I2C_RETIMER_ADDR2, 0x2F, 1, ®, 1);
342 i2c_write(I2C_RETIMER_ADDR2, 0x2F, 1, ®, 1);
344 /*return the default channel*/
345 select_i2c_ch_pca9547(I2C_MUX_CH_DEFAULT);
348 #ifdef CONFIG_MISC_INIT_R
349 int misc_init_r(void)
351 #ifdef CONFIG_TARGET_LS1088ARDB
354 if (hwconfig("esdhc-force-sd")) {
355 brdcfg5 = QIXIS_READ(brdcfg[5]);
356 brdcfg5 &= ~BRDCFG5_SPISDHC_MASK;
357 brdcfg5 |= BRDCFG5_FORCE_SD;
358 QIXIS_WRITE(brdcfg[5], brdcfg5);
366 int i2c_multiplexer_select_vid_channel(u8 channel)
368 return select_i2c_ch_pca9547(channel);
371 #ifdef CONFIG_TARGET_LS1088AQDS
372 /* read the current value(SVDD) of the LTM Regulator Voltage */
373 int get_serdes_volt(void)
376 u8 chan = PWM_CHANNEL0;
378 /* Select the PAGE 0 using PMBus commands PAGE for VDD */
379 ret = i2c_write(I2C_SVDD_MONITOR_ADDR,
380 PMBUS_CMD_PAGE, 1, &chan, 1);
382 printf("VID: failed to select VDD Page 0\n");
386 /* Read the output voltage using PMBus command READ_VOUT */
387 ret = i2c_read(I2C_SVDD_MONITOR_ADDR,
388 PMBUS_CMD_READ_VOUT, 1, (void *)&vcode, 2);
390 printf("VID: failed to read the volatge\n");
397 int set_serdes_volt(int svdd)
400 u8 buff[5] = {0x04, PWM_CHANNEL0, PMBUS_CMD_VOUT_COMMAND,
401 svdd & 0xFF, (svdd & 0xFF00) >> 8};
403 /* Write the desired voltage code to the SVDD regulator */
404 ret = i2c_write(I2C_SVDD_MONITOR_ADDR,
405 PMBUS_CMD_PAGE_PLUS_WRITE, 1, (void *)&buff, 5);
407 printf("VID: I2C failed to write to the volatge regulator\n");
411 /* Wait for the volatge to get to the desired value */
413 vdd_last = get_serdes_volt();
415 printf("VID: Couldn't read sensor abort VID adjust\n");
418 } while (vdd_last != svdd);
423 int get_serdes_volt(void)
428 int set_serdes_volt(int svdd)
433 printf("SVDD changing of RDB\n");
435 /* Read the BRDCFG54 via CLPD */
436 ret = i2c_read(CONFIG_SYS_I2C_FPGA_ADDR,
437 QIXIS_BRDCFG4_OFFSET, 1, (void *)&brdcfg4, 1);
439 printf("VID: I2C failed to read the CPLD BRDCFG4\n");
443 brdcfg4 = brdcfg4 | 0x08;
445 /* Write to the BRDCFG4 */
446 ret = i2c_write(CONFIG_SYS_I2C_FPGA_ADDR,
447 QIXIS_BRDCFG4_OFFSET, 1, (void *)&brdcfg4, 1);
449 debug("VID: I2C failed to set the SVDD CPLD BRDCFG4\n");
453 /* Wait for the volatge to get to the desired value */
460 /* this function disables the SERDES, changes the SVDD Voltage and enables it*/
461 int board_adjust_vdd(int vdd)
465 debug("%s: vdd = %d\n", __func__, vdd);
467 /* Special settings to be performed when voltage is 900mV */
469 ret = setup_serdes_volt(vdd);
479 #if !defined(CONFIG_SPL_BUILD)
482 init_final_memctl_regs();
483 #if defined(CONFIG_TARGET_LS1088ARDB) && defined(CONFIG_FSL_MC_ENET)
484 u32 __iomem *irq_ccsr = (u32 __iomem *)ISC_BASE;
487 select_i2c_ch_pca9547(I2C_MUX_CH_DEFAULT);
488 board_retimer_init();
490 #ifdef CONFIG_ENV_IS_NOWHERE
491 gd->env_addr = (ulong)&default_environment[0];
494 #if defined(CONFIG_TARGET_LS1088ARDB) && defined(CONFIG_FSL_MC_ENET)
495 /* invert AQR105 IRQ pins polarity */
496 out_le32(irq_ccsr + IRQCR_OFFSET / 4, AQR105_IRQ_MASK);
499 #ifdef CONFIG_FSL_CAAM
502 #ifdef CONFIG_FSL_LS_PPA
508 void detail_board_ddr_info(void)
511 print_size(gd->bd->bi_dram[0].size + gd->bd->bi_dram[1].size, "");
515 #if defined(CONFIG_ARCH_MISC_INIT)
516 int arch_misc_init(void)
522 #ifdef CONFIG_FSL_MC_ENET
523 void fdt_fixup_board_enet(void *fdt)
527 offset = fdt_path_offset(fdt, "/fsl-mc");
530 offset = fdt_path_offset(fdt, "/fsl,dprc@0");
533 printf("%s: ERROR: fsl-mc node not found in device tree (error %d)\n",
538 if ((get_mc_boot_status() == 0) && (get_dpl_apply_status() == 0))
539 fdt_status_okay(fdt, offset);
541 fdt_status_fail(fdt, offset);
545 #ifdef CONFIG_OF_BOARD_SETUP
546 void fsl_fdt_fixup_flash(void *fdt)
551 * IFC-NOR and QSPI are muxed on SoC.
552 * So disable IFC node in dts if QSPI is enabled or
553 * disable QSPI node in dts in case QSPI is not enabled.
556 #ifdef CONFIG_FSL_QSPI
557 offset = fdt_path_offset(fdt, "/soc/ifc/nor");
560 offset = fdt_path_offset(fdt, "/ifc/nor");
562 offset = fdt_path_offset(fdt, "/soc/quadspi");
565 offset = fdt_path_offset(fdt, "/quadspi");
570 fdt_status_disabled(fdt, offset);
573 int ft_board_setup(void *blob, bd_t *bd)
576 u64 base[CONFIG_NR_DRAM_BANKS];
577 u64 size[CONFIG_NR_DRAM_BANKS];
579 ft_cpu_setup(blob, bd);
581 /* fixup DT for the two GPP DDR banks */
582 for (i = 0; i < CONFIG_NR_DRAM_BANKS; i++) {
583 base[i] = gd->bd->bi_dram[i].start;
584 size[i] = gd->bd->bi_dram[i].size;
587 #ifdef CONFIG_RESV_RAM
588 /* reduce size if reserved memory is within this bank */
589 if (gd->arch.resv_ram >= base[0] &&
590 gd->arch.resv_ram < base[0] + size[0])
591 size[0] = gd->arch.resv_ram - base[0];
592 else if (gd->arch.resv_ram >= base[1] &&
593 gd->arch.resv_ram < base[1] + size[1])
594 size[1] = gd->arch.resv_ram - base[1];
597 fdt_fixup_memory_banks(blob, base, size, CONFIG_NR_DRAM_BANKS);
599 fdt_fsl_mc_fixup_iommu_map_entry(blob);
601 fsl_fdt_fixup_flash(blob);
603 #ifdef CONFIG_FSL_MC_ENET
604 fdt_fixup_board_enet(blob);
605 err = fsl_mc_ldpaa_exit(bd);
610 fixup_ls1088ardb_pb_banner(blob);
615 #endif /* defined(CONFIG_SPL_BUILD) */