board/freescale/ls1088a/ls1088a.c

   1 // SPDX-License-Identifier: GPL-2.0+
   2 /*
   3  * Copyright 2017-2018 NXP
   4  */
   5 #include <common.h>
   6 #include <env.h>
   7 #include <i2c.h>
   8 #include <init.h>
   9 #include <log.h>
  10 #include <malloc.h>
  11 #include <errno.h>
  12 #include <netdev.h>
  13 #include <fsl_ifc.h>
  14 #include <fsl_ddr.h>
  15 #include <fsl_sec.h>
  16 #include <asm/global_data.h>
  17 #include <asm/io.h>
  18 #include <fdt_support.h>
  19 #include <linux/delay.h>
  20 #include <linux/libfdt.h>
  21 #include <fsl-mc/fsl_mc.h>
  22 #include <env_internal.h>
  23 #include <asm/arch-fsl-layerscape/soc.h>
  24 #include <asm/arch/ppa.h>
  25 #include <hwconfig.h>
  26 #include <asm/arch/fsl_serdes.h>
  27 #include <asm/arch/soc.h>
  28 #include <asm/arch-fsl-layerscape/fsl_icid.h>
  29 #include "../common/i2c_mux.h"
  30
  31 #include "../common/qixis.h"
  32 #include "ls1088a_qixis.h"
  33 #include "../common/vid.h"
  34 #include <fsl_immap.h>
  35
  36 DECLARE_GLOBAL_DATA_PTR;
  37
  38 #ifdef CONFIG_TARGET_LS1088AQDS
  39 #ifdef CONFIG_TFABOOT
  40 struct ifc_regs ifc_cfg_ifc_nor_boot[CONFIG_SYS_FSL_IFC_BANK_COUNT] = {
  41         {
  42                 "nor0",
  43                 CONFIG_SYS_NOR0_CSPR_EARLY,
  44                 CONFIG_SYS_NOR0_CSPR_EXT,
  45                 CONFIG_SYS_NOR_AMASK,
  46                 CONFIG_SYS_NOR_CSOR,
  47                 {
  48                         CONFIG_SYS_NOR_FTIM0,
  49                         CONFIG_SYS_NOR_FTIM1,
  50                         CONFIG_SYS_NOR_FTIM2,
  51                         CONFIG_SYS_NOR_FTIM3
  52                 },
  53                 0,
  54                 CONFIG_SYS_NOR0_CSPR,
  55                 0,
  56         },
  57         {
  58                 "nor1",
  59                 CONFIG_SYS_NOR1_CSPR_EARLY,
  60                 CONFIG_SYS_NOR0_CSPR_EXT,
  61                 CONFIG_SYS_NOR_AMASK_EARLY,
  62                 CONFIG_SYS_NOR_CSOR,
  63                 {
  64                         CONFIG_SYS_NOR_FTIM0,
  65                         CONFIG_SYS_NOR_FTIM1,
  66                         CONFIG_SYS_NOR_FTIM2,
  67                         CONFIG_SYS_NOR_FTIM3
  68                 },
  69                 0,
  70                 CONFIG_SYS_NOR1_CSPR,
  71                 CONFIG_SYS_NOR_AMASK,
  72         },
  73         {
  74                 "nand",
  75                 CONFIG_SYS_NAND_CSPR,
  76                 CONFIG_SYS_NAND_CSPR_EXT,
  77                 CONFIG_SYS_NAND_AMASK,
  78                 CONFIG_SYS_NAND_CSOR,
  79                 {
  80                         CONFIG_SYS_NAND_FTIM0,
  81                         CONFIG_SYS_NAND_FTIM1,
  82                         CONFIG_SYS_NAND_FTIM2,
  83                         CONFIG_SYS_NAND_FTIM3
  84                 },
  85         },
  86         {
  87                 "fpga",
  88                 CONFIG_SYS_FPGA_CSPR,
  89                 CONFIG_SYS_FPGA_CSPR_EXT,
  90                 SYS_FPGA_AMASK,
  91                 CONFIG_SYS_FPGA_CSOR,
  92                 {
  93                         SYS_FPGA_CS_FTIM0,
  94                         SYS_FPGA_CS_FTIM1,
  95                         SYS_FPGA_CS_FTIM2,
  96                         SYS_FPGA_CS_FTIM3
  97                 },
  98                 0,
  99                 SYS_FPGA_CSPR_FINAL,
 100                 0,
 101         }
 102 };
 103
 104 struct ifc_regs ifc_cfg_qspi_nor_boot[CONFIG_SYS_FSL_IFC_BANK_COUNT] = {
 105         {
 106                 "nand",
 107                 CONFIG_SYS_NAND_CSPR,
 108                 CONFIG_SYS_NAND_CSPR_EXT,
 109                 CONFIG_SYS_NAND_AMASK,
 110                 CONFIG_SYS_NAND_CSOR,
 111                 {
 112                         CONFIG_SYS_NAND_FTIM0,
 113                         CONFIG_SYS_NAND_FTIM1,
 114                         CONFIG_SYS_NAND_FTIM2,
 115                         CONFIG_SYS_NAND_FTIM3
 116                 },
 117         },
 118         {
 119                 "reserved",
 120         },
 121         {
 122                 "fpga",
 123                 CONFIG_SYS_FPGA_CSPR,
 124                 CONFIG_SYS_FPGA_CSPR_EXT,
 125                 SYS_FPGA_AMASK,
 126                 CONFIG_SYS_FPGA_CSOR,
 127                 {
 128                         SYS_FPGA_CS_FTIM0,
 129                         SYS_FPGA_CS_FTIM1,
 130                         SYS_FPGA_CS_FTIM2,
 131                         SYS_FPGA_CS_FTIM3
 132                 },
 133                 0,
 134                 SYS_FPGA_CSPR_FINAL,
 135                 0,
 136         }
 137 };
 138
 139 void ifc_cfg_boot_info(struct ifc_regs_info *regs_info)
 140 {
 141         enum boot_src src = get_boot_src();
 142
 143         if (src == BOOT_SOURCE_QSPI_NOR)
 144                 regs_info->regs = ifc_cfg_qspi_nor_boot;
 145         else
 146                 regs_info->regs = ifc_cfg_ifc_nor_boot;
 147
 148         regs_info->cs_size = CONFIG_SYS_FSL_IFC_BANK_COUNT;
 149 }
 150 #endif /* CONFIG_TFABOOT */
 151 #endif /* CONFIG_TARGET_LS1088AQDS */
 152
 153 int board_early_init_f(void)
 154 {
 155 #if defined(CONFIG_SYS_I2C_EARLY_INIT) && defined(CONFIG_TARGET_LS1088AQDS)
 156         i2c_early_init_f();
 157 #endif
 158         fsl_lsch3_early_init_f();
 159         return 0;
 160 }
 161
 162 #ifdef CONFIG_FSL_QIXIS
 163 unsigned long long get_qixis_addr(void)
 164 {
 165         unsigned long long addr;
 166
 167         if (gd->flags & GD_FLG_RELOC)
 168                 addr = QIXIS_BASE_PHYS;
 169         else
 170                 addr = QIXIS_BASE_PHYS_EARLY;
 171
 172         /*
 173          * IFC address under 256MB is mapped to 0x30000000, any address above
 174          * is mapped to 0x5_10000000 up to 4GB.
 175          */
 176         addr = addr  > 0x10000000 ? addr + 0x500000000ULL : addr + 0x30000000;
 177
 178         return addr;
 179 }
 180 #endif
 181
 182 #if defined(CONFIG_VID)
 183 int init_func_vid(void)
 184 {
 185         if (adjust_vdd(0) < 0)
 186                 printf("core voltage not adjusted\n");
 187
 188         return 0;
 189 }
 190
 191 u16 soc_get_fuse_vid(int vid_index)
 192 {
 193         static const u16 vdd[32] = {
 194                 10250,
 195                 9875,
 196                 9750,
 197                 0,      /* reserved */
 198                 0,      /* reserved */
 199                 0,      /* reserved */
 200                 0,      /* reserved */
 201                 0,      /* reserved */
 202                 9000,
 203                 0,      /* reserved */
 204                 0,      /* reserved */
 205                 0,      /* reserved */
 206                 0,      /* reserved */
 207                 0,      /* reserved */
 208                 0,      /* reserved */
 209                 0,      /* reserved */
 210                 10000,  /* 1.0000V */
 211                 10125,
 212                 10250,
 213                 0,      /* reserved */
 214                 0,      /* reserved */
 215                 0,      /* reserved */
 216                 0,      /* reserved */
 217                 0,      /* reserved */
 218                 0,      /* reserved */
 219                 0,      /* reserved */
 220                 0,      /* reserved */
 221                 0,      /* reserved */
 222                 0,      /* reserved */
 223                 0,      /* reserved */
 224                 0,      /* reserved */
 225                 0,      /* reserved */
 226         };
 227
 228         return vdd[vid_index];
 229 };
 230 #endif
 231
 232 int is_pb_board(void)
 233 {
 234         u8 board_id;
 235
 236         board_id = QIXIS_READ(id);
 237         if (board_id == LS1088ARDB_PB_BOARD)
 238                 return 1;
 239         else
 240                 return 0;
 241 }
 242
 243 int fixup_ls1088ardb_pb_banner(void *fdt)
 244 {
 245         fdt_setprop_string(fdt, 0, "model", "LS1088ARDB-PB Board");
 246
 247         return 0;
 248 }
 249
 250 #if !defined(CONFIG_SPL_BUILD)
 251 int checkboard(void)
 252 {
 253 #ifdef CONFIG_TFABOOT
 254         enum boot_src src = get_boot_src();
 255 #endif
 256         char buf[64];
 257         u8 sw;
 258         static const char *const freq[] = {"100", "125", "156.25",
 259                                             "100 separate SSCG"};
 260         int clock;
 261
 262 #ifdef CONFIG_TARGET_LS1088AQDS
 263         printf("Board: LS1088A-QDS, ");
 264 #else
 265         if (is_pb_board())
 266                 printf("Board: LS1088ARDB-PB, ");
 267         else
 268                 printf("Board: LS1088A-RDB, ");
 269 #endif
 270
 271         sw = QIXIS_READ(arch);
 272         printf("Board Arch: V%d, ", sw >> 4);
 273
 274 #ifdef CONFIG_TARGET_LS1088AQDS
 275         printf("Board version: %c, boot from ", (sw & 0xf) + 'A' - 1);
 276 #else
 277         printf("Board version: %c, boot from ", (sw & 0xf) + 'A');
 278 #endif
 279
 280         memset((u8 *)buf, 0x00, ARRAY_SIZE(buf));
 281
 282         sw = QIXIS_READ(brdcfg[0]);
 283         sw = (sw & QIXIS_LBMAP_MASK) >> QIXIS_LBMAP_SHIFT;
 284
 285 #ifdef CONFIG_TFABOOT
 286         if (src == BOOT_SOURCE_SD_MMC)
 287                 puts("SD card\n");
 288 #else
 289 #ifdef CONFIG_SD_BOOT
 290         puts("SD card\n");
 291 #endif
 292 #endif /* CONFIG_TFABOOT */
 293         switch (sw) {
 294 #ifdef CONFIG_TARGET_LS1088AQDS
 295         case 0:
 296         case 1:
 297         case 2:
 298         case 3:
 299         case 4:
 300         case 5:
 301         case 6:
 302         case 7:
 303                 printf("vBank: %d\n", sw);
 304                 break;
 305         case 8:
 306                 puts("PromJet\n");
 307                 break;
 308         case 15:
 309                 puts("IFCCard\n");
 310                 break;
 311         case 14:
 312 #else
 313         case 0:
 314 #endif
 315                 puts("QSPI:");
 316                 sw = QIXIS_READ(brdcfg[0]);
 317                 sw = (sw & QIXIS_QMAP_MASK) >> QIXIS_QMAP_SHIFT;
 318                 if (sw == 0 || sw == 4)
 319                         puts("0\n");
 320                 else if (sw == 1)
 321                         puts("1\n");
 322                 else
 323                         puts("EMU\n");
 324                 break;
 325
 326         default:
 327                 printf("invalid setting of SW%u\n", QIXIS_LBMAP_SWITCH);
 328                 break;
 329         }
 330
 331 #ifdef CONFIG_TARGET_LS1088AQDS
 332         printf("FPGA: v%d (%s), build %d",
 333                (int)QIXIS_READ(scver), qixis_read_tag(buf),
 334                (int)qixis_read_minor());
 335         /* the timestamp string contains "\n" at the end */
 336         printf(" on %s", qixis_read_time(buf));
 337 #else
 338         printf("CPLD: v%d.%d\n", QIXIS_READ(scver), QIXIS_READ(tagdata));
 339 #endif
 340
 341         /*
 342          * Display the actual SERDES reference clocks as configured by the
 343          * dip switches on the board.  Note that the SWx registers could
 344          * technically be set to force the reference clocks to match the
 345          * values that the SERDES expects (or vice versa).  For now, however,
 346          * we just display both values and hope the user notices when they
 347          * don't match.
 348          */
 349         puts("SERDES1 Reference : ");
 350         sw = QIXIS_READ(brdcfg[2]);
 351         clock = (sw >> 6) & 3;
 352         printf("Clock1 = %sMHz ", freq[clock]);
 353         clock = (sw >> 4) & 3;
 354         printf("Clock2 = %sMHz", freq[clock]);
 355
 356         puts("\nSERDES2 Reference : ");
 357         clock = (sw >> 2) & 3;
 358         printf("Clock1 = %sMHz ", freq[clock]);
 359         clock = (sw >> 0) & 3;
 360         printf("Clock2 = %sMHz\n", freq[clock]);
 361
 362         return 0;
 363 }
 364 #endif
 365
 366 bool if_board_diff_clk(void)
 367 {
 368 #ifdef CONFIG_TARGET_LS1088AQDS
 369         u8 diff_conf = QIXIS_READ(brdcfg[11]);
 370         return diff_conf & 0x40;
 371 #else
 372         u8 diff_conf = QIXIS_READ(dutcfg[11]);
 373         return diff_conf & 0x80;
 374 #endif
 375 }
 376
 377 unsigned long get_board_sys_clk(void)
 378 {
 379         u8 sysclk_conf = QIXIS_READ(brdcfg[1]);
 380
 381         switch (sysclk_conf & 0x0f) {
 382         case QIXIS_SYSCLK_83:
 383                 return 83333333;
 384         case QIXIS_SYSCLK_100:
 385                 return 100000000;
 386         case QIXIS_SYSCLK_125:
 387                 return 125000000;
 388         case QIXIS_SYSCLK_133:
 389                 return 133333333;
 390         case QIXIS_SYSCLK_150:
 391                 return 150000000;
 392         case QIXIS_SYSCLK_160:
 393                 return 160000000;
 394         case QIXIS_SYSCLK_166:
 395                 return 166666666;
 396         }
 397
 398         return 66666666;
 399 }
 400
 401 #ifdef CONFIG_DYNAMIC_DDR_CLK_FREQ
 402 unsigned long get_board_ddr_clk(void)
 403 {
 404         u8 ddrclk_conf = QIXIS_READ(brdcfg[1]);
 405
 406         if (if_board_diff_clk())
 407                 return get_board_sys_clk();
 408         switch ((ddrclk_conf & 0x30) >> 4) {
 409         case QIXIS_DDRCLK_100:
 410                 return 100000000;
 411         case QIXIS_DDRCLK_125:
 412                 return 125000000;
 413         case QIXIS_DDRCLK_133:
 414                 return 133333333;
 415         }
 416
 417         return 66666666;
 418 }
 419 #endif
 420
 421 #if !defined(CONFIG_SPL_BUILD)
 422 void board_retimer_init(void)
 423 {
 424         u8 reg;
 425
 426         /* Retimer is connected to I2C1_CH5 */
 427         select_i2c_ch_pca9547(I2C_MUX_CH5, 0);
 428
 429         /* Access to Control/Shared register */
 430         reg = 0x0;
 431 #if !CONFIG_IS_ENABLED(DM_I2C)
 432         i2c_write(I2C_RETIMER_ADDR, 0xff, 1, &reg, 1);
 433 #else
 434         struct udevice *dev;
 435
 436         i2c_get_chip_for_busnum(0, I2C_RETIMER_ADDR, 1, &dev);
 437         dm_i2c_write(dev, 0xff, &reg, 1);
 438 #endif
 439
 440         /* Read device revision and ID */
 441 #if !CONFIG_IS_ENABLED(DM_I2C)
 442         i2c_read(I2C_RETIMER_ADDR, 1, 1, &reg, 1);
 443 #else
 444         dm_i2c_read(dev, 1, &reg, 1);
 445 #endif
 446         debug("Retimer version id = 0x%x\n", reg);
 447
 448         /* Enable Broadcast. All writes target all channel register sets */
 449         reg = 0x0c;
 450 #if !CONFIG_IS_ENABLED(DM_I2C)
 451         i2c_write(I2C_RETIMER_ADDR, 0xff, 1, &reg, 1);
 452 #else
 453         dm_i2c_write(dev, 0xff, &reg, 1);
 454 #endif
 455
 456         /* Reset Channel Registers */
 457 #if !CONFIG_IS_ENABLED(DM_I2C)
 458         i2c_read(I2C_RETIMER_ADDR, 0, 1, &reg, 1);
 459 #else
 460         dm_i2c_read(dev, 0, &reg, 1);
 461 #endif
 462         reg |= 0x4;
 463 #if !CONFIG_IS_ENABLED(DM_I2C)
 464         i2c_write(I2C_RETIMER_ADDR, 0, 1, &reg, 1);
 465 #else
 466         dm_i2c_write(dev, 0, &reg, 1);
 467 #endif
 468
 469         /* Set data rate as 10.3125 Gbps */
 470         reg = 0x90;
 471 #if !CONFIG_IS_ENABLED(DM_I2C)
 472         i2c_write(I2C_RETIMER_ADDR, 0x60, 1, &reg, 1);
 473 #else
 474         dm_i2c_write(dev, 0x60, &reg, 1);
 475 #endif
 476         reg = 0xb3;
 477 #if !CONFIG_IS_ENABLED(DM_I2C)
 478         i2c_write(I2C_RETIMER_ADDR, 0x61, 1, &reg, 1);
 479 #else
 480         dm_i2c_write(dev, 0x61, &reg, 1);
 481 #endif
 482         reg = 0x90;
 483 #if !CONFIG_IS_ENABLED(DM_I2C)
 484         i2c_write(I2C_RETIMER_ADDR, 0x62, 1, &reg, 1);
 485 #else
 486         dm_i2c_write(dev, 0x62, &reg, 1);
 487 #endif
 488         reg = 0xb3;
 489 #if !CONFIG_IS_ENABLED(DM_I2C)
 490         i2c_write(I2C_RETIMER_ADDR, 0x63, 1, &reg, 1);
 491 #else
 492         dm_i2c_write(dev, 0x63, &reg, 1);
 493 #endif
 494         reg = 0xcd;
 495 #if !CONFIG_IS_ENABLED(DM_I2C)
 496         i2c_write(I2C_RETIMER_ADDR, 0x64, 1, &reg, 1);
 497 #else
 498         dm_i2c_write(dev, 0x64, &reg, 1);
 499 #endif
 500
 501         /* Select VCO Divider to full rate (000) */
 502 #if !CONFIG_IS_ENABLED(DM_I2C)
 503         i2c_read(I2C_RETIMER_ADDR, 0x2F, 1, &reg, 1);
 504 #else
 505         dm_i2c_read(dev, 0x2F, &reg, 1);
 506 #endif
 507         reg &= 0x0f;
 508         reg |= 0x70;
 509 #if !CONFIG_IS_ENABLED(DM_I2C)
 510         i2c_write(I2C_RETIMER_ADDR, 0x2F, 1, &reg, 1);
 511 #else
 512         dm_i2c_write(dev, 0x2F, &reg, 1);
 513 #endif
 514
 515 #ifdef  CONFIG_TARGET_LS1088AQDS
 516         /* Retimer is connected to I2C1_CH5 */
 517         select_i2c_ch_pca9547(I2C_MUX_CH5, 0);
 518
 519         /* Access to Control/Shared register */
 520         reg = 0x0;
 521 #if !CONFIG_IS_ENABLED(DM_I2C)
 522         i2c_write(I2C_RETIMER_ADDR2, 0xff, 1, &reg, 1);
 523 #else
 524         i2c_get_chip_for_busnum(0, I2C_RETIMER_ADDR2, 1, &dev);
 525         dm_i2c_write(dev, 0xff, &reg, 1);
 526 #endif
 527
 528         /* Read device revision and ID */
 529 #if !CONFIG_IS_ENABLED(DM_I2C)
 530         i2c_read(I2C_RETIMER_ADDR2, 1, 1, &reg, 1);
 531 #else
 532         dm_i2c_read(dev, 1, &reg, 1);
 533 #endif
 534         debug("Retimer version id = 0x%x\n", reg);
 535
 536         /* Enable Broadcast. All writes target all channel register sets */
 537         reg = 0x0c;
 538 #if !CONFIG_IS_ENABLED(DM_I2C)
 539         i2c_write(I2C_RETIMER_ADDR2, 0xff, 1, &reg, 1);
 540 #else
 541         dm_i2c_write(dev, 0xff, &reg, 1);
 542 #endif
 543
 544         /* Reset Channel Registers */
 545 #if !CONFIG_IS_ENABLED(DM_I2C)
 546         i2c_read(I2C_RETIMER_ADDR2, 0, 1, &reg, 1);
 547 #else
 548         dm_i2c_read(dev, 0, &reg, 1);
 549 #endif
 550         reg |= 0x4;
 551 #if !CONFIG_IS_ENABLED(DM_I2C)
 552         i2c_write(I2C_RETIMER_ADDR2, 0, 1, &reg, 1);
 553 #else
 554         dm_i2c_write(dev, 0, &reg, 1);
 555 #endif
 556
 557         /* Set data rate as 10.3125 Gbps */
 558         reg = 0x90;
 559 #if !CONFIG_IS_ENABLED(DM_I2C)
 560         i2c_write(I2C_RETIMER_ADDR2, 0x60, 1, &reg, 1);
 561 #else
 562         dm_i2c_write(dev, 0x60, &reg, 1);
 563 #endif
 564         reg = 0xb3;
 565 #if !CONFIG_IS_ENABLED(DM_I2C)
 566         i2c_write(I2C_RETIMER_ADDR2, 0x61, 1, &reg, 1);
 567 #else
 568         dm_i2c_write(dev, 0x61, &reg, 1);
 569 #endif
 570         reg = 0x90;
 571 #if !CONFIG_IS_ENABLED(DM_I2C)
 572         i2c_write(I2C_RETIMER_ADDR2, 0x62, 1, &reg, 1);
 573 #else
 574         dm_i2c_write(dev, 0x62, &reg, 1);
 575 #endif
 576         reg = 0xb3;
 577 #if !CONFIG_IS_ENABLED(DM_I2C)
 578         i2c_write(I2C_RETIMER_ADDR2, 0x63, 1, &reg, 1);
 579 #else
 580         dm_i2c_write(dev, 0x63, &reg, 1);
 581 #endif
 582         reg = 0xcd;
 583 #if !CONFIG_IS_ENABLED(DM_I2C)
 584         i2c_write(I2C_RETIMER_ADDR2, 0x64, 1, &reg, 1);
 585 #else
 586         dm_i2c_write(dev, 0x64, &reg, 1);
 587 #endif
 588
 589         /* Select VCO Divider to full rate (000) */
 590 #if !CONFIG_IS_ENABLED(DM_I2C)
 591         i2c_read(I2C_RETIMER_ADDR2, 0x2F, 1, &reg, 1);
 592 #else
 593         dm_i2c_read(dev, 0x2F, &reg, 1);
 594 #endif
 595         reg &= 0x0f;
 596         reg |= 0x70;
 597 #if !CONFIG_IS_ENABLED(DM_I2C)
 598         i2c_write(I2C_RETIMER_ADDR2, 0x2F, 1, &reg, 1);
 599 #else
 600         dm_i2c_write(dev, 0x2F, &reg, 1);
 601 #endif
 602
 603 #endif
 604         /*return the default channel*/
 605         select_i2c_ch_pca9547(I2C_MUX_CH_DEFAULT, 0);
 606 }
 607
 608 #ifdef CONFIG_MISC_INIT_R
 609 int misc_init_r(void)
 610 {
 611 #ifdef CONFIG_TARGET_LS1088ARDB
 612         u8 brdcfg5;
 613
 614         if (hwconfig("esdhc-force-sd")) {
 615                 brdcfg5 = QIXIS_READ(brdcfg[5]);
 616                 brdcfg5 &= ~BRDCFG5_SPISDHC_MASK;
 617                 brdcfg5 |= BRDCFG5_FORCE_SD;
 618                 QIXIS_WRITE(brdcfg[5], brdcfg5);
 619         }
 620 #endif
 621
 622 #ifdef CONFIG_TARGET_LS1088AQDS
 623          u8 brdcfg4, brdcfg5;
 624
 625         if (hwconfig("dspi-on-board")) {
 626                 brdcfg4 = QIXIS_READ(brdcfg[4]);
 627                 brdcfg4 &= ~BRDCFG4_USBOSC_MASK;
 628                 brdcfg4 |= BRDCFG4_SPI;
 629                 QIXIS_WRITE(brdcfg[4], brdcfg4);
 630
 631                 brdcfg5 = QIXIS_READ(brdcfg[5]);
 632                 brdcfg5 &= ~BRDCFG5_SPR_MASK;
 633                 brdcfg5 |= BRDCFG5_SPI_ON_BOARD;
 634                 QIXIS_WRITE(brdcfg[5], brdcfg5);
 635         } else if (hwconfig("dspi-off-board")) {
 636                 brdcfg4 = QIXIS_READ(brdcfg[4]);
 637                 brdcfg4 &= ~BRDCFG4_USBOSC_MASK;
 638                 brdcfg4 |= BRDCFG4_SPI;
 639                 QIXIS_WRITE(brdcfg[4], brdcfg4);
 640
 641                 brdcfg5 = QIXIS_READ(brdcfg[5]);
 642                 brdcfg5 &= ~BRDCFG5_SPR_MASK;
 643                 brdcfg5 |= BRDCFG5_SPI_OFF_BOARD;
 644                 QIXIS_WRITE(brdcfg[5], brdcfg5);
 645         }
 646 #endif
 647         return 0;
 648 }
 649 #endif
 650 #endif
 651
 652 int i2c_multiplexer_select_vid_channel(u8 channel)
 653 {
 654         return select_i2c_ch_pca9547(channel, 0);
 655 }
 656
 657 #ifdef CONFIG_TARGET_LS1088AQDS
 658 /* read the current value(SVDD) of the LTM Regulator Voltage */
 659 int get_serdes_volt(void)
 660 {
 661         int  ret, vcode = 0;
 662         u8 chan = PWM_CHANNEL0;
 663
 664         /* Select the PAGE 0 using PMBus commands PAGE for VDD */
 665 #if !CONFIG_IS_ENABLED(DM_I2C)
 666         ret = i2c_write(I2C_SVDD_MONITOR_ADDR,
 667                         PMBUS_CMD_PAGE, 1, &chan, 1);
 668 #else
 669         struct udevice *dev;
 670
 671         ret = i2c_get_chip_for_busnum(0, I2C_SVDD_MONITOR_ADDR, 1, &dev);
 672         if (!ret)
 673                 ret = dm_i2c_write(dev, PMBUS_CMD_PAGE,
 674                                    &chan, 1);
 675 #endif
 676
 677         if (ret) {
 678                 printf("VID: failed to select VDD Page 0\n");
 679                 return ret;
 680         }
 681
 682         /* Read the output voltage using PMBus command READ_VOUT */
 683 #if !CONFIG_IS_ENABLED(DM_I2C)
 684         ret = i2c_read(I2C_SVDD_MONITOR_ADDR,
 685                        PMBUS_CMD_READ_VOUT, 1, (void *)&vcode, 2);
 686 #else
 687         dm_i2c_read(dev, PMBUS_CMD_READ_VOUT, (void *)&vcode, 2);
 688 #endif
 689         if (ret) {
 690                 printf("VID: failed to read the volatge\n");
 691                 return ret;
 692         }
 693
 694         return vcode;
 695 }
 696
 697 int set_serdes_volt(int svdd)
 698 {
 699         int ret, vdd_last;
 700         u8 buff[5] = {0x04, PWM_CHANNEL0, PMBUS_CMD_VOUT_COMMAND,
 701                         svdd & 0xFF, (svdd & 0xFF00) >> 8};
 702
 703         /* Write the desired voltage code to the SVDD regulator */
 704 #if !CONFIG_IS_ENABLED(DM_I2C)
 705         ret = i2c_write(I2C_SVDD_MONITOR_ADDR,
 706                         PMBUS_CMD_PAGE_PLUS_WRITE, 1, (void *)&buff, 5);
 707 #else
 708         struct udevice *dev;
 709
 710         ret = i2c_get_chip_for_busnum(0, I2C_SVDD_MONITOR_ADDR, 1, &dev);
 711         if (!ret)
 712                 ret = dm_i2c_write(dev, PMBUS_CMD_PAGE_PLUS_WRITE,
 713                                    (void *)&buff, 5);
 714 #endif
 715         if (ret) {
 716                 printf("VID: I2C failed to write to the volatge regulator\n");
 717                 return -1;
 718         }
 719
 720         /* Wait for the volatge to get to the desired value */
 721         do {
 722                 vdd_last = get_serdes_volt();
 723                 if (vdd_last < 0) {
 724                         printf("VID: Couldn't read sensor abort VID adjust\n");
 725                         return -1;
 726                 }
 727         } while (vdd_last != svdd);
 728
 729         return 1;
 730 }
 731 #else
 732 int get_serdes_volt(void)
 733 {
 734         return 0;
 735 }
 736
 737 int set_serdes_volt(int svdd)
 738 {
 739         int ret;
 740         u8 brdcfg4;
 741
 742         printf("SVDD changing of RDB\n");
 743
 744         /* Read the BRDCFG54 via CLPD */
 745 #if !CONFIG_IS_ENABLED(DM_I2C)
 746         ret = i2c_read(CONFIG_SYS_I2C_FPGA_ADDR,
 747                        QIXIS_BRDCFG4_OFFSET, 1, (void *)&brdcfg4, 1);
 748 #else
 749         struct udevice *dev;
 750
 751         ret = i2c_get_chip_for_busnum(0, CONFIG_SYS_I2C_FPGA_ADDR, 1, &dev);
 752         if (!ret)
 753                 ret = dm_i2c_read(dev, QIXIS_BRDCFG4_OFFSET,
 754                                   (void *)&brdcfg4, 1);
 755 #endif
 756
 757         if (ret) {
 758                 printf("VID: I2C failed to read the CPLD BRDCFG4\n");
 759                 return -1;
 760         }
 761
 762         brdcfg4 = brdcfg4 | 0x08;
 763
 764         /* Write to the BRDCFG4 */
 765 #if !CONFIG_IS_ENABLED(DM_I2C)
 766         ret = i2c_write(CONFIG_SYS_I2C_FPGA_ADDR,
 767                         QIXIS_BRDCFG4_OFFSET, 1, (void *)&brdcfg4, 1);
 768 #else
 769         ret = dm_i2c_write(dev, QIXIS_BRDCFG4_OFFSET,
 770                            (void *)&brdcfg4, 1);
 771 #endif
 772
 773         if (ret) {
 774                 debug("VID: I2C failed to set the SVDD CPLD BRDCFG4\n");
 775                 return -1;
 776         }
 777
 778         /* Wait for the volatge to get to the desired value */
 779         udelay(10000);
 780
 781         return 1;
 782 }
 783 #endif
 784
 785 /* this function disables the SERDES, changes the SVDD Voltage and enables it*/
 786 int board_adjust_vdd(int vdd)
 787 {
 788         int ret = 0;
 789
 790         debug("%s: vdd = %d\n", __func__, vdd);
 791
 792         /* Special settings to be performed when voltage is 900mV */
 793         if (vdd == 900) {
 794                 ret = setup_serdes_volt(vdd);
 795                 if (ret < 0) {
 796                         ret = -1;
 797                         goto exit;
 798                 }
 799         }
 800 exit:
 801         return ret;
 802 }
 803
 804 #if !defined(CONFIG_SPL_BUILD)
 805 int board_init(void)
 806 {
 807         init_final_memctl_regs();
 808 #if defined(CONFIG_TARGET_LS1088ARDB) && defined(CONFIG_FSL_MC_ENET)
 809         u32 __iomem *irq_ccsr = (u32 __iomem *)ISC_BASE;
 810 #endif
 811
 812         select_i2c_ch_pca9547(I2C_MUX_CH_DEFAULT, 0);
 813         board_retimer_init();
 814
 815 #if defined(CONFIG_TARGET_LS1088ARDB) && defined(CONFIG_FSL_MC_ENET)
 816         /* invert AQR105 IRQ pins polarity */
 817         out_le32(irq_ccsr + IRQCR_OFFSET / 4, AQR105_IRQ_MASK);
 818 #endif
 819
 820 #ifdef CONFIG_FSL_CAAM
 821         sec_init();
 822 #endif
 823 #ifdef CONFIG_FSL_LS_PPA
 824         ppa_init();
 825 #endif
 826
 827 #if !defined(CONFIG_SYS_EARLY_PCI_INIT) && defined(CONFIG_DM_ETH)
 828         pci_init();
 829 #endif
 830
 831         return 0;
 832 }
 833
 834 void detail_board_ddr_info(void)
 835 {
 836         puts("\nDDR    ");
 837         print_size(gd->bd->bi_dram[0].size + gd->bd->bi_dram[1].size, "");
 838         print_ddr_info(0);
 839 }
 840
 841 #ifdef CONFIG_FSL_MC_ENET
 842 void board_quiesce_devices(void)
 843 {
 844         fsl_mc_ldpaa_exit(gd->bd);
 845 }
 846
 847 void fdt_fixup_board_enet(void *fdt)
 848 {
 849         int offset;
 850
 851         offset = fdt_path_offset(fdt, "/fsl-mc");
 852
 853         if (offset < 0)
 854                 offset = fdt_path_offset(fdt, "/soc/fsl-mc");
 855
 856         if (offset < 0) {
 857                 printf("%s: ERROR: fsl-mc node not found in device tree (error %d)\n",
 858                        __func__, offset);
 859                 return;
 860         }
 861
 862         if (get_mc_boot_status() == 0 &&
 863             (is_lazy_dpl_addr_valid() || get_dpl_apply_status() == 0))
 864                 fdt_status_okay(fdt, offset);
 865         else
 866                 fdt_status_fail(fdt, offset);
 867 }
 868 #endif
 869
 870 #ifdef CONFIG_OF_BOARD_SETUP
 871 void fsl_fdt_fixup_flash(void *fdt)
 872 {
 873         int offset;
 874 #ifdef CONFIG_TFABOOT
 875         u32 __iomem *dcfg_ccsr = (u32 __iomem *)DCFG_BASE;
 876         u32 val;
 877 #endif
 878
 879 /*
 880  * IFC-NOR and QSPI are muxed on SoC.
 881  * So disable IFC node in dts if QSPI is enabled or
 882  * disable QSPI node in dts in case QSPI is not enabled.
 883  */
 884
 885 #ifdef CONFIG_TFABOOT
 886         enum boot_src src = get_boot_src();
 887         bool disable_ifc = false;
 888
 889         switch (src) {
 890         case BOOT_SOURCE_IFC_NOR:
 891                 disable_ifc = false;
 892                 break;
 893         case BOOT_SOURCE_QSPI_NOR:
 894                 disable_ifc = true;
 895                 break;
 896         default:
 897                 val = in_le32(dcfg_ccsr + DCFG_RCWSR15 / 4);
 898                 if (DCFG_RCWSR15_IFCGRPABASE_QSPI == (val & (u32)0x3))
 899                         disable_ifc = true;
 900                 break;
 901         }
 902
 903         if (disable_ifc) {
 904                 offset = fdt_path_offset(fdt, "/soc/ifc/nor");
 905
 906                 if (offset < 0)
 907                         offset = fdt_path_offset(fdt, "/ifc/nor");
 908         } else {
 909                 offset = fdt_path_offset(fdt, "/soc/quadspi");
 910
 911                 if (offset < 0)
 912                         offset = fdt_path_offset(fdt, "/quadspi");
 913         }
 914
 915 #else
 916 #ifdef CONFIG_FSL_QSPI
 917         offset = fdt_path_offset(fdt, "/soc/ifc/nor");
 918
 919         if (offset < 0)
 920                 offset = fdt_path_offset(fdt, "/ifc/nor");
 921 #else
 922         offset = fdt_path_offset(fdt, "/soc/quadspi");
 923
 924         if (offset < 0)
 925                 offset = fdt_path_offset(fdt, "/quadspi");
 926 #endif
 927 #endif
 928         if (offset < 0)
 929                 return;
 930
 931         fdt_status_disabled(fdt, offset);
 932 }
 933
 934 int ft_board_setup(void *blob, struct bd_info *bd)
 935 {
 936         int i;
 937         u16 mc_memory_bank = 0;
 938
 939         u64 *base;
 940         u64 *size;
 941         u64 mc_memory_base = 0;
 942         u64 mc_memory_size = 0;
 943         u16 total_memory_banks;
 944
 945         ft_cpu_setup(blob, bd);
 946
 947         fdt_fixup_mc_ddr(&mc_memory_base, &mc_memory_size);
 948
 949         if (mc_memory_base != 0)
 950                 mc_memory_bank++;
 951
 952         total_memory_banks = CONFIG_NR_DRAM_BANKS + mc_memory_bank;
 953
 954         base = calloc(total_memory_banks, sizeof(u64));
 955         size = calloc(total_memory_banks, sizeof(u64));
 956
 957         /* fixup DT for the two GPP DDR banks */
 958         for (i = 0; i < CONFIG_NR_DRAM_BANKS; i++) {
 959                 base[i] = gd->bd->bi_dram[i].start;
 960                 size[i] = gd->bd->bi_dram[i].size;
 961         }
 962
 963 #ifdef CONFIG_RESV_RAM
 964         /* reduce size if reserved memory is within this bank */
 965         if (gd->arch.resv_ram >= base[0] &&
 966             gd->arch.resv_ram < base[0] + size[0])
 967                 size[0] = gd->arch.resv_ram - base[0];
 968         else if (gd->arch.resv_ram >= base[1] &&
 969                  gd->arch.resv_ram < base[1] + size[1])
 970                 size[1] = gd->arch.resv_ram - base[1];
 971 #endif
 972
 973         if (mc_memory_base != 0) {
 974                 for (i = 0; i <= total_memory_banks; i++) {
 975                         if (base[i] == 0 && size[i] == 0) {
 976                                 base[i] = mc_memory_base;
 977                                 size[i] = mc_memory_size;
 978                                 break;
 979                         }
 980                 }
 981         }
 982
 983         fdt_fixup_memory_banks(blob, base, size, total_memory_banks);
 984
 985         fdt_fsl_mc_fixup_iommu_map_entry(blob);
 986
 987         fsl_fdt_fixup_flash(blob);
 988
 989 #ifdef CONFIG_FSL_MC_ENET
 990         fdt_fixup_board_enet(blob);
 991 #endif
 992
 993         fdt_fixup_icid(blob);
 994
 995         if (is_pb_board())
 996                 fixup_ls1088ardb_pb_banner(blob);
 997
 998         return 0;
 999 }
1000 #endif
1001 #endif /* defined(CONFIG_SPL_BUILD) */
1002
1003 #ifdef CONFIG_TFABOOT
1004 #ifdef CONFIG_MTD_NOR_FLASH
1005 int is_flash_available(void)
1006 {
1007         char *env_hwconfig = env_get("hwconfig");
1008         enum boot_src src = get_boot_src();
1009         int is_nor_flash_available = 1;
1010
1011         switch (src) {
1012         case BOOT_SOURCE_IFC_NOR:
1013                 is_nor_flash_available = 1;
1014                 break;
1015         case BOOT_SOURCE_QSPI_NOR:
1016                 is_nor_flash_available = 0;
1017                 break;
1018         /*
1019          * In Case of SD boot,if qspi is defined in env_hwconfig
1020          * disable nor flash probe.
1021          */
1022         default:
1023                 if (hwconfig_f("qspi", env_hwconfig))
1024                         is_nor_flash_available = 0;
1025                 break;
1026         }
1027         return is_nor_flash_available;
1028 }
1029 #endif
1030
1031 #ifdef CONFIG_ENV_IS_IN_SPI_FLASH
1032 void *env_sf_get_env_addr(void)
1033 {
1034         return (void *)(CONFIG_SYS_FSL_QSPI_BASE + CONFIG_ENV_OFFSET);
1035 }
1036 #endif
1037 #endif