4 * SPDX-License-Identifier: GPL-2.0+
15 #include <fdt_support.h>
17 #include <fsl-mc/fsl_mc.h>
18 #include <environment.h>
19 #include <asm/arch-fsl-layerscape/soc.h>
20 #include <asm/arch/ppa.h>
23 #include "../common/qixis.h"
24 #include "ls1088a_qixis.h"
26 DECLARE_GLOBAL_DATA_PTR;
28 unsigned long long get_qixis_addr(void)
30 unsigned long long addr;
32 if (gd->flags & GD_FLG_RELOC)
33 addr = QIXIS_BASE_PHYS;
35 addr = QIXIS_BASE_PHYS_EARLY;
38 * IFC address under 256MB is mapped to 0x30000000, any address above
39 * is mapped to 0x5_10000000 up to 4GB.
41 addr = addr > 0x10000000 ? addr + 0x500000000ULL : addr + 0x30000000;
50 static const char *const freq[] = {"100", "125", "156.25",
54 #ifdef CONFIG_TARGET_LS1088AQDS
55 printf("Board: LS1088A-QDS, ");
57 printf("Board: LS1088A-RDB, ");
60 sw = QIXIS_READ(arch);
61 printf("Board Arch: V%d, ", sw >> 4);
63 #ifdef CONFIG_TARGET_LS1088AQDS
64 printf("Board version: %c, boot from ", (sw & 0xf) + 'A' - 1);
66 printf("Board version: %c, boot from ", (sw & 0xf) + 'A');
69 memset((u8 *)buf, 0x00, ARRAY_SIZE(buf));
71 sw = QIXIS_READ(brdcfg[0]);
72 sw = (sw & QIXIS_LBMAP_MASK) >> QIXIS_LBMAP_SHIFT;
78 #ifdef CONFIG_TARGET_LS1088AQDS
87 printf("vBank: %d\n", sw);
100 sw = QIXIS_READ(brdcfg[0]);
101 sw = (sw & QIXIS_QMAP_MASK) >> QIXIS_QMAP_SHIFT;
102 if (sw == 0 || sw == 4)
111 printf("invalid setting of SW%u\n", QIXIS_LBMAP_SWITCH);
115 #ifdef CONFIG_TARGET_LS1088AQDS
116 printf("FPGA: v%d (%s), build %d",
117 (int)QIXIS_READ(scver), qixis_read_tag(buf),
118 (int)qixis_read_minor());
119 /* the timestamp string contains "\n" at the end */
120 printf(" on %s", qixis_read_time(buf));
122 printf("CPLD: v%d.%d\n", QIXIS_READ(scver), QIXIS_READ(tagdata));
126 * Display the actual SERDES reference clocks as configured by the
127 * dip switches on the board. Note that the SWx registers could
128 * technically be set to force the reference clocks to match the
129 * values that the SERDES expects (or vice versa). For now, however,
130 * we just display both values and hope the user notices when they
133 puts("SERDES1 Reference : ");
134 sw = QIXIS_READ(brdcfg[2]);
135 clock = (sw >> 6) & 3;
136 printf("Clock1 = %sMHz ", freq[clock]);
137 clock = (sw >> 4) & 3;
138 printf("Clock2 = %sMHz", freq[clock]);
140 puts("\nSERDES2 Reference : ");
141 clock = (sw >> 2) & 3;
142 printf("Clock1 = %sMHz ", freq[clock]);
143 clock = (sw >> 0) & 3;
144 printf("Clock2 = %sMHz\n", freq[clock]);
149 bool if_board_diff_clk(void)
151 #ifdef CONFIG_TARGET_LS1088AQDS
152 u8 diff_conf = QIXIS_READ(brdcfg[11]);
153 return diff_conf & 0x40;
155 u8 diff_conf = QIXIS_READ(dutcfg[11]);
156 return diff_conf & 0x80;
160 unsigned long get_board_sys_clk(void)
162 u8 sysclk_conf = QIXIS_READ(brdcfg[1]);
164 switch (sysclk_conf & 0x0f) {
165 case QIXIS_SYSCLK_83:
167 case QIXIS_SYSCLK_100:
169 case QIXIS_SYSCLK_125:
171 case QIXIS_SYSCLK_133:
173 case QIXIS_SYSCLK_150:
175 case QIXIS_SYSCLK_160:
177 case QIXIS_SYSCLK_166:
184 unsigned long get_board_ddr_clk(void)
186 u8 ddrclk_conf = QIXIS_READ(brdcfg[1]);
188 if (if_board_diff_clk())
189 return get_board_sys_clk();
190 switch ((ddrclk_conf & 0x30) >> 4) {
191 case QIXIS_DDRCLK_100:
193 case QIXIS_DDRCLK_125:
195 case QIXIS_DDRCLK_133:
202 int select_i2c_ch_pca9547(u8 ch)
206 ret = i2c_write(I2C_MUX_PCA_ADDR_PRI, 0, 1, &ch, 1);
208 puts("PCA: failed to select proper channel\n");
215 void board_retimer_init(void)
219 /* Retimer is connected to I2C1_CH5 */
220 select_i2c_ch_pca9547(I2C_MUX_CH5);
222 /* Access to Control/Shared register */
224 i2c_write(I2C_RETIMER_ADDR, 0xff, 1, ®, 1);
226 /* Read device revision and ID */
227 i2c_read(I2C_RETIMER_ADDR, 1, 1, ®, 1);
228 debug("Retimer version id = 0x%x\n", reg);
230 /* Enable Broadcast. All writes target all channel register sets */
232 i2c_write(I2C_RETIMER_ADDR, 0xff, 1, ®, 1);
234 /* Reset Channel Registers */
235 i2c_read(I2C_RETIMER_ADDR, 0, 1, ®, 1);
237 i2c_write(I2C_RETIMER_ADDR, 0, 1, ®, 1);
239 /* Set data rate as 10.3125 Gbps */
241 i2c_write(I2C_RETIMER_ADDR, 0x60, 1, ®, 1);
243 i2c_write(I2C_RETIMER_ADDR, 0x61, 1, ®, 1);
245 i2c_write(I2C_RETIMER_ADDR, 0x62, 1, ®, 1);
247 i2c_write(I2C_RETIMER_ADDR, 0x63, 1, ®, 1);
249 i2c_write(I2C_RETIMER_ADDR, 0x64, 1, ®, 1);
251 /* Select VCO Divider to full rate (000) */
252 i2c_read(I2C_RETIMER_ADDR, 0x2F, 1, ®, 1);
255 i2c_write(I2C_RETIMER_ADDR, 0x2F, 1, ®, 1);
257 #ifdef CONFIG_TARGET_LS1088AQDS
258 /* Retimer is connected to I2C1_CH5 */
259 select_i2c_ch_pca9547(I2C_MUX_CH5);
261 /* Access to Control/Shared register */
263 i2c_write(I2C_RETIMER_ADDR2, 0xff, 1, ®, 1);
265 /* Read device revision and ID */
266 i2c_read(I2C_RETIMER_ADDR2, 1, 1, ®, 1);
267 debug("Retimer version id = 0x%x\n", reg);
269 /* Enable Broadcast. All writes target all channel register sets */
271 i2c_write(I2C_RETIMER_ADDR2, 0xff, 1, ®, 1);
273 /* Reset Channel Registers */
274 i2c_read(I2C_RETIMER_ADDR2, 0, 1, ®, 1);
276 i2c_write(I2C_RETIMER_ADDR2, 0, 1, ®, 1);
278 /* Set data rate as 10.3125 Gbps */
280 i2c_write(I2C_RETIMER_ADDR2, 0x60, 1, ®, 1);
282 i2c_write(I2C_RETIMER_ADDR2, 0x61, 1, ®, 1);
284 i2c_write(I2C_RETIMER_ADDR2, 0x62, 1, ®, 1);
286 i2c_write(I2C_RETIMER_ADDR2, 0x63, 1, ®, 1);
288 i2c_write(I2C_RETIMER_ADDR2, 0x64, 1, ®, 1);
290 /* Select VCO Divider to full rate (000) */
291 i2c_read(I2C_RETIMER_ADDR2, 0x2F, 1, ®, 1);
294 i2c_write(I2C_RETIMER_ADDR2, 0x2F, 1, ®, 1);
296 /*return the default channel*/
297 select_i2c_ch_pca9547(I2C_MUX_CH_DEFAULT);
300 #ifdef CONFIG_MISC_INIT_R
301 int misc_init_r(void)
303 #ifdef CONFIG_TARGET_LS1088ARDB
306 if (hwconfig("esdhc-force-sd")) {
307 brdcfg5 = QIXIS_READ(brdcfg[5]);
308 brdcfg5 &= ~BRDCFG5_SPISDHC_MASK;
309 brdcfg5 |= BRDCFG5_FORCE_SD;
310 QIXIS_WRITE(brdcfg[5], brdcfg5);
319 init_final_memctl_regs();
320 #if defined(CONFIG_TARGET_LS1088ARDB) && defined(CONFIG_FSL_MC_ENET)
321 u32 __iomem *irq_ccsr = (u32 __iomem *)ISC_BASE;
324 select_i2c_ch_pca9547(I2C_MUX_CH_DEFAULT);
325 board_retimer_init();
327 #ifdef CONFIG_ENV_IS_NOWHERE
328 gd->env_addr = (ulong)&default_environment[0];
331 #if defined(CONFIG_TARGET_LS1088ARDB) && defined(CONFIG_FSL_MC_ENET)
332 /* invert AQR105 IRQ pins polarity */
333 out_le32(irq_ccsr + IRQCR_OFFSET / 4, AQR105_IRQ_MASK);
336 #ifdef CONFIG_FSL_CAAM
339 #ifdef CONFIG_FSL_LS_PPA
345 int board_early_init_f(void)
347 fsl_lsch3_early_init_f();
351 void detail_board_ddr_info(void)
354 print_size(gd->bd->bi_dram[0].size + gd->bd->bi_dram[1].size, "");
358 #if defined(CONFIG_ARCH_MISC_INIT)
359 int arch_misc_init(void)
365 #ifdef CONFIG_FSL_MC_ENET
366 void fdt_fixup_board_enet(void *fdt)
370 offset = fdt_path_offset(fdt, "/fsl-mc");
373 offset = fdt_path_offset(fdt, "/fsl,dprc@0");
376 printf("%s: ERROR: fsl-mc node not found in device tree (error %d)\n",
381 if (get_mc_boot_status() == 0)
382 fdt_status_okay(fdt, offset);
384 fdt_status_fail(fdt, offset);
388 #ifdef CONFIG_OF_BOARD_SETUP
389 void fsl_fdt_fixup_flash(void *fdt)
394 * IFC-NOR and QSPI are muxed on SoC.
395 * So disable IFC node in dts if QSPI is enabled or
396 * disable QSPI node in dts in case QSPI is not enabled.
399 #ifdef CONFIG_FSL_QSPI
400 offset = fdt_path_offset(fdt, "/soc/ifc/nor");
403 offset = fdt_path_offset(fdt, "/ifc/nor");
405 offset = fdt_path_offset(fdt, "/soc/quadspi");
408 offset = fdt_path_offset(fdt, "/quadspi");
413 fdt_status_disabled(fdt, offset);
416 int ft_board_setup(void *blob, bd_t *bd)
419 u64 base[CONFIG_NR_DRAM_BANKS];
420 u64 size[CONFIG_NR_DRAM_BANKS];
422 ft_cpu_setup(blob, bd);
424 /* fixup DT for the two GPP DDR banks */
425 for (i = 0; i < CONFIG_NR_DRAM_BANKS; i++) {
426 base[i] = gd->bd->bi_dram[i].start;
427 size[i] = gd->bd->bi_dram[i].size;
430 #ifdef CONFIG_RESV_RAM
431 /* reduce size if reserved memory is within this bank */
432 if (gd->arch.resv_ram >= base[0] &&
433 gd->arch.resv_ram < base[0] + size[0])
434 size[0] = gd->arch.resv_ram - base[0];
435 else if (gd->arch.resv_ram >= base[1] &&
436 gd->arch.resv_ram < base[1] + size[1])
437 size[1] = gd->arch.resv_ram - base[1];
440 fdt_fixup_memory_banks(blob, base, size, CONFIG_NR_DRAM_BANKS);
442 fsl_fdt_fixup_flash(blob);
444 #ifdef CONFIG_FSL_MC_ENET
445 fdt_fixup_board_enet(blob);
446 err = fsl_mc_ldpaa_exit(bd);