4 * SPDX-License-Identifier: GPL-2.0+
15 #include <fdt_support.h>
17 #include <fsl-mc/fsl_mc.h>
18 #include <environment.h>
19 #include <asm/arch-fsl-layerscape/soc.h>
20 #include <asm/arch/ppa.h>
22 #include "../common/qixis.h"
23 #include "ls1088a_qixis.h"
25 DECLARE_GLOBAL_DATA_PTR;
27 unsigned long long get_qixis_addr(void)
29 unsigned long long addr;
31 if (gd->flags & GD_FLG_RELOC)
32 addr = QIXIS_BASE_PHYS;
34 addr = QIXIS_BASE_PHYS_EARLY;
37 * IFC address under 256MB is mapped to 0x30000000, any address above
38 * is mapped to 0x5_10000000 up to 4GB.
40 addr = addr > 0x10000000 ? addr + 0x500000000ULL : addr + 0x30000000;
49 static const char *const freq[] = {"100", "125", "156.25",
53 #ifdef CONFIG_TARGET_LS1088AQDS
54 printf("Board: LS1088A-QDS, ");
56 printf("Board: LS1088A-RDB, ");
59 sw = QIXIS_READ(arch);
60 printf("Board Arch: V%d, ", sw >> 4);
62 #ifdef CONFIG_TARGET_LS1088AQDS
63 printf("Board version: %c, boot from ", (sw & 0xf) + 'A' - 1);
65 printf("Board version: %c, boot from ", (sw & 0xf) + 'A');
68 memset((u8 *)buf, 0x00, ARRAY_SIZE(buf));
70 sw = QIXIS_READ(brdcfg[0]);
71 sw = (sw & QIXIS_LBMAP_MASK) >> QIXIS_LBMAP_SHIFT;
77 #ifdef CONFIG_TARGET_LS1088AQDS
86 printf("vBank: %d\n", sw);
99 sw = QIXIS_READ(brdcfg[0]);
100 sw = (sw & QIXIS_QMAP_MASK) >> QIXIS_QMAP_SHIFT;
101 if (sw == 0 || sw == 4)
110 printf("invalid setting of SW%u\n", QIXIS_LBMAP_SWITCH);
114 #ifdef CONFIG_TARGET_LS1088AQDS
115 printf("FPGA: v%d (%s), build %d",
116 (int)QIXIS_READ(scver), qixis_read_tag(buf),
117 (int)qixis_read_minor());
118 /* the timestamp string contains "\n" at the end */
119 printf(" on %s", qixis_read_time(buf));
121 printf("CPLD: v%d.%d\n", QIXIS_READ(scver), QIXIS_READ(tagdata));
125 * Display the actual SERDES reference clocks as configured by the
126 * dip switches on the board. Note that the SWx registers could
127 * technically be set to force the reference clocks to match the
128 * values that the SERDES expects (or vice versa). For now, however,
129 * we just display both values and hope the user notices when they
132 puts("SERDES1 Reference : ");
133 sw = QIXIS_READ(brdcfg[2]);
134 clock = (sw >> 6) & 3;
135 printf("Clock1 = %sMHz ", freq[clock]);
136 clock = (sw >> 4) & 3;
137 printf("Clock2 = %sMHz", freq[clock]);
139 puts("\nSERDES2 Reference : ");
140 clock = (sw >> 2) & 3;
141 printf("Clock1 = %sMHz ", freq[clock]);
142 clock = (sw >> 0) & 3;
143 printf("Clock2 = %sMHz\n", freq[clock]);
148 bool if_board_diff_clk(void)
150 #ifdef CONFIG_TARGET_LS1088AQDS
151 u8 diff_conf = QIXIS_READ(brdcfg[11]);
152 return diff_conf & 0x40;
154 u8 diff_conf = QIXIS_READ(dutcfg[11]);
155 return diff_conf & 0x80;
159 unsigned long get_board_sys_clk(void)
161 u8 sysclk_conf = QIXIS_READ(brdcfg[1]);
163 switch (sysclk_conf & 0x0f) {
164 case QIXIS_SYSCLK_83:
166 case QIXIS_SYSCLK_100:
168 case QIXIS_SYSCLK_125:
170 case QIXIS_SYSCLK_133:
172 case QIXIS_SYSCLK_150:
174 case QIXIS_SYSCLK_160:
176 case QIXIS_SYSCLK_166:
183 unsigned long get_board_ddr_clk(void)
185 u8 ddrclk_conf = QIXIS_READ(brdcfg[1]);
187 if (if_board_diff_clk())
188 return get_board_sys_clk();
189 switch ((ddrclk_conf & 0x30) >> 4) {
190 case QIXIS_DDRCLK_100:
192 case QIXIS_DDRCLK_125:
194 case QIXIS_DDRCLK_133:
201 int select_i2c_ch_pca9547(u8 ch)
205 ret = i2c_write(I2C_MUX_PCA_ADDR_PRI, 0, 1, &ch, 1);
207 puts("PCA: failed to select proper channel\n");
214 void board_retimer_init(void)
218 /* Retimer is connected to I2C1_CH5 */
219 select_i2c_ch_pca9547(I2C_MUX_CH5);
221 /* Access to Control/Shared register */
223 i2c_write(I2C_RETIMER_ADDR, 0xff, 1, ®, 1);
225 /* Read device revision and ID */
226 i2c_read(I2C_RETIMER_ADDR, 1, 1, ®, 1);
227 debug("Retimer version id = 0x%x\n", reg);
229 /* Enable Broadcast. All writes target all channel register sets */
231 i2c_write(I2C_RETIMER_ADDR, 0xff, 1, ®, 1);
233 /* Reset Channel Registers */
234 i2c_read(I2C_RETIMER_ADDR, 0, 1, ®, 1);
236 i2c_write(I2C_RETIMER_ADDR, 0, 1, ®, 1);
238 /* Set data rate as 10.3125 Gbps */
240 i2c_write(I2C_RETIMER_ADDR, 0x60, 1, ®, 1);
242 i2c_write(I2C_RETIMER_ADDR, 0x61, 1, ®, 1);
244 i2c_write(I2C_RETIMER_ADDR, 0x62, 1, ®, 1);
246 i2c_write(I2C_RETIMER_ADDR, 0x63, 1, ®, 1);
248 i2c_write(I2C_RETIMER_ADDR, 0x64, 1, ®, 1);
250 /* Select VCO Divider to full rate (000) */
251 i2c_read(I2C_RETIMER_ADDR, 0x2F, 1, ®, 1);
254 i2c_write(I2C_RETIMER_ADDR, 0x2F, 1, ®, 1);
256 #ifdef CONFIG_TARGET_LS1088AQDS
257 /* Retimer is connected to I2C1_CH5 */
258 select_i2c_ch_pca9547(I2C_MUX_CH5);
260 /* Access to Control/Shared register */
262 i2c_write(I2C_RETIMER_ADDR2, 0xff, 1, ®, 1);
264 /* Read device revision and ID */
265 i2c_read(I2C_RETIMER_ADDR2, 1, 1, ®, 1);
266 debug("Retimer version id = 0x%x\n", reg);
268 /* Enable Broadcast. All writes target all channel register sets */
270 i2c_write(I2C_RETIMER_ADDR2, 0xff, 1, ®, 1);
272 /* Reset Channel Registers */
273 i2c_read(I2C_RETIMER_ADDR2, 0, 1, ®, 1);
275 i2c_write(I2C_RETIMER_ADDR2, 0, 1, ®, 1);
277 /* Set data rate as 10.3125 Gbps */
279 i2c_write(I2C_RETIMER_ADDR2, 0x60, 1, ®, 1);
281 i2c_write(I2C_RETIMER_ADDR2, 0x61, 1, ®, 1);
283 i2c_write(I2C_RETIMER_ADDR2, 0x62, 1, ®, 1);
285 i2c_write(I2C_RETIMER_ADDR2, 0x63, 1, ®, 1);
287 i2c_write(I2C_RETIMER_ADDR2, 0x64, 1, ®, 1);
289 /* Select VCO Divider to full rate (000) */
290 i2c_read(I2C_RETIMER_ADDR2, 0x2F, 1, ®, 1);
293 i2c_write(I2C_RETIMER_ADDR2, 0x2F, 1, ®, 1);
295 /*return the default channel*/
296 select_i2c_ch_pca9547(I2C_MUX_CH_DEFAULT);
301 init_final_memctl_regs();
302 #if defined(CONFIG_TARGET_LS1088ARDB) && defined(CONFIG_FSL_MC_ENET)
303 u32 __iomem *irq_ccsr = (u32 __iomem *)ISC_BASE;
306 select_i2c_ch_pca9547(I2C_MUX_CH_DEFAULT);
307 board_retimer_init();
309 #ifdef CONFIG_ENV_IS_NOWHERE
310 gd->env_addr = (ulong)&default_environment[0];
313 #if defined(CONFIG_TARGET_LS1088ARDB) && defined(CONFIG_FSL_MC_ENET)
314 /* invert AQR105 IRQ pins polarity */
315 out_le32(irq_ccsr + IRQCR_OFFSET / 4, AQR105_IRQ_MASK);
318 #ifdef CONFIG_FSL_LS_PPA
324 int board_early_init_f(void)
326 fsl_lsch3_early_init_f();
330 void detail_board_ddr_info(void)
333 print_size(gd->bd->bi_dram[0].size + gd->bd->bi_dram[1].size, "");
337 #if defined(CONFIG_ARCH_MISC_INIT)
338 int arch_misc_init(void)
340 #ifdef CONFIG_FSL_CAAM
347 #ifdef CONFIG_FSL_MC_ENET
348 void fdt_fixup_board_enet(void *fdt)
352 offset = fdt_path_offset(fdt, "/fsl-mc");
355 offset = fdt_path_offset(fdt, "/fsl,dprc@0");
358 printf("%s: ERROR: fsl-mc node not found in device tree (error %d)\n",
363 if (get_mc_boot_status() == 0)
364 fdt_status_okay(fdt, offset);
366 fdt_status_fail(fdt, offset);
370 #ifdef CONFIG_OF_BOARD_SETUP
371 int ft_board_setup(void *blob, bd_t *bd)
374 u64 base[CONFIG_NR_DRAM_BANKS];
375 u64 size[CONFIG_NR_DRAM_BANKS];
377 ft_cpu_setup(blob, bd);
379 /* fixup DT for the two GPP DDR banks */
380 for (i = 0; i < CONFIG_NR_DRAM_BANKS; i++) {
381 base[i] = gd->bd->bi_dram[i].start;
382 size[i] = gd->bd->bi_dram[i].size;
385 #ifdef CONFIG_RESV_RAM
386 /* reduce size if reserved memory is within this bank */
387 if (gd->arch.resv_ram >= base[0] &&
388 gd->arch.resv_ram < base[0] + size[0])
389 size[0] = gd->arch.resv_ram - base[0];
390 else if (gd->arch.resv_ram >= base[1] &&
391 gd->arch.resv_ram < base[1] + size[1])
392 size[1] = gd->arch.resv_ram - base[1];
395 fdt_fixup_memory_banks(blob, base, size, CONFIG_NR_DRAM_BANKS);
397 #ifdef CONFIG_FSL_MC_ENET
398 fdt_fixup_board_enet(blob);
399 err = fsl_mc_ldpaa_exit(bd);