4 * SPDX-License-Identifier: GPL-2.0+
15 #include <fdt_support.h>
17 #include <fsl-mc/fsl_mc.h>
18 #include <environment.h>
19 #include <asm/arch-fsl-layerscape/soc.h>
20 #include <asm/arch/ppa.h>
23 #include "../common/qixis.h"
24 #include "ls1088a_qixis.h"
26 DECLARE_GLOBAL_DATA_PTR;
28 int board_early_init_f(void)
30 fsl_lsch3_early_init_f();
34 #ifdef CONFIG_FSL_QIXIS
35 unsigned long long get_qixis_addr(void)
37 unsigned long long addr;
39 if (gd->flags & GD_FLG_RELOC)
40 addr = QIXIS_BASE_PHYS;
42 addr = QIXIS_BASE_PHYS_EARLY;
45 * IFC address under 256MB is mapped to 0x30000000, any address above
46 * is mapped to 0x5_10000000 up to 4GB.
48 addr = addr > 0x10000000 ? addr + 0x500000000ULL : addr + 0x30000000;
54 #if !defined(CONFIG_SPL_BUILD)
59 static const char *const freq[] = {"100", "125", "156.25",
63 #ifdef CONFIG_TARGET_LS1088AQDS
64 printf("Board: LS1088A-QDS, ");
66 printf("Board: LS1088A-RDB, ");
69 sw = QIXIS_READ(arch);
70 printf("Board Arch: V%d, ", sw >> 4);
72 #ifdef CONFIG_TARGET_LS1088AQDS
73 printf("Board version: %c, boot from ", (sw & 0xf) + 'A' - 1);
75 printf("Board version: %c, boot from ", (sw & 0xf) + 'A');
78 memset((u8 *)buf, 0x00, ARRAY_SIZE(buf));
80 sw = QIXIS_READ(brdcfg[0]);
81 sw = (sw & QIXIS_LBMAP_MASK) >> QIXIS_LBMAP_SHIFT;
87 #ifdef CONFIG_TARGET_LS1088AQDS
96 printf("vBank: %d\n", sw);
109 sw = QIXIS_READ(brdcfg[0]);
110 sw = (sw & QIXIS_QMAP_MASK) >> QIXIS_QMAP_SHIFT;
111 if (sw == 0 || sw == 4)
120 printf("invalid setting of SW%u\n", QIXIS_LBMAP_SWITCH);
124 #ifdef CONFIG_TARGET_LS1088AQDS
125 printf("FPGA: v%d (%s), build %d",
126 (int)QIXIS_READ(scver), qixis_read_tag(buf),
127 (int)qixis_read_minor());
128 /* the timestamp string contains "\n" at the end */
129 printf(" on %s", qixis_read_time(buf));
131 printf("CPLD: v%d.%d\n", QIXIS_READ(scver), QIXIS_READ(tagdata));
135 * Display the actual SERDES reference clocks as configured by the
136 * dip switches on the board. Note that the SWx registers could
137 * technically be set to force the reference clocks to match the
138 * values that the SERDES expects (or vice versa). For now, however,
139 * we just display both values and hope the user notices when they
142 puts("SERDES1 Reference : ");
143 sw = QIXIS_READ(brdcfg[2]);
144 clock = (sw >> 6) & 3;
145 printf("Clock1 = %sMHz ", freq[clock]);
146 clock = (sw >> 4) & 3;
147 printf("Clock2 = %sMHz", freq[clock]);
149 puts("\nSERDES2 Reference : ");
150 clock = (sw >> 2) & 3;
151 printf("Clock1 = %sMHz ", freq[clock]);
152 clock = (sw >> 0) & 3;
153 printf("Clock2 = %sMHz\n", freq[clock]);
158 bool if_board_diff_clk(void)
160 #ifdef CONFIG_TARGET_LS1088AQDS
161 u8 diff_conf = QIXIS_READ(brdcfg[11]);
162 return diff_conf & 0x40;
164 u8 diff_conf = QIXIS_READ(dutcfg[11]);
165 return diff_conf & 0x80;
169 unsigned long get_board_sys_clk(void)
171 u8 sysclk_conf = QIXIS_READ(brdcfg[1]);
173 switch (sysclk_conf & 0x0f) {
174 case QIXIS_SYSCLK_83:
176 case QIXIS_SYSCLK_100:
178 case QIXIS_SYSCLK_125:
180 case QIXIS_SYSCLK_133:
182 case QIXIS_SYSCLK_150:
184 case QIXIS_SYSCLK_160:
186 case QIXIS_SYSCLK_166:
193 unsigned long get_board_ddr_clk(void)
195 u8 ddrclk_conf = QIXIS_READ(brdcfg[1]);
197 if (if_board_diff_clk())
198 return get_board_sys_clk();
199 switch ((ddrclk_conf & 0x30) >> 4) {
200 case QIXIS_DDRCLK_100:
202 case QIXIS_DDRCLK_125:
204 case QIXIS_DDRCLK_133:
211 int select_i2c_ch_pca9547(u8 ch)
215 ret = i2c_write(I2C_MUX_PCA_ADDR_PRI, 0, 1, &ch, 1);
217 puts("PCA: failed to select proper channel\n");
224 void board_retimer_init(void)
228 /* Retimer is connected to I2C1_CH5 */
229 select_i2c_ch_pca9547(I2C_MUX_CH5);
231 /* Access to Control/Shared register */
233 i2c_write(I2C_RETIMER_ADDR, 0xff, 1, ®, 1);
235 /* Read device revision and ID */
236 i2c_read(I2C_RETIMER_ADDR, 1, 1, ®, 1);
237 debug("Retimer version id = 0x%x\n", reg);
239 /* Enable Broadcast. All writes target all channel register sets */
241 i2c_write(I2C_RETIMER_ADDR, 0xff, 1, ®, 1);
243 /* Reset Channel Registers */
244 i2c_read(I2C_RETIMER_ADDR, 0, 1, ®, 1);
246 i2c_write(I2C_RETIMER_ADDR, 0, 1, ®, 1);
248 /* Set data rate as 10.3125 Gbps */
250 i2c_write(I2C_RETIMER_ADDR, 0x60, 1, ®, 1);
252 i2c_write(I2C_RETIMER_ADDR, 0x61, 1, ®, 1);
254 i2c_write(I2C_RETIMER_ADDR, 0x62, 1, ®, 1);
256 i2c_write(I2C_RETIMER_ADDR, 0x63, 1, ®, 1);
258 i2c_write(I2C_RETIMER_ADDR, 0x64, 1, ®, 1);
260 /* Select VCO Divider to full rate (000) */
261 i2c_read(I2C_RETIMER_ADDR, 0x2F, 1, ®, 1);
264 i2c_write(I2C_RETIMER_ADDR, 0x2F, 1, ®, 1);
266 #ifdef CONFIG_TARGET_LS1088AQDS
267 /* Retimer is connected to I2C1_CH5 */
268 select_i2c_ch_pca9547(I2C_MUX_CH5);
270 /* Access to Control/Shared register */
272 i2c_write(I2C_RETIMER_ADDR2, 0xff, 1, ®, 1);
274 /* Read device revision and ID */
275 i2c_read(I2C_RETIMER_ADDR2, 1, 1, ®, 1);
276 debug("Retimer version id = 0x%x\n", reg);
278 /* Enable Broadcast. All writes target all channel register sets */
280 i2c_write(I2C_RETIMER_ADDR2, 0xff, 1, ®, 1);
282 /* Reset Channel Registers */
283 i2c_read(I2C_RETIMER_ADDR2, 0, 1, ®, 1);
285 i2c_write(I2C_RETIMER_ADDR2, 0, 1, ®, 1);
287 /* Set data rate as 10.3125 Gbps */
289 i2c_write(I2C_RETIMER_ADDR2, 0x60, 1, ®, 1);
291 i2c_write(I2C_RETIMER_ADDR2, 0x61, 1, ®, 1);
293 i2c_write(I2C_RETIMER_ADDR2, 0x62, 1, ®, 1);
295 i2c_write(I2C_RETIMER_ADDR2, 0x63, 1, ®, 1);
297 i2c_write(I2C_RETIMER_ADDR2, 0x64, 1, ®, 1);
299 /* Select VCO Divider to full rate (000) */
300 i2c_read(I2C_RETIMER_ADDR2, 0x2F, 1, ®, 1);
303 i2c_write(I2C_RETIMER_ADDR2, 0x2F, 1, ®, 1);
305 /*return the default channel*/
306 select_i2c_ch_pca9547(I2C_MUX_CH_DEFAULT);
309 #ifdef CONFIG_MISC_INIT_R
310 int misc_init_r(void)
312 #ifdef CONFIG_TARGET_LS1088ARDB
315 if (hwconfig("esdhc-force-sd")) {
316 brdcfg5 = QIXIS_READ(brdcfg[5]);
317 brdcfg5 &= ~BRDCFG5_SPISDHC_MASK;
318 brdcfg5 |= BRDCFG5_FORCE_SD;
319 QIXIS_WRITE(brdcfg[5], brdcfg5);
328 init_final_memctl_regs();
329 #if defined(CONFIG_TARGET_LS1088ARDB) && defined(CONFIG_FSL_MC_ENET)
330 u32 __iomem *irq_ccsr = (u32 __iomem *)ISC_BASE;
333 select_i2c_ch_pca9547(I2C_MUX_CH_DEFAULT);
334 board_retimer_init();
336 #ifdef CONFIG_ENV_IS_NOWHERE
337 gd->env_addr = (ulong)&default_environment[0];
340 #if defined(CONFIG_TARGET_LS1088ARDB) && defined(CONFIG_FSL_MC_ENET)
341 /* invert AQR105 IRQ pins polarity */
342 out_le32(irq_ccsr + IRQCR_OFFSET / 4, AQR105_IRQ_MASK);
345 #ifdef CONFIG_FSL_CAAM
348 #ifdef CONFIG_FSL_LS_PPA
354 void detail_board_ddr_info(void)
357 print_size(gd->bd->bi_dram[0].size + gd->bd->bi_dram[1].size, "");
361 #if defined(CONFIG_ARCH_MISC_INIT)
362 int arch_misc_init(void)
368 #ifdef CONFIG_FSL_MC_ENET
369 void fdt_fixup_board_enet(void *fdt)
373 offset = fdt_path_offset(fdt, "/fsl-mc");
376 offset = fdt_path_offset(fdt, "/fsl,dprc@0");
379 printf("%s: ERROR: fsl-mc node not found in device tree (error %d)\n",
384 if ((get_mc_boot_status() == 0) && (get_dpl_apply_status() == 0))
385 fdt_status_okay(fdt, offset);
387 fdt_status_fail(fdt, offset);
391 #ifdef CONFIG_OF_BOARD_SETUP
392 void fsl_fdt_fixup_flash(void *fdt)
397 * IFC-NOR and QSPI are muxed on SoC.
398 * So disable IFC node in dts if QSPI is enabled or
399 * disable QSPI node in dts in case QSPI is not enabled.
402 #ifdef CONFIG_FSL_QSPI
403 offset = fdt_path_offset(fdt, "/soc/ifc/nor");
406 offset = fdt_path_offset(fdt, "/ifc/nor");
408 offset = fdt_path_offset(fdt, "/soc/quadspi");
411 offset = fdt_path_offset(fdt, "/quadspi");
416 fdt_status_disabled(fdt, offset);
419 int ft_board_setup(void *blob, bd_t *bd)
422 u64 base[CONFIG_NR_DRAM_BANKS];
423 u64 size[CONFIG_NR_DRAM_BANKS];
425 ft_cpu_setup(blob, bd);
427 /* fixup DT for the two GPP DDR banks */
428 for (i = 0; i < CONFIG_NR_DRAM_BANKS; i++) {
429 base[i] = gd->bd->bi_dram[i].start;
430 size[i] = gd->bd->bi_dram[i].size;
433 #ifdef CONFIG_RESV_RAM
434 /* reduce size if reserved memory is within this bank */
435 if (gd->arch.resv_ram >= base[0] &&
436 gd->arch.resv_ram < base[0] + size[0])
437 size[0] = gd->arch.resv_ram - base[0];
438 else if (gd->arch.resv_ram >= base[1] &&
439 gd->arch.resv_ram < base[1] + size[1])
440 size[1] = gd->arch.resv_ram - base[1];
443 fdt_fixup_memory_banks(blob, base, size, CONFIG_NR_DRAM_BANKS);
445 fsl_fdt_fixup_flash(blob);
447 #ifdef CONFIG_FSL_MC_ENET
448 fdt_fixup_board_enet(blob);
449 err = fsl_mc_ldpaa_exit(bd);
457 #endif /* defined(CONFIG_SPL_BUILD) */