1 // SPDX-License-Identifier: GPL-2.0+
3 * Copyright 2017-2018 NXP
15 #include <fdt_support.h>
16 #include <linux/libfdt.h>
17 #include <fsl-mc/fsl_mc.h>
18 #include <env_internal.h>
19 #include <asm/arch-fsl-layerscape/soc.h>
20 #include <asm/arch/ppa.h>
22 #include <asm/arch/fsl_serdes.h>
23 #include <asm/arch/soc.h>
24 #include <asm/arch-fsl-layerscape/fsl_icid.h>
26 #include "../common/qixis.h"
27 #include "ls1088a_qixis.h"
28 #include "../common/vid.h"
29 #include <fsl_immap.h>
31 DECLARE_GLOBAL_DATA_PTR;
33 #ifdef CONFIG_TARGET_LS1088AQDS
35 struct ifc_regs ifc_cfg_ifc_nor_boot[CONFIG_SYS_FSL_IFC_BANK_COUNT] = {
38 CONFIG_SYS_NOR0_CSPR_EARLY,
39 CONFIG_SYS_NOR0_CSPR_EXT,
54 CONFIG_SYS_NOR1_CSPR_EARLY,
55 CONFIG_SYS_NOR0_CSPR_EXT,
56 CONFIG_SYS_NOR_AMASK_EARLY,
71 CONFIG_SYS_NAND_CSPR_EXT,
72 CONFIG_SYS_NAND_AMASK,
75 CONFIG_SYS_NAND_FTIM0,
76 CONFIG_SYS_NAND_FTIM1,
77 CONFIG_SYS_NAND_FTIM2,
84 CONFIG_SYS_FPGA_CSPR_EXT,
99 struct ifc_regs ifc_cfg_qspi_nor_boot[CONFIG_SYS_FSL_IFC_BANK_COUNT] = {
102 CONFIG_SYS_NAND_CSPR,
103 CONFIG_SYS_NAND_CSPR_EXT,
104 CONFIG_SYS_NAND_AMASK,
105 CONFIG_SYS_NAND_CSOR,
107 CONFIG_SYS_NAND_FTIM0,
108 CONFIG_SYS_NAND_FTIM1,
109 CONFIG_SYS_NAND_FTIM2,
110 CONFIG_SYS_NAND_FTIM3
118 CONFIG_SYS_FPGA_CSPR,
119 CONFIG_SYS_FPGA_CSPR_EXT,
121 CONFIG_SYS_FPGA_CSOR,
134 void ifc_cfg_boot_info(struct ifc_regs_info *regs_info)
136 enum boot_src src = get_boot_src();
138 if (src == BOOT_SOURCE_QSPI_NOR)
139 regs_info->regs = ifc_cfg_qspi_nor_boot;
141 regs_info->regs = ifc_cfg_ifc_nor_boot;
143 regs_info->cs_size = CONFIG_SYS_FSL_IFC_BANK_COUNT;
145 #endif /* CONFIG_TFABOOT */
146 #endif /* CONFIG_TARGET_LS1088AQDS */
148 int board_early_init_f(void)
150 #if defined(CONFIG_SYS_I2C_EARLY_INIT) && defined(CONFIG_TARGET_LS1088AQDS)
153 fsl_lsch3_early_init_f();
157 #ifdef CONFIG_FSL_QIXIS
158 unsigned long long get_qixis_addr(void)
160 unsigned long long addr;
162 if (gd->flags & GD_FLG_RELOC)
163 addr = QIXIS_BASE_PHYS;
165 addr = QIXIS_BASE_PHYS_EARLY;
168 * IFC address under 256MB is mapped to 0x30000000, any address above
169 * is mapped to 0x5_10000000 up to 4GB.
171 addr = addr > 0x10000000 ? addr + 0x500000000ULL : addr + 0x30000000;
177 #if defined(CONFIG_VID)
178 int init_func_vid(void)
180 if (adjust_vdd(0) < 0)
181 printf("core voltage not adjusted\n");
187 int is_pb_board(void)
191 board_id = QIXIS_READ(id);
192 if (board_id == LS1088ARDB_PB_BOARD)
198 int fixup_ls1088ardb_pb_banner(void *fdt)
200 fdt_setprop_string(fdt, 0, "model", "LS1088ARDB-PB Board");
205 #if !defined(CONFIG_SPL_BUILD)
208 #ifdef CONFIG_TFABOOT
209 enum boot_src src = get_boot_src();
213 static const char *const freq[] = {"100", "125", "156.25",
214 "100 separate SSCG"};
217 #ifdef CONFIG_TARGET_LS1088AQDS
218 printf("Board: LS1088A-QDS, ");
221 printf("Board: LS1088ARDB-PB, ");
223 printf("Board: LS1088A-RDB, ");
226 sw = QIXIS_READ(arch);
227 printf("Board Arch: V%d, ", sw >> 4);
229 #ifdef CONFIG_TARGET_LS1088AQDS
230 printf("Board version: %c, boot from ", (sw & 0xf) + 'A' - 1);
232 printf("Board version: %c, boot from ", (sw & 0xf) + 'A');
235 memset((u8 *)buf, 0x00, ARRAY_SIZE(buf));
237 sw = QIXIS_READ(brdcfg[0]);
238 sw = (sw & QIXIS_LBMAP_MASK) >> QIXIS_LBMAP_SHIFT;
240 #ifdef CONFIG_TFABOOT
241 if (src == BOOT_SOURCE_SD_MMC)
244 #ifdef CONFIG_SD_BOOT
247 #endif /* CONFIG_TFABOOT */
249 #ifdef CONFIG_TARGET_LS1088AQDS
258 printf("vBank: %d\n", sw);
271 sw = QIXIS_READ(brdcfg[0]);
272 sw = (sw & QIXIS_QMAP_MASK) >> QIXIS_QMAP_SHIFT;
273 if (sw == 0 || sw == 4)
282 printf("invalid setting of SW%u\n", QIXIS_LBMAP_SWITCH);
286 #ifdef CONFIG_TARGET_LS1088AQDS
287 printf("FPGA: v%d (%s), build %d",
288 (int)QIXIS_READ(scver), qixis_read_tag(buf),
289 (int)qixis_read_minor());
290 /* the timestamp string contains "\n" at the end */
291 printf(" on %s", qixis_read_time(buf));
293 printf("CPLD: v%d.%d\n", QIXIS_READ(scver), QIXIS_READ(tagdata));
297 * Display the actual SERDES reference clocks as configured by the
298 * dip switches on the board. Note that the SWx registers could
299 * technically be set to force the reference clocks to match the
300 * values that the SERDES expects (or vice versa). For now, however,
301 * we just display both values and hope the user notices when they
304 puts("SERDES1 Reference : ");
305 sw = QIXIS_READ(brdcfg[2]);
306 clock = (sw >> 6) & 3;
307 printf("Clock1 = %sMHz ", freq[clock]);
308 clock = (sw >> 4) & 3;
309 printf("Clock2 = %sMHz", freq[clock]);
311 puts("\nSERDES2 Reference : ");
312 clock = (sw >> 2) & 3;
313 printf("Clock1 = %sMHz ", freq[clock]);
314 clock = (sw >> 0) & 3;
315 printf("Clock2 = %sMHz\n", freq[clock]);
321 bool if_board_diff_clk(void)
323 #ifdef CONFIG_TARGET_LS1088AQDS
324 u8 diff_conf = QIXIS_READ(brdcfg[11]);
325 return diff_conf & 0x40;
327 u8 diff_conf = QIXIS_READ(dutcfg[11]);
328 return diff_conf & 0x80;
332 unsigned long get_board_sys_clk(void)
334 u8 sysclk_conf = QIXIS_READ(brdcfg[1]);
336 switch (sysclk_conf & 0x0f) {
337 case QIXIS_SYSCLK_83:
339 case QIXIS_SYSCLK_100:
341 case QIXIS_SYSCLK_125:
343 case QIXIS_SYSCLK_133:
345 case QIXIS_SYSCLK_150:
347 case QIXIS_SYSCLK_160:
349 case QIXIS_SYSCLK_166:
356 unsigned long get_board_ddr_clk(void)
358 u8 ddrclk_conf = QIXIS_READ(brdcfg[1]);
360 if (if_board_diff_clk())
361 return get_board_sys_clk();
362 switch ((ddrclk_conf & 0x30) >> 4) {
363 case QIXIS_DDRCLK_100:
365 case QIXIS_DDRCLK_125:
367 case QIXIS_DDRCLK_133:
374 int select_i2c_ch_pca9547(u8 ch)
378 #ifndef CONFIG_DM_I2C
379 ret = i2c_write(I2C_MUX_PCA_ADDR_PRI, 0, 1, &ch, 1);
383 ret = i2c_get_chip_for_busnum(0, I2C_MUX_PCA_ADDR_PRI, 1, &dev);
385 ret = dm_i2c_write(dev, 0, &ch, 1);
388 puts("PCA: failed to select proper channel\n");
395 #if !defined(CONFIG_SPL_BUILD)
396 void board_retimer_init(void)
400 /* Retimer is connected to I2C1_CH5 */
401 select_i2c_ch_pca9547(I2C_MUX_CH5);
403 /* Access to Control/Shared register */
405 #ifndef CONFIG_DM_I2C
406 i2c_write(I2C_RETIMER_ADDR, 0xff, 1, ®, 1);
410 i2c_get_chip_for_busnum(0, I2C_RETIMER_ADDR, 1, &dev);
411 dm_i2c_write(dev, 0xff, ®, 1);
414 /* Read device revision and ID */
415 #ifndef CONFIG_DM_I2C
416 i2c_read(I2C_RETIMER_ADDR, 1, 1, ®, 1);
418 dm_i2c_read(dev, 1, ®, 1);
420 debug("Retimer version id = 0x%x\n", reg);
422 /* Enable Broadcast. All writes target all channel register sets */
424 #ifndef CONFIG_DM_I2C
425 i2c_write(I2C_RETIMER_ADDR, 0xff, 1, ®, 1);
427 dm_i2c_write(dev, 0xff, ®, 1);
430 /* Reset Channel Registers */
431 #ifndef CONFIG_DM_I2C
432 i2c_read(I2C_RETIMER_ADDR, 0, 1, ®, 1);
434 dm_i2c_read(dev, 0, ®, 1);
437 #ifndef CONFIG_DM_I2C
438 i2c_write(I2C_RETIMER_ADDR, 0, 1, ®, 1);
440 dm_i2c_write(dev, 0, ®, 1);
443 /* Set data rate as 10.3125 Gbps */
445 #ifndef CONFIG_DM_I2C
446 i2c_write(I2C_RETIMER_ADDR, 0x60, 1, ®, 1);
448 dm_i2c_write(dev, 0x60, ®, 1);
451 #ifndef CONFIG_DM_I2C
452 i2c_write(I2C_RETIMER_ADDR, 0x61, 1, ®, 1);
454 dm_i2c_write(dev, 0x61, ®, 1);
457 #ifndef CONFIG_DM_I2C
458 i2c_write(I2C_RETIMER_ADDR, 0x62, 1, ®, 1);
460 dm_i2c_write(dev, 0x62, ®, 1);
463 #ifndef CONFIG_DM_I2C
464 i2c_write(I2C_RETIMER_ADDR, 0x63, 1, ®, 1);
466 dm_i2c_write(dev, 0x63, ®, 1);
469 #ifndef CONFIG_DM_I2C
470 i2c_write(I2C_RETIMER_ADDR, 0x64, 1, ®, 1);
472 dm_i2c_write(dev, 0x64, ®, 1);
475 /* Select VCO Divider to full rate (000) */
476 #ifndef CONFIG_DM_I2C
477 i2c_read(I2C_RETIMER_ADDR, 0x2F, 1, ®, 1);
479 dm_i2c_read(dev, 0x2F, ®, 1);
483 #ifndef CONFIG_DM_I2C
484 i2c_write(I2C_RETIMER_ADDR, 0x2F, 1, ®, 1);
486 dm_i2c_write(dev, 0x2F, ®, 1);
489 #ifdef CONFIG_TARGET_LS1088AQDS
490 /* Retimer is connected to I2C1_CH5 */
491 select_i2c_ch_pca9547(I2C_MUX_CH5);
493 /* Access to Control/Shared register */
495 #ifndef CONFIG_DM_I2C
496 i2c_write(I2C_RETIMER_ADDR2, 0xff, 1, ®, 1);
498 i2c_get_chip_for_busnum(0, I2C_RETIMER_ADDR2, 1, &dev);
499 dm_i2c_write(dev, 0xff, ®, 1);
502 /* Read device revision and ID */
503 #ifndef CONFIG_DM_I2C
504 i2c_read(I2C_RETIMER_ADDR2, 1, 1, ®, 1);
506 dm_i2c_read(dev, 1, ®, 1);
508 debug("Retimer version id = 0x%x\n", reg);
510 /* Enable Broadcast. All writes target all channel register sets */
512 #ifndef CONFIG_DM_I2C
513 i2c_write(I2C_RETIMER_ADDR2, 0xff, 1, ®, 1);
515 dm_i2c_write(dev, 0xff, ®, 1);
518 /* Reset Channel Registers */
519 #ifndef CONFIG_DM_I2C
520 i2c_read(I2C_RETIMER_ADDR2, 0, 1, ®, 1);
522 dm_i2c_read(dev, 0, ®, 1);
525 #ifndef CONFIG_DM_I2C
526 i2c_write(I2C_RETIMER_ADDR2, 0, 1, ®, 1);
528 dm_i2c_write(dev, 0, ®, 1);
531 /* Set data rate as 10.3125 Gbps */
533 #ifndef CONFIG_DM_I2C
534 i2c_write(I2C_RETIMER_ADDR2, 0x60, 1, ®, 1);
536 dm_i2c_write(dev, 0x60, ®, 1);
539 #ifndef CONFIG_DM_I2C
540 i2c_write(I2C_RETIMER_ADDR2, 0x61, 1, ®, 1);
542 dm_i2c_write(dev, 0x61, ®, 1);
545 #ifndef CONFIG_DM_I2C
546 i2c_write(I2C_RETIMER_ADDR2, 0x62, 1, ®, 1);
548 dm_i2c_write(dev, 0x62, ®, 1);
551 #ifndef CONFIG_DM_I2C
552 i2c_write(I2C_RETIMER_ADDR2, 0x63, 1, ®, 1);
554 dm_i2c_write(dev, 0x63, ®, 1);
557 #ifndef CONFIG_DM_I2C
558 i2c_write(I2C_RETIMER_ADDR2, 0x64, 1, ®, 1);
560 dm_i2c_write(dev, 0x64, ®, 1);
563 /* Select VCO Divider to full rate (000) */
564 #ifndef CONFIG_DM_I2C
565 i2c_read(I2C_RETIMER_ADDR2, 0x2F, 1, ®, 1);
567 dm_i2c_read(dev, 0x2F, ®, 1);
571 #ifndef CONFIG_DM_I2C
572 i2c_write(I2C_RETIMER_ADDR2, 0x2F, 1, ®, 1);
574 dm_i2c_write(dev, 0x2F, ®, 1);
578 /*return the default channel*/
579 select_i2c_ch_pca9547(I2C_MUX_CH_DEFAULT);
582 #ifdef CONFIG_MISC_INIT_R
583 int misc_init_r(void)
585 #ifdef CONFIG_TARGET_LS1088ARDB
588 if (hwconfig("esdhc-force-sd")) {
589 brdcfg5 = QIXIS_READ(brdcfg[5]);
590 brdcfg5 &= ~BRDCFG5_SPISDHC_MASK;
591 brdcfg5 |= BRDCFG5_FORCE_SD;
592 QIXIS_WRITE(brdcfg[5], brdcfg5);
596 #ifdef CONFIG_TARGET_LS1088AQDS
599 if (hwconfig("dspi-on-board")) {
600 brdcfg4 = QIXIS_READ(brdcfg[4]);
601 brdcfg4 &= ~BRDCFG4_USBOSC_MASK;
602 brdcfg4 |= BRDCFG4_SPI;
603 QIXIS_WRITE(brdcfg[4], brdcfg4);
605 brdcfg5 = QIXIS_READ(brdcfg[5]);
606 brdcfg5 &= ~BRDCFG5_SPR_MASK;
607 brdcfg5 |= BRDCFG5_SPI_ON_BOARD;
608 QIXIS_WRITE(brdcfg[5], brdcfg5);
609 } else if (hwconfig("dspi-off-board")) {
610 brdcfg4 = QIXIS_READ(brdcfg[4]);
611 brdcfg4 &= ~BRDCFG4_USBOSC_MASK;
612 brdcfg4 |= BRDCFG4_SPI;
613 QIXIS_WRITE(brdcfg[4], brdcfg4);
615 brdcfg5 = QIXIS_READ(brdcfg[5]);
616 brdcfg5 &= ~BRDCFG5_SPR_MASK;
617 brdcfg5 |= BRDCFG5_SPI_OFF_BOARD;
618 QIXIS_WRITE(brdcfg[5], brdcfg5);
626 int i2c_multiplexer_select_vid_channel(u8 channel)
628 return select_i2c_ch_pca9547(channel);
631 #ifdef CONFIG_TARGET_LS1088AQDS
632 /* read the current value(SVDD) of the LTM Regulator Voltage */
633 int get_serdes_volt(void)
636 u8 chan = PWM_CHANNEL0;
638 /* Select the PAGE 0 using PMBus commands PAGE for VDD */
639 #ifndef CONFIG_DM_I2C
640 ret = i2c_write(I2C_SVDD_MONITOR_ADDR,
641 PMBUS_CMD_PAGE, 1, &chan, 1);
645 ret = i2c_get_chip_for_busnum(0, I2C_SVDD_MONITOR_ADDR, 1, &dev);
647 ret = dm_i2c_write(dev, PMBUS_CMD_PAGE,
652 printf("VID: failed to select VDD Page 0\n");
656 /* Read the output voltage using PMBus command READ_VOUT */
657 #ifndef CONFIG_DM_I2C
658 ret = i2c_read(I2C_SVDD_MONITOR_ADDR,
659 PMBUS_CMD_READ_VOUT, 1, (void *)&vcode, 2);
661 dm_i2c_read(dev, PMBUS_CMD_READ_VOUT, (void *)&vcode, 2);
664 printf("VID: failed to read the volatge\n");
671 int set_serdes_volt(int svdd)
674 u8 buff[5] = {0x04, PWM_CHANNEL0, PMBUS_CMD_VOUT_COMMAND,
675 svdd & 0xFF, (svdd & 0xFF00) >> 8};
677 /* Write the desired voltage code to the SVDD regulator */
678 #ifndef CONFIG_DM_I2C
679 ret = i2c_write(I2C_SVDD_MONITOR_ADDR,
680 PMBUS_CMD_PAGE_PLUS_WRITE, 1, (void *)&buff, 5);
684 ret = i2c_get_chip_for_busnum(0, I2C_SVDD_MONITOR_ADDR, 1, &dev);
686 ret = dm_i2c_write(dev, PMBUS_CMD_PAGE_PLUS_WRITE,
690 printf("VID: I2C failed to write to the volatge regulator\n");
694 /* Wait for the volatge to get to the desired value */
696 vdd_last = get_serdes_volt();
698 printf("VID: Couldn't read sensor abort VID adjust\n");
701 } while (vdd_last != svdd);
706 int get_serdes_volt(void)
711 int set_serdes_volt(int svdd)
716 printf("SVDD changing of RDB\n");
718 /* Read the BRDCFG54 via CLPD */
719 #ifndef CONFIG_DM_I2C
720 ret = i2c_read(CONFIG_SYS_I2C_FPGA_ADDR,
721 QIXIS_BRDCFG4_OFFSET, 1, (void *)&brdcfg4, 1);
725 ret = i2c_get_chip_for_busnum(0, CONFIG_SYS_I2C_FPGA_ADDR, 1, &dev);
727 ret = dm_i2c_read(dev, QIXIS_BRDCFG4_OFFSET,
728 (void *)&brdcfg4, 1);
732 printf("VID: I2C failed to read the CPLD BRDCFG4\n");
736 brdcfg4 = brdcfg4 | 0x08;
738 /* Write to the BRDCFG4 */
739 #ifndef CONFIG_DM_I2C
740 ret = i2c_write(CONFIG_SYS_I2C_FPGA_ADDR,
741 QIXIS_BRDCFG4_OFFSET, 1, (void *)&brdcfg4, 1);
743 ret = dm_i2c_write(dev, QIXIS_BRDCFG4_OFFSET,
744 (void *)&brdcfg4, 1);
748 debug("VID: I2C failed to set the SVDD CPLD BRDCFG4\n");
752 /* Wait for the volatge to get to the desired value */
759 /* this function disables the SERDES, changes the SVDD Voltage and enables it*/
760 int board_adjust_vdd(int vdd)
764 debug("%s: vdd = %d\n", __func__, vdd);
766 /* Special settings to be performed when voltage is 900mV */
768 ret = setup_serdes_volt(vdd);
778 #if !defined(CONFIG_SPL_BUILD)
781 init_final_memctl_regs();
782 #if defined(CONFIG_TARGET_LS1088ARDB) && defined(CONFIG_FSL_MC_ENET)
783 u32 __iomem *irq_ccsr = (u32 __iomem *)ISC_BASE;
786 select_i2c_ch_pca9547(I2C_MUX_CH_DEFAULT);
787 board_retimer_init();
789 #ifdef CONFIG_ENV_IS_NOWHERE
790 gd->env_addr = (ulong)&default_environment[0];
793 #if defined(CONFIG_TARGET_LS1088ARDB) && defined(CONFIG_FSL_MC_ENET)
794 /* invert AQR105 IRQ pins polarity */
795 out_le32(irq_ccsr + IRQCR_OFFSET / 4, AQR105_IRQ_MASK);
798 #ifdef CONFIG_FSL_CAAM
801 #ifdef CONFIG_FSL_LS_PPA
805 #if !defined(CONFIG_SYS_EARLY_PCI_INIT) && defined(CONFIG_DM_ETH)
812 void detail_board_ddr_info(void)
815 print_size(gd->bd->bi_dram[0].size + gd->bd->bi_dram[1].size, "");
819 #ifdef CONFIG_FSL_MC_ENET
820 void board_quiesce_devices(void)
822 fsl_mc_ldpaa_exit(gd->bd);
825 void fdt_fixup_board_enet(void *fdt)
829 offset = fdt_path_offset(fdt, "/fsl-mc");
832 offset = fdt_path_offset(fdt, "/soc/fsl-mc");
835 printf("%s: ERROR: fsl-mc node not found in device tree (error %d)\n",
840 if (get_mc_boot_status() == 0 &&
841 (is_lazy_dpl_addr_valid() || get_dpl_apply_status() == 0))
842 fdt_status_okay(fdt, offset);
844 fdt_status_fail(fdt, offset);
848 #ifdef CONFIG_OF_BOARD_SETUP
849 void fsl_fdt_fixup_flash(void *fdt)
852 #ifdef CONFIG_TFABOOT
853 u32 __iomem *dcfg_ccsr = (u32 __iomem *)DCFG_BASE;
858 * IFC-NOR and QSPI are muxed on SoC.
859 * So disable IFC node in dts if QSPI is enabled or
860 * disable QSPI node in dts in case QSPI is not enabled.
863 #ifdef CONFIG_TFABOOT
864 enum boot_src src = get_boot_src();
865 bool disable_ifc = false;
868 case BOOT_SOURCE_IFC_NOR:
871 case BOOT_SOURCE_QSPI_NOR:
875 val = in_le32(dcfg_ccsr + DCFG_RCWSR15 / 4);
876 if (DCFG_RCWSR15_IFCGRPABASE_QSPI == (val & (u32)0x3))
882 offset = fdt_path_offset(fdt, "/soc/ifc/nor");
885 offset = fdt_path_offset(fdt, "/ifc/nor");
887 offset = fdt_path_offset(fdt, "/soc/quadspi");
890 offset = fdt_path_offset(fdt, "/quadspi");
894 #ifdef CONFIG_FSL_QSPI
895 offset = fdt_path_offset(fdt, "/soc/ifc/nor");
898 offset = fdt_path_offset(fdt, "/ifc/nor");
900 offset = fdt_path_offset(fdt, "/soc/quadspi");
903 offset = fdt_path_offset(fdt, "/quadspi");
909 fdt_status_disabled(fdt, offset);
912 int ft_board_setup(void *blob, bd_t *bd)
915 u16 mc_memory_bank = 0;
919 u64 mc_memory_base = 0;
920 u64 mc_memory_size = 0;
921 u16 total_memory_banks;
923 ft_cpu_setup(blob, bd);
925 fdt_fixup_mc_ddr(&mc_memory_base, &mc_memory_size);
927 if (mc_memory_base != 0)
930 total_memory_banks = CONFIG_NR_DRAM_BANKS + mc_memory_bank;
932 base = calloc(total_memory_banks, sizeof(u64));
933 size = calloc(total_memory_banks, sizeof(u64));
935 /* fixup DT for the two GPP DDR banks */
936 for (i = 0; i < CONFIG_NR_DRAM_BANKS; i++) {
937 base[i] = gd->bd->bi_dram[i].start;
938 size[i] = gd->bd->bi_dram[i].size;
941 #ifdef CONFIG_RESV_RAM
942 /* reduce size if reserved memory is within this bank */
943 if (gd->arch.resv_ram >= base[0] &&
944 gd->arch.resv_ram < base[0] + size[0])
945 size[0] = gd->arch.resv_ram - base[0];
946 else if (gd->arch.resv_ram >= base[1] &&
947 gd->arch.resv_ram < base[1] + size[1])
948 size[1] = gd->arch.resv_ram - base[1];
951 if (mc_memory_base != 0) {
952 for (i = 0; i <= total_memory_banks; i++) {
953 if (base[i] == 0 && size[i] == 0) {
954 base[i] = mc_memory_base;
955 size[i] = mc_memory_size;
961 fdt_fixup_memory_banks(blob, base, size, total_memory_banks);
963 fdt_fsl_mc_fixup_iommu_map_entry(blob);
965 fsl_fdt_fixup_flash(blob);
967 #ifdef CONFIG_FSL_MC_ENET
968 fdt_fixup_board_enet(blob);
971 fdt_fixup_icid(blob);
974 fixup_ls1088ardb_pb_banner(blob);
979 #endif /* defined(CONFIG_SPL_BUILD) */
981 #ifdef CONFIG_TFABOOT
982 #ifdef CONFIG_MTD_NOR_FLASH
983 int is_flash_available(void)
985 char *env_hwconfig = env_get("hwconfig");
986 enum boot_src src = get_boot_src();
987 int is_nor_flash_available = 1;
990 case BOOT_SOURCE_IFC_NOR:
991 is_nor_flash_available = 1;
993 case BOOT_SOURCE_QSPI_NOR:
994 is_nor_flash_available = 0;
997 * In Case of SD boot,if qspi is defined in env_hwconfig
998 * disable nor flash probe.
1001 if (hwconfig_f("qspi", env_hwconfig))
1002 is_nor_flash_available = 0;
1005 return is_nor_flash_available;
1009 #ifdef CONFIG_ENV_IS_IN_SPI_FLASH
1010 void *env_sf_get_env_addr(void)
1012 return (void *)(CONFIG_SYS_FSL_QSPI_BASE + CONFIG_ENV_OFFSET);