1 // SPDX-License-Identifier: GPL-2.0+
3 * Copyright 2017-2018 NXP
14 #include <fdt_support.h>
15 #include <linux/libfdt.h>
16 #include <fsl-mc/fsl_mc.h>
17 #include <environment.h>
18 #include <asm/arch-fsl-layerscape/soc.h>
19 #include <asm/arch/ppa.h>
21 #include <asm/arch/fsl_serdes.h>
22 #include <asm/arch/soc.h>
24 #include "../common/qixis.h"
25 #include "ls1088a_qixis.h"
26 #include "../common/vid.h"
27 #include <fsl_immap.h>
29 DECLARE_GLOBAL_DATA_PTR;
31 int board_early_init_f(void)
33 #if defined(CONFIG_SYS_I2C_EARLY_INIT) && defined(CONFIG_TARGET_LS1088AQDS)
36 fsl_lsch3_early_init_f();
40 #ifdef CONFIG_FSL_QIXIS
41 unsigned long long get_qixis_addr(void)
43 unsigned long long addr;
45 if (gd->flags & GD_FLG_RELOC)
46 addr = QIXIS_BASE_PHYS;
48 addr = QIXIS_BASE_PHYS_EARLY;
51 * IFC address under 256MB is mapped to 0x30000000, any address above
52 * is mapped to 0x5_10000000 up to 4GB.
54 addr = addr > 0x10000000 ? addr + 0x500000000ULL : addr + 0x30000000;
60 #if defined(CONFIG_VID)
61 int init_func_vid(void)
63 if (adjust_vdd(0) < 0)
64 printf("core voltage not adjusted\n");
74 board_id = QIXIS_READ(id);
75 if (board_id == LS1088ARDB_PB_BOARD)
81 int fixup_ls1088ardb_pb_banner(void *fdt)
83 fdt_setprop_string(fdt, 0, "model", "LS1088ARDB-PB Board");
88 #if !defined(CONFIG_SPL_BUILD)
92 enum boot_src src = get_boot_src();
96 static const char *const freq[] = {"100", "125", "156.25",
100 #ifdef CONFIG_TARGET_LS1088AQDS
101 printf("Board: LS1088A-QDS, ");
104 printf("Board: LS1088ARDB-PB, ");
106 printf("Board: LS1088A-RDB, ");
109 sw = QIXIS_READ(arch);
110 printf("Board Arch: V%d, ", sw >> 4);
112 #ifdef CONFIG_TARGET_LS1088AQDS
113 printf("Board version: %c, boot from ", (sw & 0xf) + 'A' - 1);
115 printf("Board version: %c, boot from ", (sw & 0xf) + 'A');
118 memset((u8 *)buf, 0x00, ARRAY_SIZE(buf));
120 sw = QIXIS_READ(brdcfg[0]);
121 sw = (sw & QIXIS_LBMAP_MASK) >> QIXIS_LBMAP_SHIFT;
123 #ifdef CONFIG_TFABOOT
124 if (src == BOOT_SOURCE_SD_MMC)
127 #ifdef CONFIG_SD_BOOT
130 #endif /* CONFIG_TFABOOT */
132 #ifdef CONFIG_TARGET_LS1088AQDS
141 printf("vBank: %d\n", sw);
154 sw = QIXIS_READ(brdcfg[0]);
155 sw = (sw & QIXIS_QMAP_MASK) >> QIXIS_QMAP_SHIFT;
156 if (sw == 0 || sw == 4)
165 printf("invalid setting of SW%u\n", QIXIS_LBMAP_SWITCH);
169 #ifdef CONFIG_TARGET_LS1088AQDS
170 printf("FPGA: v%d (%s), build %d",
171 (int)QIXIS_READ(scver), qixis_read_tag(buf),
172 (int)qixis_read_minor());
173 /* the timestamp string contains "\n" at the end */
174 printf(" on %s", qixis_read_time(buf));
176 printf("CPLD: v%d.%d\n", QIXIS_READ(scver), QIXIS_READ(tagdata));
180 * Display the actual SERDES reference clocks as configured by the
181 * dip switches on the board. Note that the SWx registers could
182 * technically be set to force the reference clocks to match the
183 * values that the SERDES expects (or vice versa). For now, however,
184 * we just display both values and hope the user notices when they
187 puts("SERDES1 Reference : ");
188 sw = QIXIS_READ(brdcfg[2]);
189 clock = (sw >> 6) & 3;
190 printf("Clock1 = %sMHz ", freq[clock]);
191 clock = (sw >> 4) & 3;
192 printf("Clock2 = %sMHz", freq[clock]);
194 puts("\nSERDES2 Reference : ");
195 clock = (sw >> 2) & 3;
196 printf("Clock1 = %sMHz ", freq[clock]);
197 clock = (sw >> 0) & 3;
198 printf("Clock2 = %sMHz\n", freq[clock]);
204 bool if_board_diff_clk(void)
206 #ifdef CONFIG_TARGET_LS1088AQDS
207 u8 diff_conf = QIXIS_READ(brdcfg[11]);
208 return diff_conf & 0x40;
210 u8 diff_conf = QIXIS_READ(dutcfg[11]);
211 return diff_conf & 0x80;
215 unsigned long get_board_sys_clk(void)
217 u8 sysclk_conf = QIXIS_READ(brdcfg[1]);
219 switch (sysclk_conf & 0x0f) {
220 case QIXIS_SYSCLK_83:
222 case QIXIS_SYSCLK_100:
224 case QIXIS_SYSCLK_125:
226 case QIXIS_SYSCLK_133:
228 case QIXIS_SYSCLK_150:
230 case QIXIS_SYSCLK_160:
232 case QIXIS_SYSCLK_166:
239 unsigned long get_board_ddr_clk(void)
241 u8 ddrclk_conf = QIXIS_READ(brdcfg[1]);
243 if (if_board_diff_clk())
244 return get_board_sys_clk();
245 switch ((ddrclk_conf & 0x30) >> 4) {
246 case QIXIS_DDRCLK_100:
248 case QIXIS_DDRCLK_125:
250 case QIXIS_DDRCLK_133:
257 int select_i2c_ch_pca9547(u8 ch)
261 ret = i2c_write(I2C_MUX_PCA_ADDR_PRI, 0, 1, &ch, 1);
263 puts("PCA: failed to select proper channel\n");
270 #if !defined(CONFIG_SPL_BUILD)
271 void board_retimer_init(void)
275 /* Retimer is connected to I2C1_CH5 */
276 select_i2c_ch_pca9547(I2C_MUX_CH5);
278 /* Access to Control/Shared register */
280 i2c_write(I2C_RETIMER_ADDR, 0xff, 1, ®, 1);
282 /* Read device revision and ID */
283 i2c_read(I2C_RETIMER_ADDR, 1, 1, ®, 1);
284 debug("Retimer version id = 0x%x\n", reg);
286 /* Enable Broadcast. All writes target all channel register sets */
288 i2c_write(I2C_RETIMER_ADDR, 0xff, 1, ®, 1);
290 /* Reset Channel Registers */
291 i2c_read(I2C_RETIMER_ADDR, 0, 1, ®, 1);
293 i2c_write(I2C_RETIMER_ADDR, 0, 1, ®, 1);
295 /* Set data rate as 10.3125 Gbps */
297 i2c_write(I2C_RETIMER_ADDR, 0x60, 1, ®, 1);
299 i2c_write(I2C_RETIMER_ADDR, 0x61, 1, ®, 1);
301 i2c_write(I2C_RETIMER_ADDR, 0x62, 1, ®, 1);
303 i2c_write(I2C_RETIMER_ADDR, 0x63, 1, ®, 1);
305 i2c_write(I2C_RETIMER_ADDR, 0x64, 1, ®, 1);
307 /* Select VCO Divider to full rate (000) */
308 i2c_read(I2C_RETIMER_ADDR, 0x2F, 1, ®, 1);
311 i2c_write(I2C_RETIMER_ADDR, 0x2F, 1, ®, 1);
313 #ifdef CONFIG_TARGET_LS1088AQDS
314 /* Retimer is connected to I2C1_CH5 */
315 select_i2c_ch_pca9547(I2C_MUX_CH5);
317 /* Access to Control/Shared register */
319 i2c_write(I2C_RETIMER_ADDR2, 0xff, 1, ®, 1);
321 /* Read device revision and ID */
322 i2c_read(I2C_RETIMER_ADDR2, 1, 1, ®, 1);
323 debug("Retimer version id = 0x%x\n", reg);
325 /* Enable Broadcast. All writes target all channel register sets */
327 i2c_write(I2C_RETIMER_ADDR2, 0xff, 1, ®, 1);
329 /* Reset Channel Registers */
330 i2c_read(I2C_RETIMER_ADDR2, 0, 1, ®, 1);
332 i2c_write(I2C_RETIMER_ADDR2, 0, 1, ®, 1);
334 /* Set data rate as 10.3125 Gbps */
336 i2c_write(I2C_RETIMER_ADDR2, 0x60, 1, ®, 1);
338 i2c_write(I2C_RETIMER_ADDR2, 0x61, 1, ®, 1);
340 i2c_write(I2C_RETIMER_ADDR2, 0x62, 1, ®, 1);
342 i2c_write(I2C_RETIMER_ADDR2, 0x63, 1, ®, 1);
344 i2c_write(I2C_RETIMER_ADDR2, 0x64, 1, ®, 1);
346 /* Select VCO Divider to full rate (000) */
347 i2c_read(I2C_RETIMER_ADDR2, 0x2F, 1, ®, 1);
350 i2c_write(I2C_RETIMER_ADDR2, 0x2F, 1, ®, 1);
352 /*return the default channel*/
353 select_i2c_ch_pca9547(I2C_MUX_CH_DEFAULT);
356 #ifdef CONFIG_MISC_INIT_R
357 int misc_init_r(void)
359 #ifdef CONFIG_TARGET_LS1088ARDB
362 if (hwconfig("esdhc-force-sd")) {
363 brdcfg5 = QIXIS_READ(brdcfg[5]);
364 brdcfg5 &= ~BRDCFG5_SPISDHC_MASK;
365 brdcfg5 |= BRDCFG5_FORCE_SD;
366 QIXIS_WRITE(brdcfg[5], brdcfg5);
374 int i2c_multiplexer_select_vid_channel(u8 channel)
376 return select_i2c_ch_pca9547(channel);
379 #ifdef CONFIG_TARGET_LS1088AQDS
380 /* read the current value(SVDD) of the LTM Regulator Voltage */
381 int get_serdes_volt(void)
384 u8 chan = PWM_CHANNEL0;
386 /* Select the PAGE 0 using PMBus commands PAGE for VDD */
387 ret = i2c_write(I2C_SVDD_MONITOR_ADDR,
388 PMBUS_CMD_PAGE, 1, &chan, 1);
390 printf("VID: failed to select VDD Page 0\n");
394 /* Read the output voltage using PMBus command READ_VOUT */
395 ret = i2c_read(I2C_SVDD_MONITOR_ADDR,
396 PMBUS_CMD_READ_VOUT, 1, (void *)&vcode, 2);
398 printf("VID: failed to read the volatge\n");
405 int set_serdes_volt(int svdd)
408 u8 buff[5] = {0x04, PWM_CHANNEL0, PMBUS_CMD_VOUT_COMMAND,
409 svdd & 0xFF, (svdd & 0xFF00) >> 8};
411 /* Write the desired voltage code to the SVDD regulator */
412 ret = i2c_write(I2C_SVDD_MONITOR_ADDR,
413 PMBUS_CMD_PAGE_PLUS_WRITE, 1, (void *)&buff, 5);
415 printf("VID: I2C failed to write to the volatge regulator\n");
419 /* Wait for the volatge to get to the desired value */
421 vdd_last = get_serdes_volt();
423 printf("VID: Couldn't read sensor abort VID adjust\n");
426 } while (vdd_last != svdd);
431 int get_serdes_volt(void)
436 int set_serdes_volt(int svdd)
441 printf("SVDD changing of RDB\n");
443 /* Read the BRDCFG54 via CLPD */
444 ret = i2c_read(CONFIG_SYS_I2C_FPGA_ADDR,
445 QIXIS_BRDCFG4_OFFSET, 1, (void *)&brdcfg4, 1);
447 printf("VID: I2C failed to read the CPLD BRDCFG4\n");
451 brdcfg4 = brdcfg4 | 0x08;
453 /* Write to the BRDCFG4 */
454 ret = i2c_write(CONFIG_SYS_I2C_FPGA_ADDR,
455 QIXIS_BRDCFG4_OFFSET, 1, (void *)&brdcfg4, 1);
457 debug("VID: I2C failed to set the SVDD CPLD BRDCFG4\n");
461 /* Wait for the volatge to get to the desired value */
468 /* this function disables the SERDES, changes the SVDD Voltage and enables it*/
469 int board_adjust_vdd(int vdd)
473 debug("%s: vdd = %d\n", __func__, vdd);
475 /* Special settings to be performed when voltage is 900mV */
477 ret = setup_serdes_volt(vdd);
487 #if !defined(CONFIG_SPL_BUILD)
490 init_final_memctl_regs();
491 #if defined(CONFIG_TARGET_LS1088ARDB) && defined(CONFIG_FSL_MC_ENET)
492 u32 __iomem *irq_ccsr = (u32 __iomem *)ISC_BASE;
495 select_i2c_ch_pca9547(I2C_MUX_CH_DEFAULT);
496 board_retimer_init();
498 #ifdef CONFIG_ENV_IS_NOWHERE
499 gd->env_addr = (ulong)&default_environment[0];
502 #if defined(CONFIG_TARGET_LS1088ARDB) && defined(CONFIG_FSL_MC_ENET)
503 /* invert AQR105 IRQ pins polarity */
504 out_le32(irq_ccsr + IRQCR_OFFSET / 4, AQR105_IRQ_MASK);
507 #ifdef CONFIG_FSL_CAAM
510 #ifdef CONFIG_FSL_LS_PPA
516 void detail_board_ddr_info(void)
519 print_size(gd->bd->bi_dram[0].size + gd->bd->bi_dram[1].size, "");
523 #if defined(CONFIG_ARCH_MISC_INIT)
524 int arch_misc_init(void)
530 #ifdef CONFIG_FSL_MC_ENET
531 void fdt_fixup_board_enet(void *fdt)
535 offset = fdt_path_offset(fdt, "/fsl-mc");
538 offset = fdt_path_offset(fdt, "/fsl,dprc@0");
541 printf("%s: ERROR: fsl-mc node not found in device tree (error %d)\n",
546 if ((get_mc_boot_status() == 0) && (get_dpl_apply_status() == 0))
547 fdt_status_okay(fdt, offset);
549 fdt_status_fail(fdt, offset);
553 #ifdef CONFIG_OF_BOARD_SETUP
554 void fsl_fdt_fixup_flash(void *fdt)
557 #ifdef CONFIG_TFABOOT
558 u32 __iomem *dcfg_ccsr = (u32 __iomem *)DCFG_BASE;
563 * IFC-NOR and QSPI are muxed on SoC.
564 * So disable IFC node in dts if QSPI is enabled or
565 * disable QSPI node in dts in case QSPI is not enabled.
568 #ifdef CONFIG_TFABOOT
569 enum boot_src src = get_boot_src();
570 bool disable_ifc = false;
573 case BOOT_SOURCE_IFC_NOR:
576 case BOOT_SOURCE_QSPI_NOR:
580 val = in_le32(dcfg_ccsr + DCFG_RCWSR15 / 4);
581 if (DCFG_RCWSR15_IFCGRPABASE_QSPI == (val & (u32)0x3))
587 offset = fdt_path_offset(fdt, "/soc/ifc/nor");
590 offset = fdt_path_offset(fdt, "/ifc/nor");
592 offset = fdt_path_offset(fdt, "/soc/quadspi");
595 offset = fdt_path_offset(fdt, "/quadspi");
599 #ifdef CONFIG_FSL_QSPI
600 offset = fdt_path_offset(fdt, "/soc/ifc/nor");
603 offset = fdt_path_offset(fdt, "/ifc/nor");
605 offset = fdt_path_offset(fdt, "/soc/quadspi");
608 offset = fdt_path_offset(fdt, "/quadspi");
614 fdt_status_disabled(fdt, offset);
617 int ft_board_setup(void *blob, bd_t *bd)
620 u64 base[CONFIG_NR_DRAM_BANKS];
621 u64 size[CONFIG_NR_DRAM_BANKS];
623 ft_cpu_setup(blob, bd);
625 /* fixup DT for the two GPP DDR banks */
626 for (i = 0; i < CONFIG_NR_DRAM_BANKS; i++) {
627 base[i] = gd->bd->bi_dram[i].start;
628 size[i] = gd->bd->bi_dram[i].size;
631 #ifdef CONFIG_RESV_RAM
632 /* reduce size if reserved memory is within this bank */
633 if (gd->arch.resv_ram >= base[0] &&
634 gd->arch.resv_ram < base[0] + size[0])
635 size[0] = gd->arch.resv_ram - base[0];
636 else if (gd->arch.resv_ram >= base[1] &&
637 gd->arch.resv_ram < base[1] + size[1])
638 size[1] = gd->arch.resv_ram - base[1];
641 fdt_fixup_memory_banks(blob, base, size, CONFIG_NR_DRAM_BANKS);
643 fdt_fsl_mc_fixup_iommu_map_entry(blob);
645 fsl_fdt_fixup_flash(blob);
647 #ifdef CONFIG_FSL_MC_ENET
648 fdt_fixup_board_enet(blob);
649 err = fsl_mc_ldpaa_exit(bd);
654 fixup_ls1088ardb_pb_banner(blob);
659 #endif /* defined(CONFIG_SPL_BUILD) */
661 #ifdef CONFIG_TFABOOT
662 #ifdef CONFIG_MTD_NOR_FLASH
663 int is_flash_available(void)
665 char *env_hwconfig = env_get("hwconfig");
666 enum boot_src src = get_boot_src();
667 int is_nor_flash_available = 1;
670 case BOOT_SOURCE_IFC_NOR:
671 is_nor_flash_available = 1;
673 case BOOT_SOURCE_QSPI_NOR:
674 is_nor_flash_available = 0;
677 * In Case of SD boot,if qspi is defined in env_hwconfig
678 * disable nor flash probe.
681 if (hwconfig_f("qspi", env_hwconfig))
682 is_nor_flash_available = 0;
685 return is_nor_flash_available;
689 void *env_sf_get_env_addr(void)
691 return (void *)(CONFIG_SYS_FSL_QSPI_BASE + CONFIG_ENV_OFFSET);