board/freescale/ls1088a/ls1088a.c

   1 // SPDX-License-Identifier: GPL-2.0+
   2 /*
   3  * Copyright 2017-2018 NXP
   4  */
   5 #include <common.h>
   6 #include <env.h>
   7 #include <i2c.h>
   8 #include <malloc.h>
   9 #include <errno.h>
  10 #include <netdev.h>
  11 #include <fsl_ifc.h>
  12 #include <fsl_ddr.h>
  13 #include <fsl_sec.h>
  14 #include <asm/io.h>
  15 #include <fdt_support.h>
  16 #include <linux/libfdt.h>
  17 #include <fsl-mc/fsl_mc.h>
  18 #include <env_internal.h>
  19 #include <asm/arch-fsl-layerscape/soc.h>
  20 #include <asm/arch/ppa.h>
  21 #include <hwconfig.h>
  22 #include <asm/arch/fsl_serdes.h>
  23 #include <asm/arch/soc.h>
  24
  25 #include "../common/qixis.h"
  26 #include "ls1088a_qixis.h"
  27 #include "../common/vid.h"
  28 #include <fsl_immap.h>
  29
  30 DECLARE_GLOBAL_DATA_PTR;
  31
  32 #ifdef CONFIG_TARGET_LS1088AQDS
  33 #ifdef CONFIG_TFABOOT
  34 struct ifc_regs ifc_cfg_ifc_nor_boot[CONFIG_SYS_FSL_IFC_BANK_COUNT] = {
  35         {
  36                 "nor0",
  37                 CONFIG_SYS_NOR0_CSPR_EARLY,
  38                 CONFIG_SYS_NOR0_CSPR_EXT,
  39                 CONFIG_SYS_NOR_AMASK,
  40                 CONFIG_SYS_NOR_CSOR,
  41                 {
  42                         CONFIG_SYS_NOR_FTIM0,
  43                         CONFIG_SYS_NOR_FTIM1,
  44                         CONFIG_SYS_NOR_FTIM2,
  45                         CONFIG_SYS_NOR_FTIM3
  46                 },
  47                 0,
  48                 CONFIG_SYS_NOR0_CSPR,
  49                 0,
  50         },
  51         {
  52                 "nor1",
  53                 CONFIG_SYS_NOR1_CSPR_EARLY,
  54                 CONFIG_SYS_NOR0_CSPR_EXT,
  55                 CONFIG_SYS_NOR_AMASK_EARLY,
  56                 CONFIG_SYS_NOR_CSOR,
  57                 {
  58                         CONFIG_SYS_NOR_FTIM0,
  59                         CONFIG_SYS_NOR_FTIM1,
  60                         CONFIG_SYS_NOR_FTIM2,
  61                         CONFIG_SYS_NOR_FTIM3
  62                 },
  63                 0,
  64                 CONFIG_SYS_NOR1_CSPR,
  65                 CONFIG_SYS_NOR_AMASK,
  66         },
  67         {
  68                 "nand",
  69                 CONFIG_SYS_NAND_CSPR,
  70                 CONFIG_SYS_NAND_CSPR_EXT,
  71                 CONFIG_SYS_NAND_AMASK,
  72                 CONFIG_SYS_NAND_CSOR,
  73                 {
  74                         CONFIG_SYS_NAND_FTIM0,
  75                         CONFIG_SYS_NAND_FTIM1,
  76                         CONFIG_SYS_NAND_FTIM2,
  77                         CONFIG_SYS_NAND_FTIM3
  78                 },
  79         },
  80         {
  81                 "fpga",
  82                 CONFIG_SYS_FPGA_CSPR,
  83                 CONFIG_SYS_FPGA_CSPR_EXT,
  84                 SYS_FPGA_AMASK,
  85                 CONFIG_SYS_FPGA_CSOR,
  86                 {
  87                         SYS_FPGA_CS_FTIM0,
  88                         SYS_FPGA_CS_FTIM1,
  89                         SYS_FPGA_CS_FTIM2,
  90                         SYS_FPGA_CS_FTIM3
  91                 },
  92                 0,
  93                 SYS_FPGA_CSPR_FINAL,
  94                 0,
  95         }
  96 };
  97
  98 struct ifc_regs ifc_cfg_qspi_nor_boot[CONFIG_SYS_FSL_IFC_BANK_COUNT] = {
  99         {
 100                 "nand",
 101                 CONFIG_SYS_NAND_CSPR,
 102                 CONFIG_SYS_NAND_CSPR_EXT,
 103                 CONFIG_SYS_NAND_AMASK,
 104                 CONFIG_SYS_NAND_CSOR,
 105                 {
 106                         CONFIG_SYS_NAND_FTIM0,
 107                         CONFIG_SYS_NAND_FTIM1,
 108                         CONFIG_SYS_NAND_FTIM2,
 109                         CONFIG_SYS_NAND_FTIM3
 110                 },
 111         },
 112         {
 113                 "reserved",
 114         },
 115         {
 116                 "fpga",
 117                 CONFIG_SYS_FPGA_CSPR,
 118                 CONFIG_SYS_FPGA_CSPR_EXT,
 119                 SYS_FPGA_AMASK,
 120                 CONFIG_SYS_FPGA_CSOR,
 121                 {
 122                         SYS_FPGA_CS_FTIM0,
 123                         SYS_FPGA_CS_FTIM1,
 124                         SYS_FPGA_CS_FTIM2,
 125                         SYS_FPGA_CS_FTIM3
 126                 },
 127                 0,
 128                 SYS_FPGA_CSPR_FINAL,
 129                 0,
 130         }
 131 };
 132
 133 void ifc_cfg_boot_info(struct ifc_regs_info *regs_info)
 134 {
 135         enum boot_src src = get_boot_src();
 136
 137         if (src == BOOT_SOURCE_QSPI_NOR)
 138                 regs_info->regs = ifc_cfg_qspi_nor_boot;
 139         else
 140                 regs_info->regs = ifc_cfg_ifc_nor_boot;
 141
 142         regs_info->cs_size = CONFIG_SYS_FSL_IFC_BANK_COUNT;
 143 }
 144 #endif /* CONFIG_TFABOOT */
 145 #endif /* CONFIG_TARGET_LS1088AQDS */
 146
 147 int board_early_init_f(void)
 148 {
 149 #if defined(CONFIG_SYS_I2C_EARLY_INIT) && defined(CONFIG_TARGET_LS1088AQDS)
 150         i2c_early_init_f();
 151 #endif
 152         fsl_lsch3_early_init_f();
 153         return 0;
 154 }
 155
 156 #ifdef CONFIG_FSL_QIXIS
 157 unsigned long long get_qixis_addr(void)
 158 {
 159         unsigned long long addr;
 160
 161         if (gd->flags & GD_FLG_RELOC)
 162                 addr = QIXIS_BASE_PHYS;
 163         else
 164                 addr = QIXIS_BASE_PHYS_EARLY;
 165
 166         /*
 167          * IFC address under 256MB is mapped to 0x30000000, any address above
 168          * is mapped to 0x5_10000000 up to 4GB.
 169          */
 170         addr = addr  > 0x10000000 ? addr + 0x500000000ULL : addr + 0x30000000;
 171
 172         return addr;
 173 }
 174 #endif
 175
 176 #if defined(CONFIG_VID)
 177 int init_func_vid(void)
 178 {
 179         if (adjust_vdd(0) < 0)
 180                 printf("core voltage not adjusted\n");
 181
 182         return 0;
 183 }
 184 #endif
 185
 186 int is_pb_board(void)
 187 {
 188         u8 board_id;
 189
 190         board_id = QIXIS_READ(id);
 191         if (board_id == LS1088ARDB_PB_BOARD)
 192                 return 1;
 193         else
 194                 return 0;
 195 }
 196
 197 int fixup_ls1088ardb_pb_banner(void *fdt)
 198 {
 199         fdt_setprop_string(fdt, 0, "model", "LS1088ARDB-PB Board");
 200
 201         return 0;
 202 }
 203
 204 #if !defined(CONFIG_SPL_BUILD)
 205 int checkboard(void)
 206 {
 207 #ifdef CONFIG_TFABOOT
 208         enum boot_src src = get_boot_src();
 209 #endif
 210         char buf[64];
 211         u8 sw;
 212         static const char *const freq[] = {"100", "125", "156.25",
 213                                             "100 separate SSCG"};
 214         int clock;
 215
 216 #ifdef CONFIG_TARGET_LS1088AQDS
 217         printf("Board: LS1088A-QDS, ");
 218 #else
 219         if (is_pb_board())
 220                 printf("Board: LS1088ARDB-PB, ");
 221         else
 222                 printf("Board: LS1088A-RDB, ");
 223 #endif
 224
 225         sw = QIXIS_READ(arch);
 226         printf("Board Arch: V%d, ", sw >> 4);
 227
 228 #ifdef CONFIG_TARGET_LS1088AQDS
 229         printf("Board version: %c, boot from ", (sw & 0xf) + 'A' - 1);
 230 #else
 231         printf("Board version: %c, boot from ", (sw & 0xf) + 'A');
 232 #endif
 233
 234         memset((u8 *)buf, 0x00, ARRAY_SIZE(buf));
 235
 236         sw = QIXIS_READ(brdcfg[0]);
 237         sw = (sw & QIXIS_LBMAP_MASK) >> QIXIS_LBMAP_SHIFT;
 238
 239 #ifdef CONFIG_TFABOOT
 240         if (src == BOOT_SOURCE_SD_MMC)
 241                 puts("SD card\n");
 242 #else
 243 #ifdef CONFIG_SD_BOOT
 244         puts("SD card\n");
 245 #endif
 246 #endif /* CONFIG_TFABOOT */
 247         switch (sw) {
 248 #ifdef CONFIG_TARGET_LS1088AQDS
 249         case 0:
 250         case 1:
 251         case 2:
 252         case 3:
 253         case 4:
 254         case 5:
 255         case 6:
 256         case 7:
 257                 printf("vBank: %d\n", sw);
 258                 break;
 259         case 8:
 260                 puts("PromJet\n");
 261                 break;
 262         case 15:
 263                 puts("IFCCard\n");
 264                 break;
 265         case 14:
 266 #else
 267         case 0:
 268 #endif
 269                 puts("QSPI:");
 270                 sw = QIXIS_READ(brdcfg[0]);
 271                 sw = (sw & QIXIS_QMAP_MASK) >> QIXIS_QMAP_SHIFT;
 272                 if (sw == 0 || sw == 4)
 273                         puts("0\n");
 274                 else if (sw == 1)
 275                         puts("1\n");
 276                 else
 277                         puts("EMU\n");
 278                 break;
 279
 280         default:
 281                 printf("invalid setting of SW%u\n", QIXIS_LBMAP_SWITCH);
 282                 break;
 283         }
 284
 285 #ifdef CONFIG_TARGET_LS1088AQDS
 286         printf("FPGA: v%d (%s), build %d",
 287                (int)QIXIS_READ(scver), qixis_read_tag(buf),
 288                (int)qixis_read_minor());
 289         /* the timestamp string contains "\n" at the end */
 290         printf(" on %s", qixis_read_time(buf));
 291 #else
 292         printf("CPLD: v%d.%d\n", QIXIS_READ(scver), QIXIS_READ(tagdata));
 293 #endif
 294
 295         /*
 296          * Display the actual SERDES reference clocks as configured by the
 297          * dip switches on the board.  Note that the SWx registers could
 298          * technically be set to force the reference clocks to match the
 299          * values that the SERDES expects (or vice versa).  For now, however,
 300          * we just display both values and hope the user notices when they
 301          * don't match.
 302          */
 303         puts("SERDES1 Reference : ");
 304         sw = QIXIS_READ(brdcfg[2]);
 305         clock = (sw >> 6) & 3;
 306         printf("Clock1 = %sMHz ", freq[clock]);
 307         clock = (sw >> 4) & 3;
 308         printf("Clock2 = %sMHz", freq[clock]);
 309
 310         puts("\nSERDES2 Reference : ");
 311         clock = (sw >> 2) & 3;
 312         printf("Clock1 = %sMHz ", freq[clock]);
 313         clock = (sw >> 0) & 3;
 314         printf("Clock2 = %sMHz\n", freq[clock]);
 315
 316         return 0;
 317 }
 318 #endif
 319
 320 bool if_board_diff_clk(void)
 321 {
 322 #ifdef CONFIG_TARGET_LS1088AQDS
 323         u8 diff_conf = QIXIS_READ(brdcfg[11]);
 324         return diff_conf & 0x40;
 325 #else
 326         u8 diff_conf = QIXIS_READ(dutcfg[11]);
 327         return diff_conf & 0x80;
 328 #endif
 329 }
 330
 331 unsigned long get_board_sys_clk(void)
 332 {
 333         u8 sysclk_conf = QIXIS_READ(brdcfg[1]);
 334
 335         switch (sysclk_conf & 0x0f) {
 336         case QIXIS_SYSCLK_83:
 337                 return 83333333;
 338         case QIXIS_SYSCLK_100:
 339                 return 100000000;
 340         case QIXIS_SYSCLK_125:
 341                 return 125000000;
 342         case QIXIS_SYSCLK_133:
 343                 return 133333333;
 344         case QIXIS_SYSCLK_150:
 345                 return 150000000;
 346         case QIXIS_SYSCLK_160:
 347                 return 160000000;
 348         case QIXIS_SYSCLK_166:
 349                 return 166666666;
 350         }
 351
 352         return 66666666;
 353 }
 354
 355 unsigned long get_board_ddr_clk(void)
 356 {
 357         u8 ddrclk_conf = QIXIS_READ(brdcfg[1]);
 358
 359         if (if_board_diff_clk())
 360                 return get_board_sys_clk();
 361         switch ((ddrclk_conf & 0x30) >> 4) {
 362         case QIXIS_DDRCLK_100:
 363                 return 100000000;
 364         case QIXIS_DDRCLK_125:
 365                 return 125000000;
 366         case QIXIS_DDRCLK_133:
 367                 return 133333333;
 368         }
 369
 370         return 66666666;
 371 }
 372
 373 int select_i2c_ch_pca9547(u8 ch)
 374 {
 375         int ret;
 376
 377 #ifndef CONFIG_DM_I2C
 378         ret = i2c_write(I2C_MUX_PCA_ADDR_PRI, 0, 1, &ch, 1);
 379 #else
 380         struct udevice *dev;
 381
 382         ret = i2c_get_chip_for_busnum(0, I2C_MUX_PCA_ADDR_PRI, 1, &dev);
 383         if (!ret)
 384                 ret = dm_i2c_write(dev, 0, &ch, 1);
 385 #endif
 386         if (ret) {
 387                 puts("PCA: failed to select proper channel\n");
 388                 return ret;
 389         }
 390
 391         return 0;
 392 }
 393
 394 #if !defined(CONFIG_SPL_BUILD)
 395 void board_retimer_init(void)
 396 {
 397         u8 reg;
 398
 399         /* Retimer is connected to I2C1_CH5 */
 400         select_i2c_ch_pca9547(I2C_MUX_CH5);
 401
 402         /* Access to Control/Shared register */
 403         reg = 0x0;
 404 #ifndef CONFIG_DM_I2C
 405         i2c_write(I2C_RETIMER_ADDR, 0xff, 1, &reg, 1);
 406 #else
 407         struct udevice *dev;
 408
 409         i2c_get_chip_for_busnum(0, I2C_RETIMER_ADDR, 1, &dev);
 410         dm_i2c_write(dev, 0xff, &reg, 1);
 411 #endif
 412
 413         /* Read device revision and ID */
 414 #ifndef CONFIG_DM_I2C
 415         i2c_read(I2C_RETIMER_ADDR, 1, 1, &reg, 1);
 416 #else
 417         dm_i2c_read(dev, 1, &reg, 1);
 418 #endif
 419         debug("Retimer version id = 0x%x\n", reg);
 420
 421         /* Enable Broadcast. All writes target all channel register sets */
 422         reg = 0x0c;
 423 #ifndef CONFIG_DM_I2C
 424         i2c_write(I2C_RETIMER_ADDR, 0xff, 1, &reg, 1);
 425 #else
 426         dm_i2c_write(dev, 0xff, &reg, 1);
 427 #endif
 428
 429         /* Reset Channel Registers */
 430 #ifndef CONFIG_DM_I2C
 431         i2c_read(I2C_RETIMER_ADDR, 0, 1, &reg, 1);
 432 #else
 433         dm_i2c_read(dev, 0, &reg, 1);
 434 #endif
 435         reg |= 0x4;
 436 #ifndef CONFIG_DM_I2C
 437         i2c_write(I2C_RETIMER_ADDR, 0, 1, &reg, 1);
 438 #else
 439         dm_i2c_write(dev, 0, &reg, 1);
 440 #endif
 441
 442         /* Set data rate as 10.3125 Gbps */
 443         reg = 0x90;
 444 #ifndef CONFIG_DM_I2C
 445         i2c_write(I2C_RETIMER_ADDR, 0x60, 1, &reg, 1);
 446 #else
 447         dm_i2c_write(dev, 0x60, &reg, 1);
 448 #endif
 449         reg = 0xb3;
 450 #ifndef CONFIG_DM_I2C
 451         i2c_write(I2C_RETIMER_ADDR, 0x61, 1, &reg, 1);
 452 #else
 453         dm_i2c_write(dev, 0x61, &reg, 1);
 454 #endif
 455         reg = 0x90;
 456 #ifndef CONFIG_DM_I2C
 457         i2c_write(I2C_RETIMER_ADDR, 0x62, 1, &reg, 1);
 458 #else
 459         dm_i2c_write(dev, 0x62, &reg, 1);
 460 #endif
 461         reg = 0xb3;
 462 #ifndef CONFIG_DM_I2C
 463         i2c_write(I2C_RETIMER_ADDR, 0x63, 1, &reg, 1);
 464 #else
 465         dm_i2c_write(dev, 0x63, &reg, 1);
 466 #endif
 467         reg = 0xcd;
 468 #ifndef CONFIG_DM_I2C
 469         i2c_write(I2C_RETIMER_ADDR, 0x64, 1, &reg, 1);
 470 #else
 471         dm_i2c_write(dev, 0x64, &reg, 1);
 472 #endif
 473
 474         /* Select VCO Divider to full rate (000) */
 475 #ifndef CONFIG_DM_I2C
 476         i2c_read(I2C_RETIMER_ADDR, 0x2F, 1, &reg, 1);
 477 #else
 478         dm_i2c_read(dev, 0x2F, &reg, 1);
 479 #endif
 480         reg &= 0x0f;
 481         reg |= 0x70;
 482 #ifndef CONFIG_DM_I2C
 483         i2c_write(I2C_RETIMER_ADDR, 0x2F, 1, &reg, 1);
 484 #else
 485         dm_i2c_write(dev, 0x2F, &reg, 1);
 486 #endif
 487
 488 #ifdef  CONFIG_TARGET_LS1088AQDS
 489         /* Retimer is connected to I2C1_CH5 */
 490         select_i2c_ch_pca9547(I2C_MUX_CH5);
 491
 492         /* Access to Control/Shared register */
 493         reg = 0x0;
 494 #ifndef CONFIG_DM_I2C
 495         i2c_write(I2C_RETIMER_ADDR2, 0xff, 1, &reg, 1);
 496 #else
 497         i2c_get_chip_for_busnum(0, I2C_RETIMER_ADDR2, 1, &dev);
 498         dm_i2c_write(dev, 0xff, &reg, 1);
 499 #endif
 500
 501         /* Read device revision and ID */
 502 #ifndef CONFIG_DM_I2C
 503         i2c_read(I2C_RETIMER_ADDR2, 1, 1, &reg, 1);
 504 #else
 505         dm_i2c_read(dev, 1, &reg, 1);
 506 #endif
 507         debug("Retimer version id = 0x%x\n", reg);
 508
 509         /* Enable Broadcast. All writes target all channel register sets */
 510         reg = 0x0c;
 511 #ifndef CONFIG_DM_I2C
 512         i2c_write(I2C_RETIMER_ADDR2, 0xff, 1, &reg, 1);
 513 #else
 514         dm_i2c_write(dev, 0xff, &reg, 1);
 515 #endif
 516
 517         /* Reset Channel Registers */
 518 #ifndef CONFIG_DM_I2C
 519         i2c_read(I2C_RETIMER_ADDR2, 0, 1, &reg, 1);
 520 #else
 521         dm_i2c_read(dev, 0, &reg, 1);
 522 #endif
 523         reg |= 0x4;
 524 #ifndef CONFIG_DM_I2C
 525         i2c_write(I2C_RETIMER_ADDR2, 0, 1, &reg, 1);
 526 #else
 527         dm_i2c_write(dev, 0, &reg, 1);
 528 #endif
 529
 530         /* Set data rate as 10.3125 Gbps */
 531         reg = 0x90;
 532 #ifndef CONFIG_DM_I2C
 533         i2c_write(I2C_RETIMER_ADDR2, 0x60, 1, &reg, 1);
 534 #else
 535         dm_i2c_write(dev, 0x60, &reg, 1);
 536 #endif
 537         reg = 0xb3;
 538 #ifndef CONFIG_DM_I2C
 539         i2c_write(I2C_RETIMER_ADDR2, 0x61, 1, &reg, 1);
 540 #else
 541         dm_i2c_write(dev, 0x61, &reg, 1);
 542 #endif
 543         reg = 0x90;
 544 #ifndef CONFIG_DM_I2C
 545         i2c_write(I2C_RETIMER_ADDR2, 0x62, 1, &reg, 1);
 546 #else
 547         dm_i2c_write(dev, 0x62, &reg, 1);
 548 #endif
 549         reg = 0xb3;
 550 #ifndef CONFIG_DM_I2C
 551         i2c_write(I2C_RETIMER_ADDR2, 0x63, 1, &reg, 1);
 552 #else
 553         dm_i2c_write(dev, 0x63, &reg, 1);
 554 #endif
 555         reg = 0xcd;
 556 #ifndef CONFIG_DM_I2C
 557         i2c_write(I2C_RETIMER_ADDR2, 0x64, 1, &reg, 1);
 558 #else
 559         dm_i2c_write(dev, 0x64, &reg, 1);
 560 #endif
 561
 562         /* Select VCO Divider to full rate (000) */
 563 #ifndef CONFIG_DM_I2C
 564         i2c_read(I2C_RETIMER_ADDR2, 0x2F, 1, &reg, 1);
 565 #else
 566         dm_i2c_read(dev, 0x2F, &reg, 1);
 567 #endif
 568         reg &= 0x0f;
 569         reg |= 0x70;
 570 #ifndef CONFIG_DM_I2C
 571         i2c_write(I2C_RETIMER_ADDR2, 0x2F, 1, &reg, 1);
 572 #else
 573         dm_i2c_write(dev, 0x2F, &reg, 1);
 574 #endif
 575
 576 #endif
 577         /*return the default channel*/
 578         select_i2c_ch_pca9547(I2C_MUX_CH_DEFAULT);
 579 }
 580
 581 #ifdef CONFIG_MISC_INIT_R
 582 int misc_init_r(void)
 583 {
 584 #ifdef CONFIG_TARGET_LS1088ARDB
 585         u8 brdcfg5;
 586
 587         if (hwconfig("esdhc-force-sd")) {
 588                 brdcfg5 = QIXIS_READ(brdcfg[5]);
 589                 brdcfg5 &= ~BRDCFG5_SPISDHC_MASK;
 590                 brdcfg5 |= BRDCFG5_FORCE_SD;
 591                 QIXIS_WRITE(brdcfg[5], brdcfg5);
 592         }
 593 #endif
 594
 595 #ifdef CONFIG_TARGET_LS1088AQDS
 596          u8 brdcfg4, brdcfg5;
 597
 598         if (hwconfig("dspi-on-board")) {
 599                 brdcfg4 = QIXIS_READ(brdcfg[4]);
 600                 brdcfg4 &= ~BRDCFG4_USBOSC_MASK;
 601                 brdcfg4 |= BRDCFG4_SPI;
 602                 QIXIS_WRITE(brdcfg[4], brdcfg4);
 603
 604                 brdcfg5 = QIXIS_READ(brdcfg[5]);
 605                 brdcfg5 &= ~BRDCFG5_SPR_MASK;
 606                 brdcfg5 |= BRDCFG5_SPI_ON_BOARD;
 607                 QIXIS_WRITE(brdcfg[5], brdcfg5);
 608         } else if (hwconfig("dspi-off-board")) {
 609                 brdcfg4 = QIXIS_READ(brdcfg[4]);
 610                 brdcfg4 &= ~BRDCFG4_USBOSC_MASK;
 611                 brdcfg4 |= BRDCFG4_SPI;
 612                 QIXIS_WRITE(brdcfg[4], brdcfg4);
 613
 614                 brdcfg5 = QIXIS_READ(brdcfg[5]);
 615                 brdcfg5 &= ~BRDCFG5_SPR_MASK;
 616                 brdcfg5 |= BRDCFG5_SPI_OFF_BOARD;
 617                 QIXIS_WRITE(brdcfg[5], brdcfg5);
 618         }
 619 #endif
 620         return 0;
 621 }
 622 #endif
 623 #endif
 624
 625 int i2c_multiplexer_select_vid_channel(u8 channel)
 626 {
 627         return select_i2c_ch_pca9547(channel);
 628 }
 629
 630 #ifdef CONFIG_TARGET_LS1088AQDS
 631 /* read the current value(SVDD) of the LTM Regulator Voltage */
 632 int get_serdes_volt(void)
 633 {
 634         int  ret, vcode = 0;
 635         u8 chan = PWM_CHANNEL0;
 636
 637         /* Select the PAGE 0 using PMBus commands PAGE for VDD */
 638 #ifndef CONFIG_DM_I2C
 639         ret = i2c_write(I2C_SVDD_MONITOR_ADDR,
 640                         PMBUS_CMD_PAGE, 1, &chan, 1);
 641 #else
 642         struct udevice *dev;
 643
 644         ret = i2c_get_chip_for_busnum(0, I2C_SVDD_MONITOR_ADDR, 1, &dev);
 645         if (!ret)
 646                 ret = dm_i2c_write(dev, PMBUS_CMD_PAGE,
 647                                    &chan, 1);
 648 #endif
 649
 650         if (ret) {
 651                 printf("VID: failed to select VDD Page 0\n");
 652                 return ret;
 653         }
 654
 655         /* Read the output voltage using PMBus command READ_VOUT */
 656 #ifndef CONFIG_DM_I2C
 657         ret = i2c_read(I2C_SVDD_MONITOR_ADDR,
 658                        PMBUS_CMD_READ_VOUT, 1, (void *)&vcode, 2);
 659 #else
 660         dm_i2c_read(dev, PMBUS_CMD_READ_VOUT, (void *)&vcode, 2);
 661 #endif
 662         if (ret) {
 663                 printf("VID: failed to read the volatge\n");
 664                 return ret;
 665         }
 666
 667         return vcode;
 668 }
 669
 670 int set_serdes_volt(int svdd)
 671 {
 672         int ret, vdd_last;
 673         u8 buff[5] = {0x04, PWM_CHANNEL0, PMBUS_CMD_VOUT_COMMAND,
 674                         svdd & 0xFF, (svdd & 0xFF00) >> 8};
 675
 676         /* Write the desired voltage code to the SVDD regulator */
 677 #ifndef CONFIG_DM_I2C
 678         ret = i2c_write(I2C_SVDD_MONITOR_ADDR,
 679                         PMBUS_CMD_PAGE_PLUS_WRITE, 1, (void *)&buff, 5);
 680 #else
 681         struct udevice *dev;
 682
 683         ret = i2c_get_chip_for_busnum(0, I2C_SVDD_MONITOR_ADDR, 1, &dev);
 684         if (!ret)
 685                 ret = dm_i2c_write(dev, PMBUS_CMD_PAGE_PLUS_WRITE,
 686                                    (void *)&buff, 5);
 687 #endif
 688         if (ret) {
 689                 printf("VID: I2C failed to write to the volatge regulator\n");
 690                 return -1;
 691         }
 692
 693         /* Wait for the volatge to get to the desired value */
 694         do {
 695                 vdd_last = get_serdes_volt();
 696                 if (vdd_last < 0) {
 697                         printf("VID: Couldn't read sensor abort VID adjust\n");
 698                         return -1;
 699                 }
 700         } while (vdd_last != svdd);
 701
 702         return 1;
 703 }
 704 #else
 705 int get_serdes_volt(void)
 706 {
 707         return 0;
 708 }
 709
 710 int set_serdes_volt(int svdd)
 711 {
 712         int ret;
 713         u8 brdcfg4;
 714
 715         printf("SVDD changing of RDB\n");
 716
 717         /* Read the BRDCFG54 via CLPD */
 718 #ifndef CONFIG_DM_I2C
 719         ret = i2c_read(CONFIG_SYS_I2C_FPGA_ADDR,
 720                        QIXIS_BRDCFG4_OFFSET, 1, (void *)&brdcfg4, 1);
 721 #else
 722         struct udevice *dev;
 723
 724         ret = i2c_get_chip_for_busnum(0, CONFIG_SYS_I2C_FPGA_ADDR, 1, &dev);
 725         if (!ret)
 726                 ret = dm_i2c_read(dev, QIXIS_BRDCFG4_OFFSET,
 727                                   (void *)&brdcfg4, 1);
 728 #endif
 729
 730         if (ret) {
 731                 printf("VID: I2C failed to read the CPLD BRDCFG4\n");
 732                 return -1;
 733         }
 734
 735         brdcfg4 = brdcfg4 | 0x08;
 736
 737         /* Write to the BRDCFG4 */
 738 #ifndef CONFIG_DM_I2C
 739         ret = i2c_write(CONFIG_SYS_I2C_FPGA_ADDR,
 740                         QIXIS_BRDCFG4_OFFSET, 1, (void *)&brdcfg4, 1);
 741 #else
 742         ret = dm_i2c_write(dev, QIXIS_BRDCFG4_OFFSET,
 743                            (void *)&brdcfg4, 1);
 744 #endif
 745
 746         if (ret) {
 747                 debug("VID: I2C failed to set the SVDD CPLD BRDCFG4\n");
 748                 return -1;
 749         }
 750
 751         /* Wait for the volatge to get to the desired value */
 752         udelay(10000);
 753
 754         return 1;
 755 }
 756 #endif
 757
 758 /* this function disables the SERDES, changes the SVDD Voltage and enables it*/
 759 int board_adjust_vdd(int vdd)
 760 {
 761         int ret = 0;
 762
 763         debug("%s: vdd = %d\n", __func__, vdd);
 764
 765         /* Special settings to be performed when voltage is 900mV */
 766         if (vdd == 900) {
 767                 ret = setup_serdes_volt(vdd);
 768                 if (ret < 0) {
 769                         ret = -1;
 770                         goto exit;
 771                 }
 772         }
 773 exit:
 774         return ret;
 775 }
 776
 777 #if !defined(CONFIG_SPL_BUILD)
 778 int board_init(void)
 779 {
 780         init_final_memctl_regs();
 781 #if defined(CONFIG_TARGET_LS1088ARDB) && defined(CONFIG_FSL_MC_ENET)
 782         u32 __iomem *irq_ccsr = (u32 __iomem *)ISC_BASE;
 783 #endif
 784
 785         select_i2c_ch_pca9547(I2C_MUX_CH_DEFAULT);
 786         board_retimer_init();
 787
 788 #ifdef CONFIG_ENV_IS_NOWHERE
 789         gd->env_addr = (ulong)&default_environment[0];
 790 #endif
 791
 792 #if defined(CONFIG_TARGET_LS1088ARDB) && defined(CONFIG_FSL_MC_ENET)
 793         /* invert AQR105 IRQ pins polarity */
 794         out_le32(irq_ccsr + IRQCR_OFFSET / 4, AQR105_IRQ_MASK);
 795 #endif
 796
 797 #ifdef CONFIG_FSL_CAAM
 798         sec_init();
 799 #endif
 800 #ifdef CONFIG_FSL_LS_PPA
 801         ppa_init();
 802 #endif
 803         return 0;
 804 }
 805
 806 void detail_board_ddr_info(void)
 807 {
 808         puts("\nDDR    ");
 809         print_size(gd->bd->bi_dram[0].size + gd->bd->bi_dram[1].size, "");
 810         print_ddr_info(0);
 811 }
 812
 813 #if defined(CONFIG_ARCH_MISC_INIT)
 814 int arch_misc_init(void)
 815 {
 816         return 0;
 817 }
 818 #endif
 819
 820 #ifdef CONFIG_FSL_MC_ENET
 821 void board_quiesce_devices(void)
 822 {
 823         fsl_mc_ldpaa_exit(gd->bd);
 824 }
 825
 826 void fdt_fixup_board_enet(void *fdt)
 827 {
 828         int offset;
 829
 830         offset = fdt_path_offset(fdt, "/fsl-mc");
 831
 832         if (offset < 0)
 833                 offset = fdt_path_offset(fdt, "/soc/fsl-mc");
 834
 835         if (offset < 0) {
 836                 printf("%s: ERROR: fsl-mc node not found in device tree (error %d)\n",
 837                        __func__, offset);
 838                 return;
 839         }
 840
 841         if (get_mc_boot_status() == 0 &&
 842             (is_lazy_dpl_addr_valid() || get_dpl_apply_status() == 0))
 843                 fdt_status_okay(fdt, offset);
 844         else
 845                 fdt_status_fail(fdt, offset);
 846 }
 847 #endif
 848
 849 #ifdef CONFIG_OF_BOARD_SETUP
 850 void fsl_fdt_fixup_flash(void *fdt)
 851 {
 852         int offset;
 853 #ifdef CONFIG_TFABOOT
 854         u32 __iomem *dcfg_ccsr = (u32 __iomem *)DCFG_BASE;
 855         u32 val;
 856 #endif
 857
 858 /*
 859  * IFC-NOR and QSPI are muxed on SoC.
 860  * So disable IFC node in dts if QSPI is enabled or
 861  * disable QSPI node in dts in case QSPI is not enabled.
 862  */
 863
 864 #ifdef CONFIG_TFABOOT
 865         enum boot_src src = get_boot_src();
 866         bool disable_ifc = false;
 867
 868         switch (src) {
 869         case BOOT_SOURCE_IFC_NOR:
 870                 disable_ifc = false;
 871                 break;
 872         case BOOT_SOURCE_QSPI_NOR:
 873                 disable_ifc = true;
 874                 break;
 875         default:
 876                 val = in_le32(dcfg_ccsr + DCFG_RCWSR15 / 4);
 877                 if (DCFG_RCWSR15_IFCGRPABASE_QSPI == (val & (u32)0x3))
 878                         disable_ifc = true;
 879                 break;
 880         }
 881
 882         if (disable_ifc) {
 883                 offset = fdt_path_offset(fdt, "/soc/ifc/nor");
 884
 885                 if (offset < 0)
 886                         offset = fdt_path_offset(fdt, "/ifc/nor");
 887         } else {
 888                 offset = fdt_path_offset(fdt, "/soc/quadspi");
 889
 890                 if (offset < 0)
 891                         offset = fdt_path_offset(fdt, "/quadspi");
 892         }
 893
 894 #else
 895 #ifdef CONFIG_FSL_QSPI
 896         offset = fdt_path_offset(fdt, "/soc/ifc/nor");
 897
 898         if (offset < 0)
 899                 offset = fdt_path_offset(fdt, "/ifc/nor");
 900 #else
 901         offset = fdt_path_offset(fdt, "/soc/quadspi");
 902
 903         if (offset < 0)
 904                 offset = fdt_path_offset(fdt, "/quadspi");
 905 #endif
 906 #endif
 907         if (offset < 0)
 908                 return;
 909
 910         fdt_status_disabled(fdt, offset);
 911 }
 912
 913 int ft_board_setup(void *blob, bd_t *bd)
 914 {
 915         int i;
 916         u16 mc_memory_bank = 0;
 917
 918         u64 *base;
 919         u64 *size;
 920         u64 mc_memory_base = 0;
 921         u64 mc_memory_size = 0;
 922         u16 total_memory_banks;
 923
 924         ft_cpu_setup(blob, bd);
 925
 926         fdt_fixup_mc_ddr(&mc_memory_base, &mc_memory_size);
 927
 928         if (mc_memory_base != 0)
 929                 mc_memory_bank++;
 930
 931         total_memory_banks = CONFIG_NR_DRAM_BANKS + mc_memory_bank;
 932
 933         base = calloc(total_memory_banks, sizeof(u64));
 934         size = calloc(total_memory_banks, sizeof(u64));
 935
 936         /* fixup DT for the two GPP DDR banks */
 937         for (i = 0; i < CONFIG_NR_DRAM_BANKS; i++) {
 938                 base[i] = gd->bd->bi_dram[i].start;
 939                 size[i] = gd->bd->bi_dram[i].size;
 940         }
 941
 942 #ifdef CONFIG_RESV_RAM
 943         /* reduce size if reserved memory is within this bank */
 944         if (gd->arch.resv_ram >= base[0] &&
 945             gd->arch.resv_ram < base[0] + size[0])
 946                 size[0] = gd->arch.resv_ram - base[0];
 947         else if (gd->arch.resv_ram >= base[1] &&
 948                  gd->arch.resv_ram < base[1] + size[1])
 949                 size[1] = gd->arch.resv_ram - base[1];
 950 #endif
 951
 952         if (mc_memory_base != 0) {
 953                 for (i = 0; i <= total_memory_banks; i++) {
 954                         if (base[i] == 0 && size[i] == 0) {
 955                                 base[i] = mc_memory_base;
 956                                 size[i] = mc_memory_size;
 957                                 break;
 958                         }
 959                 }
 960         }
 961
 962         fdt_fixup_memory_banks(blob, base, size, total_memory_banks);
 963
 964         fdt_fsl_mc_fixup_iommu_map_entry(blob);
 965
 966         fsl_fdt_fixup_flash(blob);
 967
 968 #ifdef CONFIG_FSL_MC_ENET
 969         fdt_fixup_board_enet(blob);
 970 #endif
 971         if (is_pb_board())
 972                 fixup_ls1088ardb_pb_banner(blob);
 973
 974         return 0;
 975 }
 976 #endif
 977 #endif /* defined(CONFIG_SPL_BUILD) */
 978
 979 #ifdef CONFIG_TFABOOT
 980 #ifdef CONFIG_MTD_NOR_FLASH
 981 int is_flash_available(void)
 982 {
 983         char *env_hwconfig = env_get("hwconfig");
 984         enum boot_src src = get_boot_src();
 985         int is_nor_flash_available = 1;
 986
 987         switch (src) {
 988         case BOOT_SOURCE_IFC_NOR:
 989                 is_nor_flash_available = 1;
 990                 break;
 991         case BOOT_SOURCE_QSPI_NOR:
 992                 is_nor_flash_available = 0;
 993                 break;
 994         /*
 995          * In Case of SD boot,if qspi is defined in env_hwconfig
 996          * disable nor flash probe.
 997          */
 998         default:
 999                 if (hwconfig_f("qspi", env_hwconfig))
1000                         is_nor_flash_available = 0;
1001                 break;
1002         }
1003         return is_nor_flash_available;
1004 }
1005 #endif
1006
1007 void *env_sf_get_env_addr(void)
1008 {
1009         return (void *)(CONFIG_SYS_FSL_QSPI_BASE + CONFIG_ENV_OFFSET);
1010 }
1011 #endif