1 // SPDX-License-Identifier: GPL-2.0+
3 * Copyright 2017-2018 NXP
16 #include <asm/global_data.h>
18 #include <fdt_support.h>
19 #include <linux/delay.h>
20 #include <linux/libfdt.h>
21 #include <fsl-mc/fsl_mc.h>
22 #include <env_internal.h>
23 #include <asm/arch-fsl-layerscape/soc.h>
24 #include <asm/arch/ppa.h>
26 #include <asm/arch/fsl_serdes.h>
27 #include <asm/arch/soc.h>
28 #include <asm/arch-fsl-layerscape/fsl_icid.h>
29 #include "../common/i2c_mux.h"
31 #include "../common/qixis.h"
32 #include "ls1088a_qixis.h"
33 #include "../common/vid.h"
34 #include <fsl_immap.h>
36 DECLARE_GLOBAL_DATA_PTR;
38 #ifdef CONFIG_TARGET_LS1088AQDS
40 struct ifc_regs ifc_cfg_ifc_nor_boot[CONFIG_SYS_FSL_IFC_BANK_COUNT] = {
43 CONFIG_SYS_NOR0_CSPR_EARLY,
44 CONFIG_SYS_NOR0_CSPR_EXT,
59 CONFIG_SYS_NOR1_CSPR_EARLY,
60 CONFIG_SYS_NOR0_CSPR_EXT,
61 CONFIG_SYS_NOR_AMASK_EARLY,
76 CONFIG_SYS_NAND_CSPR_EXT,
77 CONFIG_SYS_NAND_AMASK,
80 CONFIG_SYS_NAND_FTIM0,
81 CONFIG_SYS_NAND_FTIM1,
82 CONFIG_SYS_NAND_FTIM2,
89 CONFIG_SYS_FPGA_CSPR_EXT,
104 struct ifc_regs ifc_cfg_qspi_nor_boot[CONFIG_SYS_FSL_IFC_BANK_COUNT] = {
107 CONFIG_SYS_NAND_CSPR,
108 CONFIG_SYS_NAND_CSPR_EXT,
109 CONFIG_SYS_NAND_AMASK,
110 CONFIG_SYS_NAND_CSOR,
112 CONFIG_SYS_NAND_FTIM0,
113 CONFIG_SYS_NAND_FTIM1,
114 CONFIG_SYS_NAND_FTIM2,
115 CONFIG_SYS_NAND_FTIM3
123 CONFIG_SYS_FPGA_CSPR,
124 CONFIG_SYS_FPGA_CSPR_EXT,
126 CONFIG_SYS_FPGA_CSOR,
139 void ifc_cfg_boot_info(struct ifc_regs_info *regs_info)
141 enum boot_src src = get_boot_src();
143 if (src == BOOT_SOURCE_QSPI_NOR)
144 regs_info->regs = ifc_cfg_qspi_nor_boot;
146 regs_info->regs = ifc_cfg_ifc_nor_boot;
148 regs_info->cs_size = CONFIG_SYS_FSL_IFC_BANK_COUNT;
150 #endif /* CONFIG_TFABOOT */
151 #endif /* CONFIG_TARGET_LS1088AQDS */
153 int board_early_init_f(void)
155 #if defined(CONFIG_SYS_I2C_EARLY_INIT) && defined(CONFIG_TARGET_LS1088AQDS)
158 fsl_lsch3_early_init_f();
162 #ifdef CONFIG_FSL_QIXIS
163 unsigned long long get_qixis_addr(void)
165 unsigned long long addr;
167 if (gd->flags & GD_FLG_RELOC)
168 addr = QIXIS_BASE_PHYS;
170 addr = QIXIS_BASE_PHYS_EARLY;
173 * IFC address under 256MB is mapped to 0x30000000, any address above
174 * is mapped to 0x5_10000000 up to 4GB.
176 addr = addr > 0x10000000 ? addr + 0x500000000ULL : addr + 0x30000000;
182 #if defined(CONFIG_VID)
183 int init_func_vid(void)
185 if (adjust_vdd(0) < 0)
186 printf("core voltage not adjusted\n");
191 u16 soc_get_fuse_vid(int vid_index)
193 static const u16 vdd[32] = {
228 return vdd[vid_index];
232 int is_pb_board(void)
236 board_id = QIXIS_READ(id);
237 if (board_id == LS1088ARDB_PB_BOARD)
243 int fixup_ls1088ardb_pb_banner(void *fdt)
245 fdt_setprop_string(fdt, 0, "model", "LS1088ARDB-PB Board");
250 #if !defined(CONFIG_SPL_BUILD)
253 #ifdef CONFIG_TFABOOT
254 enum boot_src src = get_boot_src();
258 static const char *const freq[] = {"100", "125", "156.25",
259 "100 separate SSCG"};
262 #ifdef CONFIG_TARGET_LS1088AQDS
263 printf("Board: LS1088A-QDS, ");
266 printf("Board: LS1088ARDB-PB, ");
268 printf("Board: LS1088A-RDB, ");
271 sw = QIXIS_READ(arch);
272 printf("Board Arch: V%d, ", sw >> 4);
274 #ifdef CONFIG_TARGET_LS1088AQDS
275 printf("Board version: %c, boot from ", (sw & 0xf) + 'A' - 1);
277 printf("Board version: %c, boot from ", (sw & 0xf) + 'A');
280 memset((u8 *)buf, 0x00, ARRAY_SIZE(buf));
282 sw = QIXIS_READ(brdcfg[0]);
283 sw = (sw & QIXIS_LBMAP_MASK) >> QIXIS_LBMAP_SHIFT;
285 #ifdef CONFIG_TFABOOT
286 if (src == BOOT_SOURCE_SD_MMC)
289 #ifdef CONFIG_SD_BOOT
292 #endif /* CONFIG_TFABOOT */
294 #ifdef CONFIG_TARGET_LS1088AQDS
303 printf("vBank: %d\n", sw);
316 sw = QIXIS_READ(brdcfg[0]);
317 sw = (sw & QIXIS_QMAP_MASK) >> QIXIS_QMAP_SHIFT;
318 if (sw == 0 || sw == 4)
327 printf("invalid setting of SW%u\n", QIXIS_LBMAP_SWITCH);
331 #ifdef CONFIG_TARGET_LS1088AQDS
332 printf("FPGA: v%d (%s), build %d",
333 (int)QIXIS_READ(scver), qixis_read_tag(buf),
334 (int)qixis_read_minor());
335 /* the timestamp string contains "\n" at the end */
336 printf(" on %s", qixis_read_time(buf));
338 printf("CPLD: v%d.%d\n", QIXIS_READ(scver), QIXIS_READ(tagdata));
342 * Display the actual SERDES reference clocks as configured by the
343 * dip switches on the board. Note that the SWx registers could
344 * technically be set to force the reference clocks to match the
345 * values that the SERDES expects (or vice versa). For now, however,
346 * we just display both values and hope the user notices when they
349 puts("SERDES1 Reference : ");
350 sw = QIXIS_READ(brdcfg[2]);
351 clock = (sw >> 6) & 3;
352 printf("Clock1 = %sMHz ", freq[clock]);
353 clock = (sw >> 4) & 3;
354 printf("Clock2 = %sMHz", freq[clock]);
356 puts("\nSERDES2 Reference : ");
357 clock = (sw >> 2) & 3;
358 printf("Clock1 = %sMHz ", freq[clock]);
359 clock = (sw >> 0) & 3;
360 printf("Clock2 = %sMHz\n", freq[clock]);
366 bool if_board_diff_clk(void)
368 #ifdef CONFIG_TARGET_LS1088AQDS
369 u8 diff_conf = QIXIS_READ(brdcfg[11]);
370 return diff_conf & 0x40;
372 u8 diff_conf = QIXIS_READ(dutcfg[11]);
373 return diff_conf & 0x80;
377 #ifdef CONFIG_DYNAMIC_SYS_CLK_FREQ
378 unsigned long get_board_sys_clk(void)
380 u8 sysclk_conf = QIXIS_READ(brdcfg[1]);
382 switch (sysclk_conf & 0x0f) {
383 case QIXIS_SYSCLK_83:
385 case QIXIS_SYSCLK_100:
387 case QIXIS_SYSCLK_125:
389 case QIXIS_SYSCLK_133:
391 case QIXIS_SYSCLK_150:
393 case QIXIS_SYSCLK_160:
395 case QIXIS_SYSCLK_166:
403 #ifdef CONFIG_DYNAMIC_DDR_CLK_FREQ
404 unsigned long get_board_ddr_clk(void)
406 u8 ddrclk_conf = QIXIS_READ(brdcfg[1]);
408 if (if_board_diff_clk())
409 return get_board_sys_clk();
410 switch ((ddrclk_conf & 0x30) >> 4) {
411 case QIXIS_DDRCLK_100:
413 case QIXIS_DDRCLK_125:
415 case QIXIS_DDRCLK_133:
423 #if !defined(CONFIG_SPL_BUILD)
424 void board_retimer_init(void)
428 /* Retimer is connected to I2C1_CH5 */
429 select_i2c_ch_pca9547(I2C_MUX_CH5, 0);
431 /* Access to Control/Shared register */
433 #if !CONFIG_IS_ENABLED(DM_I2C)
434 i2c_write(I2C_RETIMER_ADDR, 0xff, 1, ®, 1);
438 i2c_get_chip_for_busnum(0, I2C_RETIMER_ADDR, 1, &dev);
439 dm_i2c_write(dev, 0xff, ®, 1);
442 /* Read device revision and ID */
443 #if !CONFIG_IS_ENABLED(DM_I2C)
444 i2c_read(I2C_RETIMER_ADDR, 1, 1, ®, 1);
446 dm_i2c_read(dev, 1, ®, 1);
448 debug("Retimer version id = 0x%x\n", reg);
450 /* Enable Broadcast. All writes target all channel register sets */
452 #if !CONFIG_IS_ENABLED(DM_I2C)
453 i2c_write(I2C_RETIMER_ADDR, 0xff, 1, ®, 1);
455 dm_i2c_write(dev, 0xff, ®, 1);
458 /* Reset Channel Registers */
459 #if !CONFIG_IS_ENABLED(DM_I2C)
460 i2c_read(I2C_RETIMER_ADDR, 0, 1, ®, 1);
462 dm_i2c_read(dev, 0, ®, 1);
465 #if !CONFIG_IS_ENABLED(DM_I2C)
466 i2c_write(I2C_RETIMER_ADDR, 0, 1, ®, 1);
468 dm_i2c_write(dev, 0, ®, 1);
471 /* Set data rate as 10.3125 Gbps */
473 #if !CONFIG_IS_ENABLED(DM_I2C)
474 i2c_write(I2C_RETIMER_ADDR, 0x60, 1, ®, 1);
476 dm_i2c_write(dev, 0x60, ®, 1);
479 #if !CONFIG_IS_ENABLED(DM_I2C)
480 i2c_write(I2C_RETIMER_ADDR, 0x61, 1, ®, 1);
482 dm_i2c_write(dev, 0x61, ®, 1);
485 #if !CONFIG_IS_ENABLED(DM_I2C)
486 i2c_write(I2C_RETIMER_ADDR, 0x62, 1, ®, 1);
488 dm_i2c_write(dev, 0x62, ®, 1);
491 #if !CONFIG_IS_ENABLED(DM_I2C)
492 i2c_write(I2C_RETIMER_ADDR, 0x63, 1, ®, 1);
494 dm_i2c_write(dev, 0x63, ®, 1);
497 #if !CONFIG_IS_ENABLED(DM_I2C)
498 i2c_write(I2C_RETIMER_ADDR, 0x64, 1, ®, 1);
500 dm_i2c_write(dev, 0x64, ®, 1);
503 /* Select VCO Divider to full rate (000) */
504 #if !CONFIG_IS_ENABLED(DM_I2C)
505 i2c_read(I2C_RETIMER_ADDR, 0x2F, 1, ®, 1);
507 dm_i2c_read(dev, 0x2F, ®, 1);
511 #if !CONFIG_IS_ENABLED(DM_I2C)
512 i2c_write(I2C_RETIMER_ADDR, 0x2F, 1, ®, 1);
514 dm_i2c_write(dev, 0x2F, ®, 1);
517 #ifdef CONFIG_TARGET_LS1088AQDS
518 /* Retimer is connected to I2C1_CH5 */
519 select_i2c_ch_pca9547(I2C_MUX_CH5, 0);
521 /* Access to Control/Shared register */
523 #if !CONFIG_IS_ENABLED(DM_I2C)
524 i2c_write(I2C_RETIMER_ADDR2, 0xff, 1, ®, 1);
526 i2c_get_chip_for_busnum(0, I2C_RETIMER_ADDR2, 1, &dev);
527 dm_i2c_write(dev, 0xff, ®, 1);
530 /* Read device revision and ID */
531 #if !CONFIG_IS_ENABLED(DM_I2C)
532 i2c_read(I2C_RETIMER_ADDR2, 1, 1, ®, 1);
534 dm_i2c_read(dev, 1, ®, 1);
536 debug("Retimer version id = 0x%x\n", reg);
538 /* Enable Broadcast. All writes target all channel register sets */
540 #if !CONFIG_IS_ENABLED(DM_I2C)
541 i2c_write(I2C_RETIMER_ADDR2, 0xff, 1, ®, 1);
543 dm_i2c_write(dev, 0xff, ®, 1);
546 /* Reset Channel Registers */
547 #if !CONFIG_IS_ENABLED(DM_I2C)
548 i2c_read(I2C_RETIMER_ADDR2, 0, 1, ®, 1);
550 dm_i2c_read(dev, 0, ®, 1);
553 #if !CONFIG_IS_ENABLED(DM_I2C)
554 i2c_write(I2C_RETIMER_ADDR2, 0, 1, ®, 1);
556 dm_i2c_write(dev, 0, ®, 1);
559 /* Set data rate as 10.3125 Gbps */
561 #if !CONFIG_IS_ENABLED(DM_I2C)
562 i2c_write(I2C_RETIMER_ADDR2, 0x60, 1, ®, 1);
564 dm_i2c_write(dev, 0x60, ®, 1);
567 #if !CONFIG_IS_ENABLED(DM_I2C)
568 i2c_write(I2C_RETIMER_ADDR2, 0x61, 1, ®, 1);
570 dm_i2c_write(dev, 0x61, ®, 1);
573 #if !CONFIG_IS_ENABLED(DM_I2C)
574 i2c_write(I2C_RETIMER_ADDR2, 0x62, 1, ®, 1);
576 dm_i2c_write(dev, 0x62, ®, 1);
579 #if !CONFIG_IS_ENABLED(DM_I2C)
580 i2c_write(I2C_RETIMER_ADDR2, 0x63, 1, ®, 1);
582 dm_i2c_write(dev, 0x63, ®, 1);
585 #if !CONFIG_IS_ENABLED(DM_I2C)
586 i2c_write(I2C_RETIMER_ADDR2, 0x64, 1, ®, 1);
588 dm_i2c_write(dev, 0x64, ®, 1);
591 /* Select VCO Divider to full rate (000) */
592 #if !CONFIG_IS_ENABLED(DM_I2C)
593 i2c_read(I2C_RETIMER_ADDR2, 0x2F, 1, ®, 1);
595 dm_i2c_read(dev, 0x2F, ®, 1);
599 #if !CONFIG_IS_ENABLED(DM_I2C)
600 i2c_write(I2C_RETIMER_ADDR2, 0x2F, 1, ®, 1);
602 dm_i2c_write(dev, 0x2F, ®, 1);
606 /*return the default channel*/
607 select_i2c_ch_pca9547(I2C_MUX_CH_DEFAULT, 0);
610 #ifdef CONFIG_MISC_INIT_R
611 int misc_init_r(void)
613 #ifdef CONFIG_TARGET_LS1088ARDB
616 if (hwconfig("esdhc-force-sd")) {
617 brdcfg5 = QIXIS_READ(brdcfg[5]);
618 brdcfg5 &= ~BRDCFG5_SPISDHC_MASK;
619 brdcfg5 |= BRDCFG5_FORCE_SD;
620 QIXIS_WRITE(brdcfg[5], brdcfg5);
624 #ifdef CONFIG_TARGET_LS1088AQDS
627 if (hwconfig("dspi-on-board")) {
628 brdcfg4 = QIXIS_READ(brdcfg[4]);
629 brdcfg4 &= ~BRDCFG4_USBOSC_MASK;
630 brdcfg4 |= BRDCFG4_SPI;
631 QIXIS_WRITE(brdcfg[4], brdcfg4);
633 brdcfg5 = QIXIS_READ(brdcfg[5]);
634 brdcfg5 &= ~BRDCFG5_SPR_MASK;
635 brdcfg5 |= BRDCFG5_SPI_ON_BOARD;
636 QIXIS_WRITE(brdcfg[5], brdcfg5);
637 } else if (hwconfig("dspi-off-board")) {
638 brdcfg4 = QIXIS_READ(brdcfg[4]);
639 brdcfg4 &= ~BRDCFG4_USBOSC_MASK;
640 brdcfg4 |= BRDCFG4_SPI;
641 QIXIS_WRITE(brdcfg[4], brdcfg4);
643 brdcfg5 = QIXIS_READ(brdcfg[5]);
644 brdcfg5 &= ~BRDCFG5_SPR_MASK;
645 brdcfg5 |= BRDCFG5_SPI_OFF_BOARD;
646 QIXIS_WRITE(brdcfg[5], brdcfg5);
654 int i2c_multiplexer_select_vid_channel(u8 channel)
656 return select_i2c_ch_pca9547(channel, 0);
659 #ifdef CONFIG_TARGET_LS1088AQDS
660 /* read the current value(SVDD) of the LTM Regulator Voltage */
661 int get_serdes_volt(void)
664 u8 chan = PWM_CHANNEL0;
666 /* Select the PAGE 0 using PMBus commands PAGE for VDD */
667 #if !CONFIG_IS_ENABLED(DM_I2C)
668 ret = i2c_write(I2C_SVDD_MONITOR_ADDR,
669 PMBUS_CMD_PAGE, 1, &chan, 1);
673 ret = i2c_get_chip_for_busnum(0, I2C_SVDD_MONITOR_ADDR, 1, &dev);
675 ret = dm_i2c_write(dev, PMBUS_CMD_PAGE,
680 printf("VID: failed to select VDD Page 0\n");
684 /* Read the output voltage using PMBus command READ_VOUT */
685 #if !CONFIG_IS_ENABLED(DM_I2C)
686 ret = i2c_read(I2C_SVDD_MONITOR_ADDR,
687 PMBUS_CMD_READ_VOUT, 1, (void *)&vcode, 2);
689 dm_i2c_read(dev, PMBUS_CMD_READ_VOUT, (void *)&vcode, 2);
692 printf("VID: failed to read the volatge\n");
699 int set_serdes_volt(int svdd)
702 u8 buff[5] = {0x04, PWM_CHANNEL0, PMBUS_CMD_VOUT_COMMAND,
703 svdd & 0xFF, (svdd & 0xFF00) >> 8};
705 /* Write the desired voltage code to the SVDD regulator */
706 #if !CONFIG_IS_ENABLED(DM_I2C)
707 ret = i2c_write(I2C_SVDD_MONITOR_ADDR,
708 PMBUS_CMD_PAGE_PLUS_WRITE, 1, (void *)&buff, 5);
712 ret = i2c_get_chip_for_busnum(0, I2C_SVDD_MONITOR_ADDR, 1, &dev);
714 ret = dm_i2c_write(dev, PMBUS_CMD_PAGE_PLUS_WRITE,
718 printf("VID: I2C failed to write to the volatge regulator\n");
722 /* Wait for the volatge to get to the desired value */
724 vdd_last = get_serdes_volt();
726 printf("VID: Couldn't read sensor abort VID adjust\n");
729 } while (vdd_last != svdd);
734 int get_serdes_volt(void)
739 int set_serdes_volt(int svdd)
744 printf("SVDD changing of RDB\n");
746 /* Read the BRDCFG54 via CLPD */
747 #if !CONFIG_IS_ENABLED(DM_I2C)
748 ret = i2c_read(CONFIG_SYS_I2C_FPGA_ADDR,
749 QIXIS_BRDCFG4_OFFSET, 1, (void *)&brdcfg4, 1);
753 ret = i2c_get_chip_for_busnum(0, CONFIG_SYS_I2C_FPGA_ADDR, 1, &dev);
755 ret = dm_i2c_read(dev, QIXIS_BRDCFG4_OFFSET,
756 (void *)&brdcfg4, 1);
760 printf("VID: I2C failed to read the CPLD BRDCFG4\n");
764 brdcfg4 = brdcfg4 | 0x08;
766 /* Write to the BRDCFG4 */
767 #if !CONFIG_IS_ENABLED(DM_I2C)
768 ret = i2c_write(CONFIG_SYS_I2C_FPGA_ADDR,
769 QIXIS_BRDCFG4_OFFSET, 1, (void *)&brdcfg4, 1);
771 ret = dm_i2c_write(dev, QIXIS_BRDCFG4_OFFSET,
772 (void *)&brdcfg4, 1);
776 debug("VID: I2C failed to set the SVDD CPLD BRDCFG4\n");
780 /* Wait for the volatge to get to the desired value */
787 /* this function disables the SERDES, changes the SVDD Voltage and enables it*/
788 int board_adjust_vdd(int vdd)
792 debug("%s: vdd = %d\n", __func__, vdd);
794 /* Special settings to be performed when voltage is 900mV */
796 ret = setup_serdes_volt(vdd);
806 #if !defined(CONFIG_SPL_BUILD)
809 init_final_memctl_regs();
810 #if defined(CONFIG_TARGET_LS1088ARDB) && defined(CONFIG_FSL_MC_ENET)
811 u32 __iomem *irq_ccsr = (u32 __iomem *)ISC_BASE;
814 select_i2c_ch_pca9547(I2C_MUX_CH_DEFAULT, 0);
815 board_retimer_init();
817 #if defined(CONFIG_TARGET_LS1088ARDB) && defined(CONFIG_FSL_MC_ENET)
818 /* invert AQR105 IRQ pins polarity */
819 out_le32(irq_ccsr + IRQCR_OFFSET / 4, AQR105_IRQ_MASK);
822 #ifdef CONFIG_FSL_CAAM
825 #ifdef CONFIG_FSL_LS_PPA
829 #if !defined(CONFIG_SYS_EARLY_PCI_INIT) && defined(CONFIG_DM_ETH)
836 void detail_board_ddr_info(void)
839 print_size(gd->bd->bi_dram[0].size + gd->bd->bi_dram[1].size, "");
843 #ifdef CONFIG_FSL_MC_ENET
844 void board_quiesce_devices(void)
846 fsl_mc_ldpaa_exit(gd->bd);
849 void fdt_fixup_board_enet(void *fdt)
853 offset = fdt_path_offset(fdt, "/fsl-mc");
856 offset = fdt_path_offset(fdt, "/soc/fsl-mc");
859 printf("%s: ERROR: fsl-mc node not found in device tree (error %d)\n",
864 if (get_mc_boot_status() == 0 &&
865 (is_lazy_dpl_addr_valid() || get_dpl_apply_status() == 0))
866 fdt_status_okay(fdt, offset);
868 fdt_status_fail(fdt, offset);
872 #ifdef CONFIG_OF_BOARD_SETUP
873 void fsl_fdt_fixup_flash(void *fdt)
876 #ifdef CONFIG_TFABOOT
877 u32 __iomem *dcfg_ccsr = (u32 __iomem *)DCFG_BASE;
882 * IFC-NOR and QSPI are muxed on SoC.
883 * So disable IFC node in dts if QSPI is enabled or
884 * disable QSPI node in dts in case QSPI is not enabled.
887 #ifdef CONFIG_TFABOOT
888 enum boot_src src = get_boot_src();
889 bool disable_ifc = false;
892 case BOOT_SOURCE_IFC_NOR:
895 case BOOT_SOURCE_QSPI_NOR:
899 val = in_le32(dcfg_ccsr + DCFG_RCWSR15 / 4);
900 if (DCFG_RCWSR15_IFCGRPABASE_QSPI == (val & (u32)0x3))
906 offset = fdt_path_offset(fdt, "/soc/ifc/nor");
909 offset = fdt_path_offset(fdt, "/ifc/nor");
911 offset = fdt_path_offset(fdt, "/soc/quadspi");
914 offset = fdt_path_offset(fdt, "/quadspi");
918 #ifdef CONFIG_FSL_QSPI
919 offset = fdt_path_offset(fdt, "/soc/ifc/nor");
922 offset = fdt_path_offset(fdt, "/ifc/nor");
924 offset = fdt_path_offset(fdt, "/soc/quadspi");
927 offset = fdt_path_offset(fdt, "/quadspi");
933 fdt_status_disabled(fdt, offset);
936 int ft_board_setup(void *blob, struct bd_info *bd)
939 u16 mc_memory_bank = 0;
943 u64 mc_memory_base = 0;
944 u64 mc_memory_size = 0;
945 u16 total_memory_banks;
947 ft_cpu_setup(blob, bd);
949 fdt_fixup_mc_ddr(&mc_memory_base, &mc_memory_size);
951 if (mc_memory_base != 0)
954 total_memory_banks = CONFIG_NR_DRAM_BANKS + mc_memory_bank;
956 base = calloc(total_memory_banks, sizeof(u64));
957 size = calloc(total_memory_banks, sizeof(u64));
959 /* fixup DT for the two GPP DDR banks */
960 for (i = 0; i < CONFIG_NR_DRAM_BANKS; i++) {
961 base[i] = gd->bd->bi_dram[i].start;
962 size[i] = gd->bd->bi_dram[i].size;
965 #ifdef CONFIG_RESV_RAM
966 /* reduce size if reserved memory is within this bank */
967 if (gd->arch.resv_ram >= base[0] &&
968 gd->arch.resv_ram < base[0] + size[0])
969 size[0] = gd->arch.resv_ram - base[0];
970 else if (gd->arch.resv_ram >= base[1] &&
971 gd->arch.resv_ram < base[1] + size[1])
972 size[1] = gd->arch.resv_ram - base[1];
975 if (mc_memory_base != 0) {
976 for (i = 0; i <= total_memory_banks; i++) {
977 if (base[i] == 0 && size[i] == 0) {
978 base[i] = mc_memory_base;
979 size[i] = mc_memory_size;
985 fdt_fixup_memory_banks(blob, base, size, total_memory_banks);
987 fdt_fsl_mc_fixup_iommu_map_entry(blob);
989 fsl_fdt_fixup_flash(blob);
991 #ifdef CONFIG_FSL_MC_ENET
992 fdt_fixup_board_enet(blob);
995 fdt_fixup_icid(blob);
998 fixup_ls1088ardb_pb_banner(blob);
1003 #endif /* defined(CONFIG_SPL_BUILD) */
1005 #ifdef CONFIG_TFABOOT
1006 #ifdef CONFIG_MTD_NOR_FLASH
1007 int is_flash_available(void)
1009 char *env_hwconfig = env_get("hwconfig");
1010 enum boot_src src = get_boot_src();
1011 int is_nor_flash_available = 1;
1014 case BOOT_SOURCE_IFC_NOR:
1015 is_nor_flash_available = 1;
1017 case BOOT_SOURCE_QSPI_NOR:
1018 is_nor_flash_available = 0;
1021 * In Case of SD boot,if qspi is defined in env_hwconfig
1022 * disable nor flash probe.
1025 if (hwconfig_f("qspi", env_hwconfig))
1026 is_nor_flash_available = 0;
1029 return is_nor_flash_available;
1033 #ifdef CONFIG_ENV_IS_IN_SPI_FLASH
1034 void *env_sf_get_env_addr(void)
1036 return (void *)(CONFIG_SYS_FSL_QSPI_BASE + CONFIG_ENV_OFFSET);